1 /** 2 * @file rtc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_RTC_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_RTC_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup rtc 66 * @defgroup rtc_registers RTC_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 68 * @details Real Time Clock and Alarm. 69 */ 70 71 /** 72 * @ingroup rtc_registers 73 * Structure type to access the RTC Registers. 74 */ 75 typedef struct { 76 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */ 77 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */ 78 __IO uint32_t toda; /**< <tt>\b 0x08:</tt> RTC TODA Register */ 79 __IO uint32_t sseca; /**< <tt>\b 0x0C:</tt> RTC SSECA Register */ 80 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */ 81 __IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */ 82 __IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */ 83 } mxc_rtc_regs_t; 84 85 /* Register offsets for module RTC */ 86 /** 87 * @ingroup rtc_registers 88 * @defgroup RTC_Register_Offsets Register Offsets 89 * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ 98 #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 99 /**@} end of group rtc_registers */ 100 101 /** 102 * @ingroup rtc_registers 103 * @defgroup RTC_SEC RTC_SEC 104 * @brief RTC Second Counter. This register contains the 32-bit second counter. 105 * @{ 106 */ 107 #define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ 108 #define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ 109 110 /**@} end of group RTC_SEC_Register */ 111 112 /** 113 * @ingroup rtc_registers 114 * @defgroup RTC_SSEC RTC_SSEC 115 * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented 116 * when this register rolls over from 0xFF to 0x00. 117 * @{ 118 */ 119 #define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ 120 #define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ 121 122 /**@} end of group RTC_SSEC_Register */ 123 124 /** 125 * @ingroup rtc_registers 126 * @defgroup RTC_TODA RTC_TODA 127 * @brief Time-of-day Alarm. 128 * @{ 129 */ 130 #define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ 131 #define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ 132 133 /**@} end of group RTC_TODA_Register */ 134 135 /** 136 * @ingroup rtc_registers 137 * @defgroup RTC_SSECA RTC_SSECA 138 * @brief RTC sub-second alarm. This register contains the reload value for the sub- 139 * second alarm. 140 * @{ 141 */ 142 #define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ 143 #define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ 144 145 /**@} end of group RTC_SSECA_Register */ 146 147 /** 148 * @ingroup rtc_registers 149 * @defgroup RTC_CTRL RTC_CTRL 150 * @brief RTC Control Register. 151 * @{ 152 */ 153 #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ 154 #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ 155 156 #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ 157 #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ 158 159 #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ 160 #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ 161 162 #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 163 #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 164 165 #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 166 #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 167 168 #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ 169 #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ 170 171 #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ 172 #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ 173 174 #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ 175 #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ 176 177 #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ 178 #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ 179 180 #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ 181 #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ 182 #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ 183 #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ 184 #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ 185 #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ 186 #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ 187 #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ 188 189 #define MXC_F_RTC_CTRL_ACRE_POS 14 /**< CTRL_ACRE Position */ 190 #define MXC_F_RTC_CTRL_ACRE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ACRE_POS)) /**< CTRL_ACRE Mask */ 191 192 #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ 193 #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ 194 195 /**@} end of group RTC_CTRL_Register */ 196 197 /** 198 * @ingroup rtc_registers 199 * @defgroup RTC_TRIM RTC_TRIM 200 * @brief RTC Trim Register. 201 * @{ 202 */ 203 #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ 204 #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ 205 206 #define MXC_F_RTC_TRIM_COUNT_POS 8 /**< TRIM_COUNT Position */ 207 #define MXC_F_RTC_TRIM_COUNT ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_COUNT_POS)) /**< TRIM_COUNT Mask */ 208 209 /**@} end of group RTC_TRIM_Register */ 210 211 /** 212 * @ingroup rtc_registers 213 * @defgroup RTC_OSCCTRL RTC_OSCCTRL 214 * @brief RTC Oscillator Control Register. 215 * @{ 216 */ 217 #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ 218 #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ 219 220 #define MXC_F_RTC_OSCCTRL_32KOUT_POS 5 /**< OSCCTRL_32KOUT Position */ 221 #define MXC_F_RTC_OSCCTRL_32KOUT ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_32KOUT_POS)) /**< OSCCTRL_32KOUT Mask */ 222 223 /**@} end of group RTC_OSCCTRL_Register */ 224 225 #ifdef __cplusplus 226 } 227 #endif 228 229 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_RTC_REGS_H_ 230
