1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_PWRSEQ_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_PWRSEQ_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup pwrseq 66 * @defgroup pwrseq_registers PWRSEQ_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 68 * @details Power Sequencer / Low Power Control Register. 69 */ 70 71 /** 72 * @ingroup pwrseq_registers 73 * Structure type to access the PWRSEQ Registers. 74 */ 75 typedef struct { 76 __IO uint32_t lpcn; /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */ 77 __IO uint32_t lpwkst0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */ 78 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 79 __IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */ 80 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 81 __IO uint32_t lpwkst2; /**< <tt>\b 0x14:</tt> PWRSEQ LPWKST2 Register */ 82 __IO uint32_t lpwken2; /**< <tt>\b 0x18:</tt> PWRSEQ LPWKEN2 Register */ 83 __IO uint32_t lpwkst3; /**< <tt>\b 0x1C:</tt> PWRSEQ LPWKST3 Register */ 84 __IO uint32_t lpwken3; /**< <tt>\b 0x20:</tt> PWRSEQ LPWKEN3 Register */ 85 __R uint32_t rsv_0x24_0x2f[3]; 86 __IO uint32_t lppwkst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKST Register */ 87 __IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */ 88 __R uint32_t rsv_0x38_0x3f[2]; 89 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 90 __IO uint32_t lpvddpd; /**< <tt>\b 0x44:</tt> PWRSEQ LPVDDPD Register */ 91 __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */ 92 __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */ 93 } mxc_pwrseq_regs_t; 94 95 /* Register offsets for module PWRSEQ */ 96 /** 97 * @ingroup pwrseq_registers 98 * @defgroup PWRSEQ_Register_Offsets Register Offsets 99 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 100 * @{ 101 */ 102 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 103 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 104 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 105 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 106 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 107 #define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */ 108 #define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */ 109 #define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */ 110 #define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */ 111 #define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 112 #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 113 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 114 #define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0044</tt> */ 115 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 116 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 117 /**@} end of group pwrseq_registers */ 118 119 /** 120 * @ingroup pwrseq_registers 121 * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN 122 * @brief Low Power Control Register. 123 * @{ 124 */ 125 #define MXC_F_PWRSEQ_LPCN_RAMRET_EN_POS 0 /**< LPCN_RAMRET_EN Position */ 126 #define MXC_F_PWRSEQ_LPCN_RAMRET_EN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_EN_POS)) /**< LPCN_RAMRET_EN Mask */ 127 128 #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */ 129 #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */ 130 #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */ 131 #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */ 132 #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */ 133 #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */ 134 #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */ 135 #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */ 136 137 #define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */ 138 #define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */ 139 140 #define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */ 141 #define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */ 142 143 #define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */ 144 #define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */ 145 146 #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */ 147 #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */ 148 149 #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ 150 #define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ 151 152 #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ 153 #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ 154 155 #define MXC_F_PWRSEQ_LPCN_VRTCMON_DIS_POS 21 /**< LPCN_VRTCMON_DIS Position */ 156 #define MXC_F_PWRSEQ_LPCN_VRTCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRTCMON_DIS_POS)) /**< LPCN_VRTCMON_DIS Mask */ 157 158 #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ 159 #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ 160 161 #define MXC_F_PWRSEQ_LPCN_VDDIOMON_DIS_POS 23 /**< LPCN_VDDIOMON_DIS Position */ 162 #define MXC_F_PWRSEQ_LPCN_VDDIOMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMON_DIS_POS)) /**< LPCN_VDDIOMON_DIS Mask */ 163 164 #define MXC_F_PWRSEQ_LPCN_VDDIOHMON_DIS_POS 24 /**< LPCN_VDDIOHMON_DIS Position */ 165 #define MXC_F_PWRSEQ_LPCN_VDDIOHMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMON_DIS_POS)) /**< LPCN_VDDIOHMON_DIS Mask */ 166 167 #define MXC_F_PWRSEQ_LPCN_PORVDDBMON_DIS_POS 27 /**< LPCN_PORVDDBMON_DIS Position */ 168 #define MXC_F_PWRSEQ_LPCN_PORVDDBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDBMON_DIS_POS)) /**< LPCN_PORVDDBMON_DIS Mask */ 169 170 /**@} end of group PWRSEQ_LPCN_Register */ 171 172 /** 173 * @ingroup pwrseq_registers 174 * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 175 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 176 * wakeup status for GPIO0. 177 * @{ 178 */ 179 #define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ 180 #define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ 181 182 /**@} end of group PWRSEQ_LPWKST0_Register */ 183 184 /** 185 * @ingroup pwrseq_registers 186 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 187 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 188 * functionality for GPIO0. 189 * @{ 190 */ 191 #define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ 192 #define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ 193 194 /**@} end of group PWRSEQ_LPWKEN0_Register */ 195 196 /** 197 * @ingroup pwrseq_registers 198 * @defgroup PWRSEQ_LPPWKST PWRSEQ_LPPWKST 199 * @brief Low Power Peripheral Wakeup Status Register. 200 * @{ 201 */ 202 #define MXC_F_PWRSEQ_LPPWKST_USBLS_POS 0 /**< LPPWKST_USBLS Position */ 203 #define MXC_F_PWRSEQ_LPPWKST_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKST_USBLS_POS)) /**< LPPWKST_USBLS Mask */ 204 205 #define MXC_F_PWRSEQ_LPPWKST_USBVBUS_POS 2 /**< LPPWKST_USBVBUS Position */ 206 #define MXC_F_PWRSEQ_LPPWKST_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_USBVBUS_POS)) /**< LPPWKST_USBVBUS Mask */ 207 208 #define MXC_F_PWRSEQ_LPPWKST_HA0_POS 3 /**< LPPWKST_HA0 Position */ 209 #define MXC_F_PWRSEQ_LPPWKST_HA0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_HA0_POS)) /**< LPPWKST_HA0 Mask */ 210 211 #define MXC_F_PWRSEQ_LPPWKST_BBMOD_POS 16 /**< LPPWKST_BBMOD Position */ 212 #define MXC_F_PWRSEQ_LPPWKST_BBMOD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_BBMOD_POS)) /**< LPPWKST_BBMOD Mask */ 213 214 #define MXC_F_PWRSEQ_LPPWKST_RST_POS 17 /**< LPPWKST_RST Position */ 215 #define MXC_F_PWRSEQ_LPPWKST_RST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_RST_POS)) /**< LPPWKST_RST Mask */ 216 217 #define MXC_F_PWRSEQ_LPPWKST_SDMA1_POS 18 /**< LPPWKST_SDMA1 Position */ 218 #define MXC_F_PWRSEQ_LPPWKST_SDMA1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_SDMA1_POS)) /**< LPPWKST_SDMA1 Mask */ 219 220 /**@} end of group PWRSEQ_LPPWKST_Register */ 221 222 /** 223 * @ingroup pwrseq_registers 224 * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN 225 * @brief Low Power Peripheral Wakeup Enable Register. 226 * @{ 227 */ 228 #define MXC_F_PWRSEQ_LPPWKEN_USBLS_POS 0 /**< LPPWKEN_USBLS Position */ 229 #define MXC_F_PWRSEQ_LPPWKEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKEN_USBLS_POS)) /**< LPPWKEN_USBLS Mask */ 230 231 #define MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS 2 /**< LPPWKEN_USBVBUS Position */ 232 #define MXC_F_PWRSEQ_LPPWKEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS)) /**< LPPWKEN_USBVBUS Mask */ 233 234 #define MXC_F_PWRSEQ_LPPWKEN_SDMA0_POS 3 /**< LPPWKEN_SDMA0 Position */ 235 #define MXC_F_PWRSEQ_LPPWKEN_SDMA0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_SDMA0_POS)) /**< LPPWKEN_SDMA0 Mask */ 236 237 #define MXC_F_PWRSEQ_LPPWKEN_SDMA1_POS 18 /**< LPPWKEN_SDMA1 Position */ 238 #define MXC_F_PWRSEQ_LPPWKEN_SDMA1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_SDMA1_POS)) /**< LPPWKEN_SDMA1 Mask */ 239 240 /**@} end of group PWRSEQ_LPPWKEN_Register */ 241 242 /** 243 * @ingroup pwrseq_registers 244 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 245 * @brief Low Power Memory Shutdown Control. 246 * @{ 247 */ 248 #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ 249 #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ 250 251 #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ 252 #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ 253 254 #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ 255 #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ 256 257 #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ 258 #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ 259 260 #define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS 4 /**< LPMEMSD_RAM4 Position */ 261 #define MXC_F_PWRSEQ_LPMEMSD_RAM4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) /**< LPMEMSD_RAM4 Mask */ 262 263 #define MXC_F_PWRSEQ_LPMEMSD_RAM5_POS 5 /**< LPMEMSD_RAM5 Position */ 264 #define MXC_F_PWRSEQ_LPMEMSD_RAM5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM5_POS)) /**< LPMEMSD_RAM5 Mask */ 265 266 #define MXC_F_PWRSEQ_LPMEMSD_ICACHE_POS 7 /**< LPMEMSD_ICACHE Position */ 267 #define MXC_F_PWRSEQ_LPMEMSD_ICACHE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHE_POS)) /**< LPMEMSD_ICACHE Mask */ 268 269 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP_POS 8 /**< LPMEMSD_ICACHEXIP Position */ 270 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP_POS)) /**< LPMEMSD_ICACHEXIP Mask */ 271 272 #define MXC_F_PWRSEQ_LPMEMSD_SRCC_POS 9 /**< LPMEMSD_SRCC Position */ 273 #define MXC_F_PWRSEQ_LPMEMSD_SRCC ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCC_POS)) /**< LPMEMSD_SRCC Mask */ 274 275 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS 11 /**< LPMEMSD_USBFIFO Position */ 276 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS)) /**< LPMEMSD_USBFIFO Mask */ 277 278 #define MXC_F_PWRSEQ_LPMEMSD_ROM_POS 12 /**< LPMEMSD_ROM Position */ 279 #define MXC_F_PWRSEQ_LPMEMSD_ROM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM_POS)) /**< LPMEMSD_ROM Mask */ 280 281 /**@} end of group PWRSEQ_LPMEMSD_Register */ 282 283 #ifdef __cplusplus 284 } 285 #endif 286 287 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_PWRSEQ_REGS_H_ 288
