1 /** 2 * @file ptg_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_PTG_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_PTG_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup ptg 66 * @defgroup ptg_registers PTG_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 68 * @details Pulse Train Generation 69 */ 70 71 /** 72 * @ingroup ptg_registers 73 * Structure type to access the PTG Registers. 74 */ 75 typedef struct { 76 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG ENABLE Register */ 77 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG RESYNC Register */ 78 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> PTG INTFL Register */ 79 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> PTG INTEN Register */ 80 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG SAFE_EN Register */ 81 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG SAFE_DIS Register */ 82 } mxc_ptg_regs_t; 83 84 /* Register offsets for module PTG */ 85 /** 86 * @ingroup ptg_registers 87 * @defgroup PTG_Register_Offsets Register Offsets 88 * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_PTG_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_PTG_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: <tt> 0x0010</tt> */ 96 #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: <tt> 0x0014</tt> */ 97 /**@} end of group ptg_registers */ 98 99 /** 100 * @ingroup ptg_registers 101 * @defgroup PTG_ENABLE PTG_ENABLE 102 * @brief Global Enable/Disable Controls for All Pulse Trains 103 * @{ 104 */ 105 #define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 106 #define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 107 108 #define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 109 #define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 110 111 #define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 112 #define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 113 114 #define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 115 #define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 116 117 #define MXC_F_PTG_ENABLE_PT4_POS 4 /**< ENABLE_PT4 Position */ 118 #define MXC_F_PTG_ENABLE_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT4_POS)) /**< ENABLE_PT4 Mask */ 119 120 #define MXC_F_PTG_ENABLE_PT5_POS 5 /**< ENABLE_PT5 Position */ 121 #define MXC_F_PTG_ENABLE_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT5_POS)) /**< ENABLE_PT5 Mask */ 122 123 #define MXC_F_PTG_ENABLE_PT6_POS 6 /**< ENABLE_PT6 Position */ 124 #define MXC_F_PTG_ENABLE_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT6_POS)) /**< ENABLE_PT6 Mask */ 125 126 #define MXC_F_PTG_ENABLE_PT7_POS 7 /**< ENABLE_PT7 Position */ 127 #define MXC_F_PTG_ENABLE_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT7_POS)) /**< ENABLE_PT7 Mask */ 128 129 /**@} end of group PTG_ENABLE_Register */ 130 131 /** 132 * @ingroup ptg_registers 133 * @defgroup PTG_RESYNC PTG_RESYNC 134 * @brief Global Resync (All Pulse Trains) Control 135 * @{ 136 */ 137 #define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 138 #define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 139 140 #define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 141 #define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 142 143 #define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 144 #define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 145 146 #define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 147 #define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 148 149 #define MXC_F_PTG_RESYNC_PT4_POS 4 /**< RESYNC_PT4 Position */ 150 #define MXC_F_PTG_RESYNC_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT4_POS)) /**< RESYNC_PT4 Mask */ 151 152 #define MXC_F_PTG_RESYNC_PT5_POS 5 /**< RESYNC_PT5 Position */ 153 #define MXC_F_PTG_RESYNC_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT5_POS)) /**< RESYNC_PT5 Mask */ 154 155 #define MXC_F_PTG_RESYNC_PT6_POS 6 /**< RESYNC_PT6 Position */ 156 #define MXC_F_PTG_RESYNC_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT6_POS)) /**< RESYNC_PT6 Mask */ 157 158 #define MXC_F_PTG_RESYNC_PT7_POS 7 /**< RESYNC_PT7 Position */ 159 #define MXC_F_PTG_RESYNC_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT7_POS)) /**< RESYNC_PT7 Mask */ 160 161 /**@} end of group PTG_RESYNC_Register */ 162 163 /** 164 * @ingroup ptg_registers 165 * @defgroup PTG_INTFL PTG_INTFL 166 * @brief Pulse Train Interrupt Flags 167 * @{ 168 */ 169 #define MXC_F_PTG_INTFL_PT0_POS 0 /**< INTFL_PT0 Position */ 170 #define MXC_F_PTG_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT0_POS)) /**< INTFL_PT0 Mask */ 171 172 #define MXC_F_PTG_INTFL_PT1_POS 1 /**< INTFL_PT1 Position */ 173 #define MXC_F_PTG_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT1_POS)) /**< INTFL_PT1 Mask */ 174 175 #define MXC_F_PTG_INTFL_PT2_POS 2 /**< INTFL_PT2 Position */ 176 #define MXC_F_PTG_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT2_POS)) /**< INTFL_PT2 Mask */ 177 178 #define MXC_F_PTG_INTFL_PT3_POS 3 /**< INTFL_PT3 Position */ 179 #define MXC_F_PTG_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT3_POS)) /**< INTFL_PT3 Mask */ 180 181 #define MXC_F_PTG_INTFL_PT4_POS 4 /**< INTFL_PT4 Position */ 182 #define MXC_F_PTG_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT4_POS)) /**< INTFL_PT4 Mask */ 183 184 #define MXC_F_PTG_INTFL_PT5_POS 5 /**< INTFL_PT5 Position */ 185 #define MXC_F_PTG_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT5_POS)) /**< INTFL_PT5 Mask */ 186 187 #define MXC_F_PTG_INTFL_PT6_POS 6 /**< INTFL_PT6 Position */ 188 #define MXC_F_PTG_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT6_POS)) /**< INTFL_PT6 Mask */ 189 190 #define MXC_F_PTG_INTFL_PT7_POS 7 /**< INTFL_PT7 Position */ 191 #define MXC_F_PTG_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT7_POS)) /**< INTFL_PT7 Mask */ 192 193 /**@} end of group PTG_INTFL_Register */ 194 195 /** 196 * @ingroup ptg_registers 197 * @defgroup PTG_INTEN PTG_INTEN 198 * @brief Pulse Train Interrupt Enable/Disable 199 * @{ 200 */ 201 #define MXC_F_PTG_INTEN_PT0_POS 0 /**< INTEN_PT0 Position */ 202 #define MXC_F_PTG_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT0_POS)) /**< INTEN_PT0 Mask */ 203 204 #define MXC_F_PTG_INTEN_PT1_POS 1 /**< INTEN_PT1 Position */ 205 #define MXC_F_PTG_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT1_POS)) /**< INTEN_PT1 Mask */ 206 207 #define MXC_F_PTG_INTEN_PT2_POS 2 /**< INTEN_PT2 Position */ 208 #define MXC_F_PTG_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT2_POS)) /**< INTEN_PT2 Mask */ 209 210 #define MXC_F_PTG_INTEN_PT3_POS 3 /**< INTEN_PT3 Position */ 211 #define MXC_F_PTG_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT3_POS)) /**< INTEN_PT3 Mask */ 212 213 #define MXC_F_PTG_INTEN_PT4_POS 4 /**< INTEN_PT4 Position */ 214 #define MXC_F_PTG_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT4_POS)) /**< INTEN_PT4 Mask */ 215 216 #define MXC_F_PTG_INTEN_PT5_POS 5 /**< INTEN_PT5 Position */ 217 #define MXC_F_PTG_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT5_POS)) /**< INTEN_PT5 Mask */ 218 219 #define MXC_F_PTG_INTEN_PT6_POS 6 /**< INTEN_PT6 Position */ 220 #define MXC_F_PTG_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT6_POS)) /**< INTEN_PT6 Mask */ 221 222 #define MXC_F_PTG_INTEN_PT7_POS 7 /**< INTEN_PT7 Position */ 223 #define MXC_F_PTG_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT7_POS)) /**< INTEN_PT7 Mask */ 224 225 /**@} end of group PTG_INTEN_Register */ 226 227 /** 228 * @ingroup ptg_registers 229 * @defgroup PTG_SAFE_EN PTG_SAFE_EN 230 * @brief Pulse Train Global Safe Enable. 231 * @{ 232 */ 233 #define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 234 #define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 235 236 #define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 237 #define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 238 239 #define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 240 #define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 241 242 #define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 243 #define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 244 245 #define MXC_F_PTG_SAFE_EN_PT4_POS 4 /**< SAFE_EN_PT4 Position */ 246 #define MXC_F_PTG_SAFE_EN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT4_POS)) /**< SAFE_EN_PT4 Mask */ 247 248 #define MXC_F_PTG_SAFE_EN_PT5_POS 5 /**< SAFE_EN_PT5 Position */ 249 #define MXC_F_PTG_SAFE_EN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT5_POS)) /**< SAFE_EN_PT5 Mask */ 250 251 #define MXC_F_PTG_SAFE_EN_PT6_POS 6 /**< SAFE_EN_PT6 Position */ 252 #define MXC_F_PTG_SAFE_EN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT6_POS)) /**< SAFE_EN_PT6 Mask */ 253 254 #define MXC_F_PTG_SAFE_EN_PT7_POS 7 /**< SAFE_EN_PT7 Position */ 255 #define MXC_F_PTG_SAFE_EN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT7_POS)) /**< SAFE_EN_PT7 Mask */ 256 257 /**@} end of group PTG_SAFE_EN_Register */ 258 259 /** 260 * @ingroup ptg_registers 261 * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS 262 * @brief Pulse Train Global Safe Disable. 263 * @{ 264 */ 265 #define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 266 #define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 267 268 #define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 269 #define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 270 271 #define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 272 #define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 273 274 #define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 275 #define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 276 277 #define MXC_F_PTG_SAFE_DIS_PT4_POS 4 /**< SAFE_DIS_PT4 Position */ 278 #define MXC_F_PTG_SAFE_DIS_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT4_POS)) /**< SAFE_DIS_PT4 Mask */ 279 280 #define MXC_F_PTG_SAFE_DIS_PT5_POS 5 /**< SAFE_DIS_PT5 Position */ 281 #define MXC_F_PTG_SAFE_DIS_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT5_POS)) /**< SAFE_DIS_PT5 Mask */ 282 283 #define MXC_F_PTG_SAFE_DIS_PT6_POS 6 /**< SAFE_DIS_PT6 Position */ 284 #define MXC_F_PTG_SAFE_DIS_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT6_POS)) /**< SAFE_DIS_PT6 Mask */ 285 286 #define MXC_F_PTG_SAFE_DIS_PT7_POS 7 /**< SAFE_DIS_PT7 Position */ 287 #define MXC_F_PTG_SAFE_DIS_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT7_POS)) /**< SAFE_DIS_PT7 Mask */ 288 289 /**@} end of group PTG_SAFE_DIS_Register */ 290 291 #ifdef __cplusplus 292 } 293 #endif 294 295 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_PTG_REGS_H_ 296
