1 /** 2 * @file owm_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_OWM_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_OWM_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup owm 66 * @defgroup owm_registers OWM_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. 68 * @details 1-Wire Master Interface. 69 */ 70 71 /** 72 * @ingroup owm_registers 73 * Structure type to access the OWM Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM CFG Register */ 77 __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM CLK_DIV_1US Register */ 78 __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM CTRL_STAT Register */ 79 __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM DATA Register */ 80 __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM INTFL Register */ 81 __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM INTEN Register */ 82 } mxc_owm_regs_t; 83 84 /* Register offsets for module OWM */ 85 /** 86 * @ingroup owm_registers 87 * @defgroup OWM_Register_Offsets Register Offsets 88 * @brief OWM Peripheral Register Offsets from the OWM Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_OWM_CFG ((uint32_t)0x00000000UL) /**< Offset from OWM Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_OWM_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from OWM Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_OWM_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from OWM Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_OWM_DATA ((uint32_t)0x0000000CUL) /**< Offset from OWM Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_OWM_INTFL ((uint32_t)0x00000010UL) /**< Offset from OWM Base Address: <tt> 0x0010</tt> */ 96 #define MXC_R_OWM_INTEN ((uint32_t)0x00000014UL) /**< Offset from OWM Base Address: <tt> 0x0014</tt> */ 97 /**@} end of group owm_registers */ 98 99 /** 100 * @ingroup owm_registers 101 * @defgroup OWM_CFG OWM_CFG 102 * @brief 1-Wire Master Configuration. 103 * @{ 104 */ 105 #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< CFG_LONG_LINE_MODE Position */ 106 #define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< CFG_LONG_LINE_MODE Mask */ 107 108 #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< CFG_FORCE_PRES_DET Position */ 109 #define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x1UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< CFG_FORCE_PRES_DET Mask */ 110 111 #define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< CFG_BIT_BANG_EN Position */ 112 #define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x1UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< CFG_BIT_BANG_EN Mask */ 113 114 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< CFG_EXT_PULLUP_MODE Position */ 115 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< CFG_EXT_PULLUP_MODE Mask */ 116 117 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< CFG_EXT_PULLUP_ENABLE Position */ 118 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< CFG_EXT_PULLUP_ENABLE Mask */ 119 120 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< CFG_SINGLE_BIT_MODE Position */ 121 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< CFG_SINGLE_BIT_MODE Mask */ 122 123 #define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< CFG_OVERDRIVE Position */ 124 #define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< CFG_OVERDRIVE Mask */ 125 126 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< CFG_INT_PULLUP_ENABLE Position */ 127 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< CFG_INT_PULLUP_ENABLE Mask */ 128 129 /**@} end of group OWM_CFG_Register */ 130 131 /** 132 * @ingroup owm_registers 133 * @defgroup OWM_CLK_DIV_1US OWM_CLK_DIV_1US 134 * @brief 1-Wire Master Clock Divisor. 135 * @{ 136 */ 137 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< CLK_DIV_1US_DIVISOR Position */ 138 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0xFFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< CLK_DIV_1US_DIVISOR Mask */ 139 140 /**@} end of group OWM_CLK_DIV_1US_Register */ 141 142 /** 143 * @ingroup owm_registers 144 * @defgroup OWM_CTRL_STAT OWM_CTRL_STAT 145 * @brief 1-Wire Master Control/Status. 146 * @{ 147 */ 148 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< CTRL_STAT_START_OW_RESET Position */ 149 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< CTRL_STAT_START_OW_RESET Mask */ 150 151 #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< CTRL_STAT_SRA_MODE Position */ 152 #define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< CTRL_STAT_SRA_MODE Mask */ 153 154 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< CTRL_STAT_BIT_BANG_OE Position */ 155 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< CTRL_STAT_BIT_BANG_OE Mask */ 156 157 #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< CTRL_STAT_OW_INPUT Position */ 158 #define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< CTRL_STAT_OW_INPUT Mask */ 159 160 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< CTRL_STAT_OD_SPEC_MODE Position */ 161 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< CTRL_STAT_OD_SPEC_MODE Mask */ 162 163 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< CTRL_STAT_PRESENCE_DETECT Position */ 164 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< CTRL_STAT_PRESENCE_DETECT Mask */ 165 166 /**@} end of group OWM_CTRL_STAT_Register */ 167 168 /** 169 * @ingroup owm_registers 170 * @defgroup OWM_DATA OWM_DATA 171 * @brief 1-Wire Master Data Buffer. 172 * @{ 173 */ 174 #define MXC_F_OWM_DATA_TX_RX_POS 0 /**< DATA_TX_RX Position */ 175 #define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0xFFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< DATA_TX_RX Mask */ 176 177 /**@} end of group OWM_DATA_Register */ 178 179 /** 180 * @ingroup owm_registers 181 * @defgroup OWM_INTFL OWM_INTFL 182 * @brief 1-Wire Master Interrupt Flags. 183 * @{ 184 */ 185 #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< INTFL_OW_RESET_DONE Position */ 186 #define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< INTFL_OW_RESET_DONE Mask */ 187 188 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< INTFL_TX_DATA_EMPTY Position */ 189 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< INTFL_TX_DATA_EMPTY Mask */ 190 191 #define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< INTFL_RX_DATA_READY Position */ 192 #define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< INTFL_RX_DATA_READY Mask */ 193 194 #define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< INTFL_LINE_SHORT Position */ 195 #define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< INTFL_LINE_SHORT Mask */ 196 197 #define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< INTFL_LINE_LOW Position */ 198 #define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< INTFL_LINE_LOW Mask */ 199 200 /**@} end of group OWM_INTFL_Register */ 201 202 /** 203 * @ingroup owm_registers 204 * @defgroup OWM_INTEN OWM_INTEN 205 * @brief 1-Wire Master Interrupt Enables. 206 * @{ 207 */ 208 #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< INTEN_OW_RESET_DONE Position */ 209 #define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< INTEN_OW_RESET_DONE Mask */ 210 211 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< INTEN_TX_DATA_EMPTY Position */ 212 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< INTEN_TX_DATA_EMPTY Mask */ 213 214 #define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< INTEN_RX_DATA_READY Position */ 215 #define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< INTEN_RX_DATA_READY Mask */ 216 217 #define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< INTEN_LINE_SHORT Position */ 218 #define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< INTEN_LINE_SHORT Mask */ 219 220 #define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< INTEN_LINE_LOW Position */ 221 #define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< INTEN_LINE_LOW Mask */ 222 223 /**@} end of group OWM_INTEN_Register */ 224 225 #ifdef __cplusplus 226 } 227 #endif 228 229 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_OWM_REGS_H_ 230
