1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_MCR_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_MCR_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup mcr 66 * @defgroup mcr_registers MCR_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 68 * @details Misc Control. 69 */ 70 71 /** 72 * @ingroup mcr_registers 73 * Structure type to access the MCR Registers. 74 */ 75 typedef struct { 76 __IO uint32_t eccen; /**< <tt>\b 0x00:</tt> MCR ECCEN Register */ 77 __R uint32_t rsv_0x4; 78 __IO uint32_t pdown; /**< <tt>\b 0x08:</tt> MCR PDOWN Register */ 79 __R uint32_t rsv_0xc; 80 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> MCR CTRL Register */ 81 } mxc_mcr_regs_t; 82 83 /* Register offsets for module MCR */ 84 /** 85 * @ingroup mcr_registers 86 * @defgroup MCR_Register_Offsets Register Offsets 87 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_MCR_PDOWN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 92 #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 93 /**@} end of group mcr_registers */ 94 95 /** 96 * @ingroup mcr_registers 97 * @defgroup MCR_ECCEN MCR_ECCEN 98 * @brief ECC Enable Register 99 * @{ 100 */ 101 #define MXC_F_MCR_ECCEN_SYSRAM0ECCEN_POS 0 /**< ECCEN_SYSRAM0ECCEN Position */ 102 #define MXC_F_MCR_ECCEN_SYSRAM0ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM0ECCEN_POS)) /**< ECCEN_SYSRAM0ECCEN Mask */ 103 104 #define MXC_F_MCR_ECCEN_SYSRAM1ECCEN_POS 1 /**< ECCEN_SYSRAM1ECCEN Position */ 105 #define MXC_F_MCR_ECCEN_SYSRAM1ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM1ECCEN_POS)) /**< ECCEN_SYSRAM1ECCEN Mask */ 106 107 #define MXC_F_MCR_ECCEN_SYSRAM2ECCEN_POS 2 /**< ECCEN_SYSRAM2ECCEN Position */ 108 #define MXC_F_MCR_ECCEN_SYSRAM2ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM2ECCEN_POS)) /**< ECCEN_SYSRAM2ECCEN Mask */ 109 110 #define MXC_F_MCR_ECCEN_SYSRAM3ECCEN_POS 3 /**< ECCEN_SYSRAM3ECCEN Position */ 111 #define MXC_F_MCR_ECCEN_SYSRAM3ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM3ECCEN_POS)) /**< ECCEN_SYSRAM3ECCEN Mask */ 112 113 #define MXC_F_MCR_ECCEN_SYSRAM4ECCEN_POS 4 /**< ECCEN_SYSRAM4ECCEN Position */ 114 #define MXC_F_MCR_ECCEN_SYSRAM4ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM4ECCEN_POS)) /**< ECCEN_SYSRAM4ECCEN Mask */ 115 116 #define MXC_F_MCR_ECCEN_SYSRAM5ECCEN_POS 5 /**< ECCEN_SYSRAM5ECCEN Position */ 117 #define MXC_F_MCR_ECCEN_SYSRAM5ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM5ECCEN_POS)) /**< ECCEN_SYSRAM5ECCEN Mask */ 118 119 #define MXC_F_MCR_ECCEN_IC0ECCEN_POS 8 /**< ECCEN_IC0ECCEN Position */ 120 #define MXC_F_MCR_ECCEN_IC0ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_IC0ECCEN_POS)) /**< ECCEN_IC0ECCEN Mask */ 121 122 #define MXC_F_MCR_ECCEN_ICXIPECCEN_POS 10 /**< ECCEN_ICXIPECCEN Position */ 123 #define MXC_F_MCR_ECCEN_ICXIPECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_ICXIPECCEN_POS)) /**< ECCEN_ICXIPECCEN Mask */ 124 125 #define MXC_F_MCR_ECCEN_FL0ECCEN_POS 11 /**< ECCEN_FL0ECCEN Position */ 126 #define MXC_F_MCR_ECCEN_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_FL0ECCEN_POS)) /**< ECCEN_FL0ECCEN Mask */ 127 128 #define MXC_F_MCR_ECCEN_FL1ECCEN_POS 12 /**< ECCEN_FL1ECCEN Position */ 129 #define MXC_F_MCR_ECCEN_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_FL1ECCEN_POS)) /**< ECCEN_FL1ECCEN Mask */ 130 131 /**@} end of group MCR_ECCEN_Register */ 132 133 /** 134 * @ingroup mcr_registers 135 * @defgroup MCR_PDOWN MCR_PDOWN 136 * @brief PDOWN Drive Strength 137 * @{ 138 */ 139 #define MXC_F_MCR_PDOWN_PDOWNDS_POS 0 /**< PDOWN_PDOWNDS Position */ 140 #define MXC_F_MCR_PDOWN_PDOWNDS ((uint32_t)(0x3UL << MXC_F_MCR_PDOWN_PDOWNDS_POS)) /**< PDOWN_PDOWNDS Mask */ 141 142 #define MXC_F_MCR_PDOWN_PDOWNVS_POS 2 /**< PDOWN_PDOWNVS Position */ 143 #define MXC_F_MCR_PDOWN_PDOWNVS ((uint32_t)(0x1UL << MXC_F_MCR_PDOWN_PDOWNVS_POS)) /**< PDOWN_PDOWNVS Mask */ 144 145 /**@} end of group MCR_PDOWN_Register */ 146 147 /** 148 * @ingroup mcr_registers 149 * @defgroup MCR_CTRL MCR_CTRL 150 * @brief Misc Power State Control Register 151 * @{ 152 */ 153 #define MXC_F_MCR_CTRL_VDDCSW_POS 1 /**< CTRL_VDDCSW Position */ 154 #define MXC_F_MCR_CTRL_VDDCSW ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_VDDCSW_POS)) /**< CTRL_VDDCSW Mask */ 155 156 #define MXC_F_MCR_CTRL_USBSWEN_N_POS 3 /**< CTRL_USBSWEN_N Position */ 157 #define MXC_F_MCR_CTRL_USBSWEN_N ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_USBSWEN_N_POS)) /**< CTRL_USBSWEN_N Mask */ 158 159 #define MXC_F_MCR_CTRL_P1M_POS 9 /**< CTRL_P1M Position */ 160 #define MXC_F_MCR_CTRL_P1M ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_P1M_POS)) /**< CTRL_P1M Mask */ 161 162 #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS 10 /**< CTRL_RSTN_VOLTAGE_SEL Position */ 163 #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS)) /**< CTRL_RSTN_VOLTAGE_SEL Mask */ 164 165 /**@} end of group MCR_CTRL_Register */ 166 167 #ifdef __cplusplus 168 } 169 #endif 170 171 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_MCR_REGS_H_ 172
