1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_MAX32570_H_ 22 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_MAX32570_H_ 23 24 #ifndef TARGET_NUM 25 #define TARGET_NUM 32570 26 #endif 27 28 #define MXC_NUMCORES 1 29 30 #include <stdint.h> 31 #include <stdbool.h> 32 33 #ifndef FALSE 34 #define FALSE (0) 35 #endif 36 37 #ifndef TRUE 38 #define TRUE (1) 39 #endif 40 41 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 42 #if defined(__GNUC__) 43 #ifndef __weak 44 #define __weak __attribute__((weak)) 45 #endif 46 47 #elif defined(__CC_ARM) 48 49 #define inline __inline 50 #pragma anon_unions 51 52 #endif 53 54 typedef enum { 55 NonMaskableInt_IRQn = -14, 56 HardFault_IRQn = -13, 57 MemoryManagement_IRQn = -12, 58 BusFault_IRQn = -11, 59 UsageFault_IRQn = -10, 60 SVCall_IRQn = -5, 61 DebugMonitor_IRQn = -4, 62 PendSV_IRQn = -2, 63 SysTick_IRQn = -1, 64 65 /* Device-specific interrupt sources (external to ARM core) */ 66 /* table entry number */ 67 /* |||| */ 68 /* |||| table offset address */ 69 /* vvvv vvvvvv */ 70 71 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 72 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 73 USB_IRQn, /* 0x12 0x0048 18: USB */ 74 RTC_IRQn, /* 0x13 0x004C 19: RTC */ 75 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 76 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 77 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 78 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 79 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3*/ 80 TMR4_IRQn, /* 0x19 0x0064 25: Timer 4*/ 81 TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */ 82 SC0_IRQn, /* 0x1B 0x006C 27: Smart Card 0 */ 83 LCD_IRQn, /* 0x1C 0x0070 28: LCD Controller*/ 84 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 85 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 86 UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ 87 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ 88 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ 89 SPI2_IRQn, /* 0x22 0x0088 34: SPI2 */ 90 SKB_IRQn, /* 0x23 0x008C 35: Secure Keypad */ 91 ADC_IRQn, /* 0x24 0x0090 36: ADC */ 92 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 93 MSR_IRQn, /* 0x26 0x0098 38: Magstripe DSP */ 94 FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */ 95 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 96 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */ 97 GPIO2_IRQn, /* 0x2A 0x00A8 42: GPIO2 */ 98 CRYPTO_IRQn, /* 0x2B 0x00AC 43: Crypto */ 99 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 100 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 101 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 102 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 103 TMR6_IRQn, /* 0x30 0x00C0 48: Timer 6 */ 104 TMR7_IRQn, /* 0x31 0x00C4 49: Timer 7 */ 105 UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */ 106 CLC_IRQn, /* 0x33 0x00CC 51: Contactless Link Control */ 107 I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ 108 SC1_IRQn, /* 0x35 0x00D4 53: Smart Card 1 */ 109 SPIXFC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */ 110 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ 111 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ 112 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ 113 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ 114 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ 115 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ 116 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ 117 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ 118 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ 119 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ 120 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ 121 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ 122 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ 123 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ 124 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ 125 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 126 NFCWAKE_IRQn, /* 0x47 0x011C 71: NFC Wakeup */ 127 SPI3_IRQn, /* 0x48 0x0120 72: SPI3 */ 128 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ 129 GPIO3_IRQn, /* 0x4A 0x0128 74: GPIO3 */ 130 PT_IRQn, /* 0x4B 0x012C 75: Pulse train */ 131 HA0_IRQn, /* 0x4C 0x0130 76: Hardware Accelerator 0 */ 132 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 133 I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */ 134 HA1_IRQn, /* 0x4F 0x013C 79: Hardware Accelerator 1 */ 135 EMAC_IRQn, /* 0x50 0x0140 80: Ethernet MAC */ 136 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 137 SDHC_IRQn, /* 0x52 0x0148 82: SDIO/SDHC */ 138 OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */ 139 DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */ 140 DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */ 141 DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */ 142 DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */ 143 DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */ 144 DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */ 145 DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */ 146 DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */ 147 DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */ 148 DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */ 149 DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */ 150 DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */ 151 USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */ 152 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 153 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ 154 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ 155 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ 156 RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ 157 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 158 FLC1_IRQn, /* 0x67 0x019C 103: Flash Control 1 */ 159 UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */ 160 UART4_IRQn, /* 0x69 0x01A4 105: UART 4 */ 161 UART5_IRQn, /* 0x6A 0x01A8 106: UART 5 */ 162 CameraIF_IRQn, /* 0x6B 0x01AC 107: Camera IF */ 163 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 164 HTMR0_IRQn, /* 0x6D 0x01B4 109: HTimer0 */ 165 HTMR1_IRQn, /* 0x6E 0x01B8 110: HTimer1 */ 166 MXC_IRQ_EXT_COUNT 167 } IRQn_Type; 168 169 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 170 171 /* ================================================================================ */ 172 /* ================ Processor and Core Peripheral Section ================ */ 173 /* ================================================================================ */ 174 175 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 176 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 177 #define __MPU_PRESENT 1 /*!< MPU present or not */ 178 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 179 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 180 #define __FPU_PRESENT 1 /*!< FPU present or not */ 181 182 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 183 #include "system_max32570.h" /*!< System Header */ 184 185 /* ================================================================================ */ 186 /* ================== Device Specific Memory Section ================== */ 187 /* ================================================================================ */ 188 189 #define MXC_ROM_MEM_BASE 0x00000000UL 190 #define MXC_ROM_MEM_SIZE 0x00020000UL 191 #define MXC_XIP_MEM_BASE 0x08000000UL 192 #define MXC_XIP_MEM_SIZE 0x08000000UL 193 #define MXC_FLASH0_MEM_BASE 0x10000000UL 194 #define MXC_FLASH1_MEM_BASE 0x10080000UL 195 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE 196 #define MXC_FLASH_PAGE_SIZE 0x00002000UL 197 #define MXC_FLASH_MEM_SIZE 0x00080000UL 198 #define MXC_INFO0_MEM_BASE 0x10800000UL 199 #define MXC_INFO1_MEM_BASE 0x10804000UL 200 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 201 #define MXC_INFO_MEM_SIZE 0x00004000UL 202 #define MXC_SRAM_MEM_BASE 0x20000000UL 203 #define MXC_SRAM_MEM_SIZE 0x000BE000UL 204 #define MXC_XIP_DATA_MEM_BASE 0x80000000UL 205 #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL 206 207 /* ================================================================================ */ 208 /* ================ Device Specific Peripheral Section ================ */ 209 /* ================================================================================ */ 210 211 /* 212 Base addresses and configuration settings for all MAX32570 peripheral modules. 213 */ 214 215 /******************************************************************************/ 216 /* Global control */ 217 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 218 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 219 220 /******************************************************************************/ 221 /* Non-battery backed SI Registers */ 222 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 223 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 224 225 /******************************************************************************/ 226 /* Non-battery backed Function Control */ 227 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 228 #define MXC_FCR ((mxc_fcr_regs_t *)MXC_BASE_FCR) 229 230 /******************************************************************************/ 231 /* Trust Protection Unit */ 232 #define MXC_BASE_CTB ((uint32_t)0x40001000UL) 233 #define MXC_CTB ((mxc_ctb_regs_t *)MXC_BASE_CTB) 234 235 /******************************************************************************/ 236 /* Watchdog */ 237 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 238 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 239 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) 240 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 241 242 /******************************************************************************/ 243 /* Security Monitor */ 244 #define MXC_BASE_SMON ((uint32_t)0x40004000UL) 245 #define MXC_SMON ((mxc_smon_regs_t *)MXC_BASE_SMON) 246 247 /******************************************************************************/ 248 /* SIMO */ 249 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL) 250 #define MXC_SIMO ((mxc_simo_regs_t *)MXC_BASE_SIMO) 251 252 /******************************************************************************/ 253 /* DVS*/ 254 #define MXC_BASE_DVS ((uint32_t)0x40004800UL) 255 #define MXC_DVS ((mxc_dvs_regs_t *)MXC_BASE_DVS) 256 257 /******************************************************************************/ 258 /* Trim System Initalization Register */ 259 #define MXC_BASE_TRIMSIR ((uint32_t)0x40005400UL) 260 #define MXC_TRIMSIR ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR) 261 262 /******************************************************************************/ 263 /* BBFC */ 264 #define MXC_BASE_BBFC ((uint32_t)0x40005800UL) 265 #define MXC_BBFC ((mxc_bbfc_regs_t *)MXC_BASE_BBFC) 266 267 /******************************************************************************/ 268 /* Real Time Clock */ 269 #define MXC_BASE_RTC ((uint32_t)0x40006000UL) 270 #define MXC_RTC ((mxc_rtc_regs_t *)MXC_BASE_RTC) 271 272 /******************************************************************************/ 273 /* Power Sequencer */ 274 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 275 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 276 277 /******************************************************************************/ 278 /* Power Sequencer */ 279 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL) 280 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 281 282 /******************************************************************************/ 283 /* GPIO */ 284 #define MXC_CFG_GPIO_INSTANCES (4) 285 #define MXC_CFG_GPIO_PINS_PORT (32) 286 287 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 288 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 289 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 290 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 291 #define MXC_BASE_GPIO2 ((uint32_t)0x4000A000UL) 292 #define MXC_GPIO2 ((mxc_gpio_regs_t *)MXC_BASE_GPIO2) 293 #define MXC_BASE_GPIO3 ((uint32_t)0x4000B000UL) 294 #define MXC_GPIO3 ((mxc_gpio_regs_t *)MXC_BASE_GPIO3) 295 296 #define MXC_GPIO_GET_IDX(p) \ 297 ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : (p) == MXC_GPIO2 ? 2 : (p) == MXC_GPIO3 ? 3 : -1) 298 299 #define MXC_GPIO_GET_GPIO(i) \ 300 ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : (i) == 2 ? MXC_GPIO2 : (i) == 3 ? MXC_GPIO3 : 0) 301 302 #define MXC_GPIO_GET_IRQ(i) \ 303 ((i) == 0 ? GPIO0_IRQn : \ 304 (i) == 1 ? GPIO1_IRQn : \ 305 (i) == 2 ? GPIO2_IRQn : \ 306 (i) == 3 ? GPIO3_IRQn : \ 307 0) 308 309 /******************************************************************************/ 310 /* PCIF */ 311 #define MXC_BASE_PCIF ((uint32_t)0x4000E000UL) 312 #define MXC_PCIF ((mxc_cameraif_regs_t *)MXC_BASE_PCIF) 313 314 /******************************************************************************/ 315 /* Timer */ 316 #define SEC(s) (((uint32_t)s) * 1000000UL) 317 #define MSEC(ms) (ms * 1000UL) 318 #define USEC(us) (us) 319 320 #define MXC_CFG_TMR_INSTANCES (6) 321 322 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 323 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 324 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 325 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 326 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 327 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 328 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 329 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 330 #define MXC_BASE_TMR4 ((uint32_t)0x40014000UL) 331 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) 332 #define MXC_BASE_TMR5 ((uint32_t)0x40015000UL) 333 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) 334 #define MXC_BASE_TMR6 ((uint32_t)0x40016000UL) 335 #define MXC_TMR6 ((mxc_tmr_regs_t *)MXC_BASE_TMR6) 336 #define MXC_BASE_TMR7 ((uint32_t)0x40017000UL) 337 #define MXC_TMR7 ((mxc_tmr_regs_t *)MXC_BASE_TMR7) 338 339 #define MXC_TMR_GET_IRQ(i) \ 340 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 341 (i) == 1 ? TMR1_IRQn : \ 342 (i) == 2 ? TMR2_IRQn : \ 343 (i) == 3 ? TMR3_IRQn : \ 344 (i) == 4 ? TMR4_IRQn : \ 345 (i) == 5 ? TMR5_IRQn : \ 346 (i) == 6 ? TMR6_IRQn : \ 347 (i) == 7 ? TMR7_IRQn : \ 348 0) 349 350 #define MXC_TMR_GET_BASE(i) \ 351 ((i) == 0 ? MXC_BASE_TMR0 : \ 352 (i) == 1 ? MXC_BASE_TMR1 : \ 353 (i) == 2 ? MXC_BASE_TMR2 : \ 354 (i) == 3 ? MXC_BASE_TMR3 : \ 355 (i) == 4 ? MXC_BASE_TMR4 : \ 356 (i) == 5 ? MXC_BASE_TMR5 : \ 357 (i) == 6 ? MXC_BASE_TMR6 : \ 358 (i) == 7 ? MXC_BASE_TMR7 : \ 359 0) 360 361 #define MXC_TMR_GET_TMR(i) \ 362 ((i) == 0 ? MXC_TMR0 : \ 363 (i) == 1 ? MXC_TMR1 : \ 364 (i) == 2 ? MXC_TMR2 : \ 365 (i) == 3 ? MXC_TMR3 : \ 366 (i) == 4 ? MXC_TMR4 : \ 367 (i) == 5 ? MXC_TMR5 : \ 368 (i) == 6 ? MXC_TMR6 : \ 369 (i) == 7 ? MXC_TMR7 : \ 370 0) 371 372 #define MXC_TMR_GET_IDX(p) \ 373 ((p) == MXC_TMR0 ? 0 : \ 374 (p) == MXC_TMR1 ? 1 : \ 375 (p) == MXC_TMR2 ? 2 : \ 376 (p) == MXC_TMR3 ? 3 : \ 377 (p) == MXC_TMR4 ? 4 : \ 378 (p) == MXC_TMR5 ? 5 : \ 379 (p) == MXC_TMR6 ? 6 : \ 380 (p) == MXC_TMR7 ? 7 : \ 381 -1) 382 383 /******************************************************************************/ 384 /* High Speed Timer */ 385 #define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL) 386 #define MXC_HTMR0 ((mxc_htmr_regs_t *)MXC_BASE_HTMR0) 387 #define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL) 388 #define MXC_HTMR1 ((mxc_htmr_regs_t *)MXC_BASE_HTMR1) 389 390 /******************************************************************************/ 391 /* I2C */ 392 #define MXC_I2C_INSTANCES (3) 393 394 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 395 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 396 #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) 397 #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) 398 #define MXC_BASE_I2C2 ((uint32_t)0x4001F000UL) 399 #define MXC_I2C2 ((mxc_i2c_regs_t *)MXC_BASE_I2C2) 400 401 #define MXC_I2C_GET_IRQ(i) \ 402 (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : (i) == 2 ? I2C2_IRQn : 0) 403 404 #define MXC_I2C_GET_BASE(i) \ 405 ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : (i) == 2 ? MXC_BASE_I2C2 : 0) 406 407 #define MXC_I2C_GET_TMR(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : (i) == 2 ? MXC_I2C2 : 0) 408 409 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : (p) == MXC_I2C2 ? 2 : -1) 410 #define MXC_I2C_FIFO_DEPTH (8) 411 412 /******************************************************************************/ 413 /* SPI Execute in Place */ 414 #define MXC_BASE_SPIXFM ((uint32_t)0x40026000UL) 415 #define MXC_SPIXFM ((mxc_spixfm_regs_t *)MXC_BASE_SPIXFM) 416 417 /******************************************************************************/ 418 /* SPI Execute in Place Master */ 419 #define MXC_CFG_SPIXFC_FIFO_DEPTH (16) 420 421 #define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL) 422 #define MXC_SPIXFC ((mxc_spixfc_regs_t *)MXC_BASE_SPIXFC) 423 424 #define MXC_BASE_SPIXFC_FIFO ((uint32_t)0x400BC000UL) 425 #define MXC_SPIXFC_FIFO ((mxc_spixfc_fifo_regs_t *)MXC_BASE_SPIXFC_FIFO) 426 427 /******************************************************************************/ 428 /* DMA */ 429 #define MXC_DMA_CHANNELS (16) 430 #define MXC_DMA_INSTANCES (1) 431 432 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 433 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 434 435 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 436 437 #define MXC_DMA_CH_GET_IRQ(i) \ 438 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 439 ((i) == 1) ? DMA1_IRQn : \ 440 ((i) == 2) ? DMA2_IRQn : \ 441 ((i) == 3) ? DMA3_IRQn : \ 442 ((i) == 4) ? DMA4_IRQn : \ 443 ((i) == 5) ? DMA5_IRQn : \ 444 ((i) == 6) ? DMA6_IRQn : \ 445 ((i) == 7) ? DMA7_IRQn : \ 446 ((i) == 8) ? DMA8_IRQn : \ 447 ((i) == 9) ? DMA9_IRQn : \ 448 ((i) == 10) ? DMA10_IRQn : \ 449 ((i) == 11) ? DMA11_IRQn : \ 450 ((i) == 12) ? DMA12_IRQn : \ 451 ((i) == 13) ? DMA13_IRQn : \ 452 ((i) == 14) ? DMA14_IRQn : \ 453 ((i) == 15) ? DMA15_IRQn : \ 454 0)) 455 456 /******************************************************************************/ 457 /* FLC */ 458 #define MXC_FLC_INSTANCES (2) 459 460 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL) 461 #define MXC_FLC0 ((mxc_flc_regs_t *)MXC_BASE_FLC0) 462 #define MXC_BASE_FLC1 ((uint32_t)0x40029400UL) 463 #define MXC_FLC1 ((mxc_flc_regs_t *)MXC_BASE_FLC1) 464 465 #define MXC_FLC MXC_FLC0 466 467 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : (i) == 1 ? FLC1_IRQn : 0) 468 469 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : (i) == 1 ? MXC_BASE_FLC1 : 0) 470 471 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : (i) == 1 ? MXC_FLC1 : 0) 472 473 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : (p) == MXC_FLC1 ? 1 : -1) 474 475 /******************************************************************************/ 476 /* Instruction Cache */ 477 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL) 478 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) 479 480 /******************************************************************************/ 481 /* Magstripe Reader ADC */ 482 #define MXC_BASE_ADC9 ((uint32_t)0x4002B000UL) 483 #define MXC_ADC9 ((mxc_adc9_regs_t *)MXC_BASE_ADC9) 484 485 #define MXC_BASE_MSRADC MXC_BASE_ADC9 486 #define MXC_MSRADC MXC_ADC9 487 488 /******************************************************************************/ 489 /* Smart Card */ 490 #define MXC_SC_INSTANCES (2) 491 492 #define MXC_BASE_SC0 ((uint32_t)0x4002C000UL) 493 #define MXC_SC0 ((mxc_scn_regs_t *)MXC_BASE_SC0) 494 #define MXC_BASE_SC1 ((uint32_t)0x4002D000UL) 495 #define MXC_SC1 ((mxc_scn_regs_t *)MXC_BASE_SC1) 496 497 #define MXC_SC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SC0_IRQn : (i) == 1 ? SC1_IRQn : 0) 498 499 #define MXC_SC_GET_BASE(i) ((i) == 0 ? MXC_BASE_SC0 : (i) == 1 ? MXC_BASE_SC1 : 0) 500 501 #define MXC_SC_GET_IDX(p) ((p) == MXC_SC0 ? 0 : (p) == MXC_SC1 ? 1 : -1) 502 503 /******************************************************************************/ 504 /* Instruction Cache XIP */ 505 #define MXC_BASE_SFCC ((uint32_t)0x4002F000UL) 506 #define MXC_SFCC ((mxc_icc_regs_t *)MXC_BASE_SFCC) 507 508 /******************************************************************************/ 509 /* CLCD */ 510 #define MXC_BASE_CLCD ((uint32_t)0x40031000UL) 511 #define MXC_CLCD ((mxc_clcd_regs_t *)MXC_BASE_CLCD) 512 513 /******************************************************************************/ 514 /* Secure Keyboard */ 515 #define MXC_BASE_SKBD ((uint32_t)0x40032000UL) 516 #define MXC_SKBD ((mxc_skbd_regs_t *)MXC_BASE_SKBD) 517 518 /******************************************************************************/ 519 /* SPIX Data Cache */ 520 #define MXC_BASE_SRCC ((uint32_t)0x40033000UL) 521 #define MXC_SRCC ((mxc_srcc_regs_t *)MXC_BASE_SRCC) 522 523 /******************************************************************************/ 524 /* ADC */ 525 #define MXC_BASE_ADC ((uint32_t)0x40034000UL) 526 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) 527 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz 528 529 /******************************************************************************/ 530 /* XXX Actually reserved! */ 531 #define MXC_BASE_RESERVED ((uint32_t)0x40035000UL) 532 533 /******************************************************************************/ 534 /* Smart DMA */ 535 #define MXC_BASE_SDMA0 ((uint32_t)0x40036000UL) 536 #define MXC_SDMA0 ((mxc_sdma_regs_t *)MXC_BASE_SDMA0) 537 #define MXC_BASE_SDMA1 ((uint32_t)0x4004B000UL) 538 #define MXC_SDMA1 ((mxc_sdma_regs_t *)MXC_BASE_SDMA1) 539 540 /******************************************************************************/ 541 /* SPI XIP Data */ 542 #define MXC_BASE_SPID ((uint32_t)0x4003A000UL) 543 #define MXC_SPID ((mxc_spid_regs_t *)MXC_BASE_SPID) 544 #define MXC_SPIXR ((mxc_spixr_regs_t *)MXC_BASE_SPID) 545 546 /******************************************************************************/ 547 /* MIPI DSI */ 548 #define MXC_BASE_MIPI ((uint32_t)0x4003B000UL) 549 #define MXC_MIPI ((mxc_mipi_regs_t *)MXC_BASE_MIPI) 550 551 /*******************************************************************************/ 552 /* Pulse Train Generation */ 553 #define MXC_CFG_PT_INSTANCES (8) 554 555 #define MXC_BASE_PTG ((uint32_t)0x4003C000UL) 556 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) 557 #define MXC_BASE_PT0 ((uint32_t)0x4003C020UL) 558 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) 559 #define MXC_BASE_PT1 ((uint32_t)0x4003C040UL) 560 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) 561 #define MXC_BASE_PT2 ((uint32_t)0x4003C060UL) 562 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) 563 #define MXC_BASE_PT3 ((uint32_t)0x4003C080UL) 564 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) 565 #define MXC_BASE_PT4 ((uint32_t)0x4003C0A0UL) 566 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) 567 #define MXC_BASE_PT5 ((uint32_t)0x4003C0C0UL) 568 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) 569 #define MXC_BASE_PT6 ((uint32_t)0x4003C0E0UL) 570 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) 571 #define MXC_BASE_PT7 ((uint32_t)0x4003C100UL) 572 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) 573 574 #define MXC_PT_GET_BASE(i) \ 575 ((i) == 0 ? MXC_BASE_PT0 : \ 576 (i) == 1 ? MXC_BASE_PT1 : \ 577 (i) == 2 ? MXC_BASE_PT2 : \ 578 (i) == 3 ? MXC_BASE_PT3 : \ 579 (i) == 4 ? MXC_BASE_PT4 : \ 580 (i) == 5 ? MXC_BASE_PT5 : \ 581 (i) == 6 ? MXC_BASE_PT6 : \ 582 (i) == 7 ? MXC_BASE_PT7 : \ 583 0) 584 585 #define MXC_PT_GET_PT(i) \ 586 ((i) == 0 ? MXC_PT0 : \ 587 (i) == 1 ? MXC_PT1 : \ 588 (i) == 2 ? MXC_PT2 : \ 589 (i) == 3 ? MXC_PT3 : \ 590 (i) == 4 ? MXC_PT4 : \ 591 (i) == 5 ? MXC_PT5 : \ 592 (i) == 6 ? MXC_PT6 : \ 593 (i) == 7 ? MXC_PT7 : \ 594 0) 595 596 #define MXC_PT_GET_IDX(p) \ 597 ((p) == MXC_PT0 ? 0 : \ 598 (p) == MXC_PT1 ? 1 : \ 599 (p) == MXC_PT2 ? 2 : \ 600 (p) == MXC_PT3 ? 3 : \ 601 (p) == MXC_PT4 ? 4 : \ 602 (p) == MXC_PT5 ? 5 : \ 603 (p) == MXC_PT6 ? 6 : \ 604 (p) == MXC_PT7 ? 7 : \ 605 -1) 606 607 /******************************************************************************/ 608 /* One Wire Master */ 609 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL) 610 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM) 611 612 /******************************************************************************/ 613 /* Semaphore */ 614 #define MXC_CFG_SEMA_INSTANCES (8) 615 616 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL) 617 #define MXC_SEMA ((mxc_sema_regs_t *)MXC_BASE_SEMA) 618 619 /******************************************************************************/ 620 /* Pixel Bit Manipulator */ 621 #define MXC_BASE_PBM ((uint32_t)0x4003F000UL) 622 #define MXC_PBM ((mxc_pbm_regs_t *)MXC_BASE_PBM) 623 624 /******************************************************************************/ 625 /* Contactless RF NFC */ 626 #define MXC_BASE_NFC ((uint32_t)0x40040000UL) 627 #define MXC_NFC ((mxc_nfc_regs_t *)MXC_BASE_NFC) 628 629 /******************************************************************************/ 630 /* UART / Serial Port Interface */ 631 #define MXC_UART_INSTANCES (6) 632 #define MXC_UART_FIFO_DEPTH (8) 633 634 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL) 635 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 636 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL) 637 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) 638 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL) 639 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2) 640 #define MXC_BASE_UART3 ((uint32_t)0x40045000UL) 641 #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) 642 #define MXC_BASE_UART4 ((uint32_t)0x40023000UL) 643 #define MXC_UART4 ((mxc_uart_regs_t *)MXC_BASE_UART4) 644 #define MXC_BASE_UART5 ((uint32_t)0x40024000UL) 645 #define MXC_UART5 ((mxc_uart_regs_t *)MXC_BASE_UART5) 646 647 #define MXC_UART_GET_IRQ(i) \ 648 (IRQn_Type)((i) == 0 ? UART0_IRQn : \ 649 (i) == 1 ? UART1_IRQn : \ 650 (i) == 2 ? UART2_IRQn : \ 651 (i) == 3 ? UART3_IRQn : \ 652 (i) == 4 ? UART4_IRQn : \ 653 (i) == 5 ? UART5_IRQn : \ 654 0) 655 656 #define MXC_UART_GET_BASE(i) \ 657 ((i) == 0 ? MXC_BASE_UART0 : \ 658 (i) == 1 ? MXC_BASE_UART1 : \ 659 (i) == 2 ? MXC_BASE_UART2 : \ 660 (i) == 3 ? MXC_BASE_UART3 : \ 661 (i) == 4 ? MXC_BASE_UART4 : \ 662 (i) == 5 ? MXC_BASE_UART5 : \ 663 0) 664 665 #define MXC_UART_GET_UART(i) \ 666 ((i) == 0 ? MXC_UART0 : \ 667 (i) == 1 ? MXC_UART1 : \ 668 (i) == 2 ? MXC_UART2 : \ 669 (i) == 3 ? MXC_UART3 : \ 670 (i) == 4 ? MXC_UART4 : \ 671 (i) == 5 ? MXC_UART5 : \ 672 0) 673 674 #define MXC_UART_GET_IDX(p) \ 675 ((p) == MXC_UART0 ? 0 : \ 676 (p) == MXC_UART1 ? 1 : \ 677 (p) == MXC_UART2 ? 2 : \ 678 (p) == MXC_UART3 ? 3 : \ 679 (p) == MXC_UART4 ? 4 : \ 680 (p) == MXC_UART5 ? 5 : \ 681 -1) 682 683 /******************************************************************************/ 684 /* SPI */ 685 #define MXC_SPI_INSTANCES (4) 686 #define MXC_SPI_SS_INSTANCES (4) 687 #define MXC_SPI_FIFO_DEPTH (32) 688 689 #define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) 690 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 691 #define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) 692 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 693 #define MXC_BASE_SPI2 ((uint32_t)0x40048000UL) 694 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) 695 #define MXC_BASE_SPI3 ((uint32_t)0x400BE000UL) 696 #define MXC_SPI3 ((mxc_spi_regs_t *)MXC_BASE_SPI3) 697 698 #define MXC_SPI_GET_IDX(p) \ 699 ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : (p) == MXC_SPI2 ? 2 : (p) == MXC_SPI3 ? 3 : -1) 700 701 #define MXC_SPI_GET_BASE(i) \ 702 ((i) == 0 ? MXC_BASE_SPI0 : \ 703 (i) == 1 ? MXC_BASE_SPI1 : \ 704 (i) == 2 ? MXC_BASE_SPI2 : \ 705 (i) == 3 ? MXC_BASE_SPI3 : \ 706 0) 707 708 #define MXC_SPI_GET_SPI(i) \ 709 ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : (i) == 2 ? MXC_SPI2 : (i) == 3 ? MXC_SPI3 : 0) 710 711 #define MXC_SPI_GET_IRQ(i) \ 712 (IRQn_Type)((i) == 0 ? SPI0_IRQn : \ 713 (i) == 1 ? SPI1_IRQn : \ 714 (i) == 2 ? SPI2_IRQn : \ 715 (i) == 3 ? SPI3_IRQn : \ 716 0) 717 718 /******************************************************************************/ 719 /* TRNG */ 720 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 721 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 722 723 /******************************************************************************/ 724 /* Ethernet MAC*/ 725 #define MXC_BASE_EMAC ((uint32_t)0x4004F000UL) 726 #define MXC_EMAC ((mxc_emac_regs_t *)MXC_BASE_EMAC) 727 728 /******************************************************************************/ 729 /* USB */ 730 #define MXC_BASE_USBHS ((uint32_t)0x400B1000UL) 731 #define MXC_USBHS ((mxc_usbhs_regs_t *)MXC_BASE_USBHS) 732 #define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */ 733 #define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */ 734 #define MXC_USBHS_MAX_PACKET 64 735 736 /******************************************************************************/ 737 /* SDHC */ 738 #define MXC_BASE_SDHC ((uint32_t)0x400B6000UL) 739 #define MXC_SDHC ((mxc_sdhc_regs_t *)MXC_BASE_SDHC) 740 741 /******************************************************************************/ 742 /* Bit Shifting */ 743 744 #define MXC_F_BIT_0 (1 << 0) 745 #define MXC_F_BIT_1 (1 << 1) 746 #define MXC_F_BIT_2 (1 << 2) 747 #define MXC_F_BIT_3 (1 << 3) 748 #define MXC_F_BIT_4 (1 << 4) 749 #define MXC_F_BIT_5 (1 << 5) 750 #define MXC_F_BIT_6 (1 << 6) 751 #define MXC_F_BIT_7 (1 << 7) 752 #define MXC_F_BIT_8 (1 << 8) 753 #define MXC_F_BIT_9 (1 << 9) 754 #define MXC_F_BIT_10 (1 << 10) 755 #define MXC_F_BIT_11 (1 << 11) 756 #define MXC_F_BIT_12 (1 << 12) 757 #define MXC_F_BIT_13 (1 << 13) 758 #define MXC_F_BIT_14 (1 << 14) 759 #define MXC_F_BIT_15 (1 << 15) 760 #define MXC_F_BIT_16 (1 << 16) 761 #define MXC_F_BIT_17 (1 << 17) 762 #define MXC_F_BIT_18 (1 << 18) 763 #define MXC_F_BIT_19 (1 << 19) 764 #define MXC_F_BIT_20 (1 << 20) 765 #define MXC_F_BIT_21 (1 << 21) 766 #define MXC_F_BIT_22 (1 << 22) 767 #define MXC_F_BIT_23 (1 << 23) 768 #define MXC_F_BIT_24 (1 << 24) 769 #define MXC_F_BIT_25 (1 << 25) 770 #define MXC_F_BIT_26 (1 << 26) 771 #define MXC_F_BIT_27 (1 << 27) 772 #define MXC_F_BIT_28 (1 << 28) 773 #define MXC_F_BIT_29 (1 << 29) 774 #define MXC_F_BIT_30 (1 << 30) 775 #define MXC_F_BIT_31 (1 << 31) 776 777 /******************************************************************************/ 778 /* Bit Banding */ 779 #define BITBAND(reg, bit) \ 780 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 781 ((bit) << 2)) 782 783 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 784 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 785 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 786 787 #define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) 788 789 /******************************************************************************/ 790 /* SCB CPACR */ 791 792 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 793 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 794 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 795 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 796 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 797 798 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_MAX32570_H_ 799
