1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_I2C_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_I2C_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup i2c 66 * @defgroup i2c_registers I2C_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 68 * @details Inter-Integrated Circuit. 69 */ 70 71 /** 72 * @ingroup i2c_registers 73 * Structure type to access the I2C Registers. 74 */ 75 typedef struct { 76 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */ 77 __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */ 78 __IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */ 79 __IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */ 80 __IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */ 81 __IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */ 82 __IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */ 83 __IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */ 84 __IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */ 85 __IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */ 86 __IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */ 87 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ 88 __IO uint32_t master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */ 89 __IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */ 90 __IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */ 91 __R uint32_t rsv_0x3c; 92 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ 93 __R uint32_t rsv_0x44; 94 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 95 __IO uint32_t slave_addr; /**< <tt>\b 0x4C:</tt> I2C SLAVE_ADDR Register */ 96 } mxc_i2c_regs_t; 97 98 /* Register offsets for module I2C */ 99 /** 100 * @ingroup i2c_registers 101 * @defgroup I2C_Register_Offsets Register Offsets 102 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 112 #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 115 #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 116 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 117 #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 118 #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 119 #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 120 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 121 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 122 #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */ 123 /**@} end of group i2c_registers */ 124 125 /** 126 * @ingroup i2c_registers 127 * @defgroup I2C_CTRL I2C_CTRL 128 * @brief Control Register0. 129 * @{ 130 */ 131 #define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */ 132 #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */ 133 134 #define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */ 135 #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */ 136 137 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */ 138 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */ 139 140 #define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */ 141 #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */ 142 143 #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */ 144 #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */ 145 146 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ 147 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ 148 149 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ 150 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ 151 152 #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ 153 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ 154 155 #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ 156 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ 157 158 #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */ 159 #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */ 160 161 #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ 162 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ 163 164 #define MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS_POS 12 /**< CTRL_SCL_CLK_STRETCH_DIS Position */ 165 #define MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS_POS)) /**< CTRL_SCL_CLK_STRETCH_DIS Mask */ 166 167 #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */ 168 #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */ 169 170 /**@} end of group I2C_CTRL_Register */ 171 172 /** 173 * @ingroup i2c_registers 174 * @defgroup I2C_STATUS I2C_STATUS 175 * @brief Status Register. 176 * @{ 177 */ 178 #define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */ 179 #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */ 180 181 #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */ 182 #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ 183 184 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ 185 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 186 187 #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */ 188 #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ 189 190 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ 191 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 192 193 #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */ 194 #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */ 195 196 /**@} end of group I2C_STATUS_Register */ 197 198 /** 199 * @ingroup i2c_registers 200 * @defgroup I2C_INT_FL0 I2C_INT_FL0 201 * @brief Interrupt Status Register. 202 * @{ 203 */ 204 #define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */ 205 #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */ 206 207 #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */ 208 #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */ 209 210 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */ 211 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */ 212 213 #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */ 214 #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */ 215 216 #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */ 217 #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */ 218 219 #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */ 220 #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */ 221 222 #define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */ 223 #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */ 224 225 #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */ 226 #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */ 227 228 #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */ 229 #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */ 230 231 #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */ 232 #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */ 233 234 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */ 235 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */ 236 237 #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */ 238 #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */ 239 240 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */ 241 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */ 242 243 #define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */ 244 #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */ 245 246 #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */ 247 #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */ 248 249 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */ 250 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */ 251 252 #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS 22 /**< INT_FL0_RD_ADDR_MATCH Position */ 253 #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS)) /**< INT_FL0_RD_ADDR_MATCH Mask */ 254 255 #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS 23 /**< INT_FL0_WR_ADDR_MATCH Position */ 256 #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS)) /**< INT_FL0_WR_ADDR_MATCH Mask */ 257 258 /**@} end of group I2C_INT_FL0_Register */ 259 260 /** 261 * @ingroup i2c_registers 262 * @defgroup I2C_INT_EN0 I2C_INT_EN0 263 * @brief Interrupt Enable Register. 264 * @{ 265 */ 266 #define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */ 267 #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */ 268 269 #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */ 270 #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */ 271 272 #define MXC_F_I2C_INT_EN0_GEN_CALL_ADDR_POS 2 /**< INT_EN0_GEN_CALL_ADDR Position */ 273 #define MXC_F_I2C_INT_EN0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CALL_ADDR_POS)) /**< INT_EN0_GEN_CALL_ADDR Mask */ 274 275 #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */ 276 #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */ 277 278 #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */ 279 #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */ 280 281 #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */ 282 #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */ 283 284 #define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */ 285 #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */ 286 287 #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */ 288 #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */ 289 290 #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */ 291 #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */ 292 293 #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */ 294 #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */ 295 296 #define MXC_F_I2C_INT_EN0_ADDR_NACK_ERR_POS 10 /**< INT_EN0_ADDR_NACK_ERR Position */ 297 #define MXC_F_I2C_INT_EN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_NACK_ERR_POS)) /**< INT_EN0_ADDR_NACK_ERR Mask */ 298 299 #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */ 300 #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */ 301 302 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */ 303 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */ 304 305 #define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */ 306 #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */ 307 308 #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */ 309 #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */ 310 311 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */ 312 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */ 313 314 #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS 22 /**< INT_EN0_RD_ADDR_MATCH Position */ 315 #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS)) /**< INT_EN0_RD_ADDR_MATCH Mask */ 316 317 #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS 23 /**< INT_EN0_WR_ADDR_MATCH Position */ 318 #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS)) /**< INT_EN0_WR_ADDR_MATCH Mask */ 319 320 /**@} end of group I2C_INT_EN0_Register */ 321 322 /** 323 * @ingroup i2c_registers 324 * @defgroup I2C_INT_FL1 I2C_INT_FL1 325 * @brief Interrupt Status Register 1. 326 * @{ 327 */ 328 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */ 329 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */ 330 331 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */ 332 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */ 333 334 #define MXC_F_I2C_INT_FL1_START_POS 2 /**< INT_FL1_START Position */ 335 #define MXC_F_I2C_INT_FL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS)) /**< INT_FL1_START Mask */ 336 337 /**@} end of group I2C_INT_FL1_Register */ 338 339 /** 340 * @ingroup i2c_registers 341 * @defgroup I2C_INT_EN1 I2C_INT_EN1 342 * @brief Interrupt Staus Register 1. 343 * @{ 344 */ 345 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */ 346 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */ 347 348 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */ 349 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */ 350 351 #define MXC_F_I2C_INT_EN1_START_POS 2 /**< INT_EN1_START Position */ 352 #define MXC_F_I2C_INT_EN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_START_POS)) /**< INT_EN1_START Mask */ 353 354 /**@} end of group I2C_INT_EN1_Register */ 355 356 /** 357 * @ingroup i2c_registers 358 * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN 359 * @brief FIFO Configuration Register. 360 * @{ 361 */ 362 #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */ 363 #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */ 364 365 #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */ 366 #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */ 367 368 /**@} end of group I2C_FIFO_LEN_Register */ 369 370 /** 371 * @ingroup i2c_registers 372 * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0 373 * @brief Receive Control Register 0. 374 * @{ 375 */ 376 #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ 377 #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ 378 379 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */ 380 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */ 381 382 #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */ 383 #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */ 384 385 /**@} end of group I2C_RX_CTRL0_Register */ 386 387 /** 388 * @ingroup i2c_registers 389 * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1 390 * @brief Receive Control Register 1. 391 * @{ 392 */ 393 #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */ 394 #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */ 395 396 #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */ 397 #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */ 398 399 /**@} end of group I2C_RX_CTRL1_Register */ 400 401 /** 402 * @ingroup i2c_registers 403 * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0 404 * @brief Transmit Control Register 0. 405 * @{ 406 */ 407 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */ 408 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */ 409 410 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */ 411 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */ 412 413 #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS 2 /**< TX_CTRL0_TX_AMGC_AFD Position */ 414 #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS)) /**< TX_CTRL0_TX_AMGC_AFD Mask */ 415 416 #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS 3 /**< TX_CTRL0_TX_AMW_AFD Position */ 417 #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS)) /**< TX_CTRL0_TX_AMW_AFD Mask */ 418 419 #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS 4 /**< TX_CTRL0_TX_AMR_AFD Position */ 420 #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS)) /**< TX_CTRL0_TX_AMR_AFD Mask */ 421 422 #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS 5 /**< TX_CTRL0_TX_NACK_AFD Position */ 423 #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS)) /**< TX_CTRL0_TX_NACK_AFD Mask */ 424 425 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */ 426 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */ 427 428 #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */ 429 #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */ 430 431 /**@} end of group I2C_TX_CTRL0_Register */ 432 433 /** 434 * @ingroup i2c_registers 435 * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1 436 * @brief Transmit Control Register 1. 437 * @{ 438 */ 439 #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */ 440 #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */ 441 442 #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */ 443 #define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */ 444 445 /**@} end of group I2C_TX_CTRL1_Register */ 446 447 /** 448 * @ingroup i2c_registers 449 * @defgroup I2C_FIFO I2C_FIFO 450 * @brief Data Register. 451 * @{ 452 */ 453 #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 454 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 455 456 /**@} end of group I2C_FIFO_Register */ 457 458 /** 459 * @ingroup i2c_registers 460 * @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL 461 * @brief Master Control Register. 462 * @{ 463 */ 464 #define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */ 465 #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */ 466 467 #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */ 468 #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */ 469 470 #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */ 471 #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */ 472 473 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */ 474 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */ 475 476 /**@} end of group I2C_MASTER_CTRL_Register */ 477 478 /** 479 * @ingroup i2c_registers 480 * @defgroup I2C_CLK_LO I2C_CLK_LO 481 * @brief Clock Low Register. 482 * @{ 483 */ 484 #define MXC_F_I2C_CLK_LO_SCL_LO_POS 0 /**< CLK_LO_SCL_LO Position */ 485 #define MXC_F_I2C_CLK_LO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_SCL_LO_POS)) /**< CLK_LO_SCL_LO Mask */ 486 487 /**@} end of group I2C_CLK_LO_Register */ 488 489 /** 490 * @ingroup i2c_registers 491 * @defgroup I2C_CLK_HI I2C_CLK_HI 492 * @brief Clock high Register. 493 * @{ 494 */ 495 #define MXC_F_I2C_CLK_HI_SCL_HI_POS 0 /**< CLK_HI_SCL_HI Position */ 496 #define MXC_F_I2C_CLK_HI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_SCL_HI_POS)) /**< CLK_HI_SCL_HI Mask */ 497 498 /**@} end of group I2C_CLK_HI_Register */ 499 500 /** 501 * @ingroup i2c_registers 502 * @defgroup I2C_TIMEOUT I2C_TIMEOUT 503 * @brief Timeout Register 504 * @{ 505 */ 506 #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ 507 #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ 508 509 /**@} end of group I2C_TIMEOUT_Register */ 510 511 /** 512 * @ingroup i2c_registers 513 * @defgroup I2C_DMA I2C_DMA 514 * @brief DMA Register. 515 * @{ 516 */ 517 #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ 518 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 519 520 #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ 521 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 522 523 /**@} end of group I2C_DMA_Register */ 524 525 /** 526 * @ingroup i2c_registers 527 * @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR 528 * @brief Slave Address Register. 529 * @{ 530 */ 531 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */ 532 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */ 533 534 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */ 535 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */ 536 537 /**@} end of group I2C_SLAVE_ADDR_Register */ 538 539 #ifdef __cplusplus 540 } 541 #endif 542 543 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_I2C_REGS_H_ 544
