1 /** 2 * @file htmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_HTMR_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_HTMR_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup htmr 66 * @defgroup htmr_registers HTMR_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 68 * @details High Speed Timer Module. 69 */ 70 71 /** 72 * @ingroup htmr_registers 73 * Structure type to access the HTMR Registers. 74 */ 75 typedef struct { 76 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> HTMR SEC Register */ 77 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> HTMR SSEC Register */ 78 __IO uint32_t ras; /**< <tt>\b 0x08:</tt> HTMR RAS Register */ 79 __IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> HTMR RSSA Register */ 80 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> HTMR CTRL Register */ 81 } mxc_htmr_regs_t; 82 83 /* Register offsets for module HTMR */ 84 /** 85 * @ingroup htmr_registers 86 * @defgroup HTMR_Register_Offsets Register Offsets 87 * @brief HTMR Peripheral Register Offsets from the HTMR Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_HTMR_SEC ((uint32_t)0x00000000UL) /**< Offset from HTMR Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_HTMR_SSEC ((uint32_t)0x00000004UL) /**< Offset from HTMR Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_HTMR_RAS ((uint32_t)0x00000008UL) /**< Offset from HTMR Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_HTMR_RSSA ((uint32_t)0x0000000CUL) /**< Offset from HTMR Base Address: <tt> 0x000C</tt> */ 94 #define MXC_R_HTMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from HTMR Base Address: <tt> 0x0010</tt> */ 95 /**@} end of group htmr_registers */ 96 97 /** 98 * @ingroup htmr_registers 99 * @defgroup HTMR_SEC HTMR_SEC 100 * @brief HTimer Long-Interval Counter. This register contains the 32 most significant 101 * bits of the counter. 102 * @{ 103 */ 104 #define MXC_F_HTMR_SEC_RTS_POS 0 /**< SEC_RTS Position */ 105 #define MXC_F_HTMR_SEC_RTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_HTMR_SEC_RTS_POS)) /**< SEC_RTS Mask */ 106 107 /**@} end of group HTMR_SEC_Register */ 108 109 /** 110 * @ingroup htmr_registers 111 * @defgroup HTMR_SSEC HTMR_SSEC 112 * @brief HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). 113 * HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 114 * @{ 115 */ 116 #define MXC_F_HTMR_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ 117 #define MXC_F_HTMR_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_HTMR_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ 118 119 /**@} end of group HTMR_SSEC_Register */ 120 121 /** 122 * @ingroup htmr_registers 123 * @defgroup HTMR_RAS HTMR_RAS 124 * @brief Long Interval Alarm. 125 * @{ 126 */ 127 #define MXC_F_HTMR_RAS_RAS_POS 0 /**< RAS_RAS Position */ 128 #define MXC_F_HTMR_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_HTMR_RAS_RAS_POS)) /**< RAS_RAS Mask */ 129 130 /**@} end of group HTMR_RAS_Register */ 131 132 /** 133 * @ingroup htmr_registers 134 * @defgroup HTMR_RSSA HTMR_RSSA 135 * @brief HTimer Short Interval Alarm. This register contains the reload value for the 136 * short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. 137 * @{ 138 */ 139 #define MXC_F_HTMR_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ 140 #define MXC_F_HTMR_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_HTMR_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ 141 142 /**@} end of group HTMR_RSSA_Register */ 143 144 /** 145 * @ingroup htmr_registers 146 * @defgroup HTMR_CTRL HTMR_CTRL 147 * @brief HTimer Control Register. 148 * @{ 149 */ 150 #define MXC_F_HTMR_CTRL_HTEN_POS 0 /**< CTRL_HTEN Position */ 151 #define MXC_F_HTMR_CTRL_HTEN ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_HTEN_POS)) /**< CTRL_HTEN Mask */ 152 153 #define MXC_F_HTMR_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ 154 #define MXC_F_HTMR_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ 155 156 #define MXC_F_HTMR_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ 157 #define MXC_F_HTMR_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ 158 159 #define MXC_F_HTMR_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 160 #define MXC_F_HTMR_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 161 162 #define MXC_F_HTMR_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 163 #define MXC_F_HTMR_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 164 165 #define MXC_F_HTMR_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ 166 #define MXC_F_HTMR_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ 167 168 #define MXC_F_HTMR_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ 169 #define MXC_F_HTMR_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ 170 171 #define MXC_F_HTMR_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ 172 #define MXC_F_HTMR_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ 173 174 #define MXC_F_HTMR_CTRL_WE_POS 15 /**< CTRL_WE Position */ 175 #define MXC_F_HTMR_CTRL_WE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_WE_POS)) /**< CTRL_WE Mask */ 176 177 /**@} end of group HTMR_CTRL_Register */ 178 179 #ifdef __cplusplus 180 } 181 #endif 182 183 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_HTMR_REGS_H_ 184
