1 /** 2 * @file ha_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HA Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_HA_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_HA_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup ha 66 * @defgroup ha_registers HA_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the HA Peripheral Module. 68 * @details Hardware Accelerator 69 */ 70 71 /** 72 * @ingroup ha_registers 73 * Structure type to access the HA Registers. 74 */ 75 typedef struct { 76 __I uint32_t ip; /**< <tt>\b 0x00:</tt> HA IP Register */ 77 __I uint32_t sp; /**< <tt>\b 0x04:</tt> HA SP Register */ 78 __I uint32_t dp0; /**< <tt>\b 0x08:</tt> HA DP0 Register */ 79 __I uint32_t dp1; /**< <tt>\b 0x0C:</tt> HA DP1 Register */ 80 __I uint32_t bp; /**< <tt>\b 0x10:</tt> HA BP Register */ 81 __I uint32_t offs; /**< <tt>\b 0x14:</tt> HA OFFS Register */ 82 __I uint32_t lc0; /**< <tt>\b 0x18:</tt> HA LC0 Register */ 83 __I uint32_t lc1; /**< <tt>\b 0x1C:</tt> HA LC1 Register */ 84 __I uint32_t a0; /**< <tt>\b 0x20:</tt> HA A0 Register */ 85 __I uint32_t a1; /**< <tt>\b 0x24:</tt> HA A1 Register */ 86 __I uint32_t a2; /**< <tt>\b 0x28:</tt> HA A2 Register */ 87 __I uint32_t a3; /**< <tt>\b 0x2C:</tt> HA A3 Register */ 88 __I uint32_t wdcn; /**< <tt>\b 0x30:</tt> HA WDCN Register */ 89 __R uint32_t rsv_0x34_0x7f[19]; 90 __IO uint32_t int_mux_ctrl0; /**< <tt>\b 0x80:</tt> HA INT_MUX_CTRL0 Register */ 91 __IO uint32_t int_mux_ctrl1; /**< <tt>\b 0x84:</tt> HA INT_MUX_CTRL1 Register */ 92 __IO uint32_t int_mux_ctrl2; /**< <tt>\b 0x88:</tt> HA INT_MUX_CTRL2 Register */ 93 __IO uint32_t int_mux_ctrl3; /**< <tt>\b 0x8C:</tt> HA INT_MUX_CTRL3 Register */ 94 __IO uint32_t ip_addr; /**< <tt>\b 0x90:</tt> HA IP_ADDR Register */ 95 __IO uint32_t ctrl; /**< <tt>\b 0x94:</tt> HA CTRL Register */ 96 __R uint32_t rsv_0x98_0x9f[2]; 97 __IO uint32_t int_in_ctrl; /**< <tt>\b 0xA0:</tt> HA INT_IN_CTRL Register */ 98 __IO uint32_t int_in_flag; /**< <tt>\b 0xA4:</tt> HA INT_IN_FLAG Register */ 99 __IO uint32_t int_in_ie; /**< <tt>\b 0xA8:</tt> HA INT_IN_IE Register */ 100 __R uint32_t rsv_0xac; 101 __IO uint32_t irq_flag; /**< <tt>\b 0xB0:</tt> HA IRQ_FLAG Register */ 102 __IO uint32_t irq_ie; /**< <tt>\b 0xB4:</tt> HA IRQ_IE Register */ 103 } mxc_ha_regs_t; 104 105 /* Register offsets for module HA */ 106 /** 107 * @ingroup ha_registers 108 * @defgroup HA_Register_Offsets Register Offsets 109 * @brief HA Peripheral Register Offsets from the HA Base Peripheral Address. 110 * @{ 111 */ 112 #define MXC_R_HA_IP ((uint32_t)0x00000000UL) /**< Offset from HA Base Address: <tt> 0x0000</tt> */ 113 #define MXC_R_HA_SP ((uint32_t)0x00000004UL) /**< Offset from HA Base Address: <tt> 0x0004</tt> */ 114 #define MXC_R_HA_DP0 ((uint32_t)0x00000008UL) /**< Offset from HA Base Address: <tt> 0x0008</tt> */ 115 #define MXC_R_HA_DP1 ((uint32_t)0x0000000CUL) /**< Offset from HA Base Address: <tt> 0x000C</tt> */ 116 #define MXC_R_HA_BP ((uint32_t)0x00000010UL) /**< Offset from HA Base Address: <tt> 0x0010</tt> */ 117 #define MXC_R_HA_OFFS ((uint32_t)0x00000014UL) /**< Offset from HA Base Address: <tt> 0x0014</tt> */ 118 #define MXC_R_HA_LC0 ((uint32_t)0x00000018UL) /**< Offset from HA Base Address: <tt> 0x0018</tt> */ 119 #define MXC_R_HA_LC1 ((uint32_t)0x0000001CUL) /**< Offset from HA Base Address: <tt> 0x001C</tt> */ 120 #define MXC_R_HA_A0 ((uint32_t)0x00000020UL) /**< Offset from HA Base Address: <tt> 0x0020</tt> */ 121 #define MXC_R_HA_A1 ((uint32_t)0x00000024UL) /**< Offset from HA Base Address: <tt> 0x0024</tt> */ 122 #define MXC_R_HA_A2 ((uint32_t)0x00000028UL) /**< Offset from HA Base Address: <tt> 0x0028</tt> */ 123 #define MXC_R_HA_A3 ((uint32_t)0x0000002CUL) /**< Offset from HA Base Address: <tt> 0x002C</tt> */ 124 #define MXC_R_HA_WDCN ((uint32_t)0x00000030UL) /**< Offset from HA Base Address: <tt> 0x0030</tt> */ 125 #define MXC_R_HA_INT_MUX_CTRL0 ((uint32_t)0x00000080UL) /**< Offset from HA Base Address: <tt> 0x0080</tt> */ 126 #define MXC_R_HA_INT_MUX_CTRL1 ((uint32_t)0x00000084UL) /**< Offset from HA Base Address: <tt> 0x0084</tt> */ 127 #define MXC_R_HA_INT_MUX_CTRL2 ((uint32_t)0x00000088UL) /**< Offset from HA Base Address: <tt> 0x0088</tt> */ 128 #define MXC_R_HA_INT_MUX_CTRL3 ((uint32_t)0x0000008CUL) /**< Offset from HA Base Address: <tt> 0x008C</tt> */ 129 #define MXC_R_HA_IP_ADDR ((uint32_t)0x00000090UL) /**< Offset from HA Base Address: <tt> 0x0090</tt> */ 130 #define MXC_R_HA_CTRL ((uint32_t)0x00000094UL) /**< Offset from HA Base Address: <tt> 0x0094</tt> */ 131 #define MXC_R_HA_INT_IN_CTRL ((uint32_t)0x000000A0UL) /**< Offset from HA Base Address: <tt> 0x00A0</tt> */ 132 #define MXC_R_HA_INT_IN_FLAG ((uint32_t)0x000000A4UL) /**< Offset from HA Base Address: <tt> 0x00A4</tt> */ 133 #define MXC_R_HA_INT_IN_IE ((uint32_t)0x000000A8UL) /**< Offset from HA Base Address: <tt> 0x00A8</tt> */ 134 #define MXC_R_HA_IRQ_FLAG ((uint32_t)0x000000B0UL) /**< Offset from HA Base Address: <tt> 0x00B0</tt> */ 135 #define MXC_R_HA_IRQ_IE ((uint32_t)0x000000B4UL) /**< Offset from HA Base Address: <tt> 0x00B4</tt> */ 136 /**@} end of group ha_registers */ 137 138 /** 139 * @ingroup ha_registers 140 * @defgroup HA_INT_MUX_CTRL0 HA_INT_MUX_CTRL0 141 * @brief Interrupt Mux Control 0. 142 * @{ 143 */ 144 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL16_POS 0 /**< INT_MUX_CTRL0_INTSEL16 Position */ 145 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL16 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL0_INTSEL16_POS)) /**< INT_MUX_CTRL0_INTSEL16 Mask */ 146 147 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL17_POS 8 /**< INT_MUX_CTRL0_INTSEL17 Position */ 148 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL17 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL0_INTSEL17_POS)) /**< INT_MUX_CTRL0_INTSEL17 Mask */ 149 150 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL18_POS 16 /**< INT_MUX_CTRL0_INTSEL18 Position */ 151 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL18 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL0_INTSEL18_POS)) /**< INT_MUX_CTRL0_INTSEL18 Mask */ 152 153 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL19_POS 24 /**< INT_MUX_CTRL0_INTSEL19 Position */ 154 #define MXC_F_HA_INT_MUX_CTRL0_INTSEL19 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL0_INTSEL19_POS)) /**< INT_MUX_CTRL0_INTSEL19 Mask */ 155 156 /**@} end of group HA_INT_MUX_CTRL0_Register */ 157 158 /** 159 * @ingroup ha_registers 160 * @defgroup HA_INT_MUX_CTRL1 HA_INT_MUX_CTRL1 161 * @brief Interrupt Mux Control 1. 162 * @{ 163 */ 164 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL20_POS 0 /**< INT_MUX_CTRL1_INTSEL20 Position */ 165 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL20 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL1_INTSEL20_POS)) /**< INT_MUX_CTRL1_INTSEL20 Mask */ 166 167 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL21_POS 8 /**< INT_MUX_CTRL1_INTSEL21 Position */ 168 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL21 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL1_INTSEL21_POS)) /**< INT_MUX_CTRL1_INTSEL21 Mask */ 169 170 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL22_POS 16 /**< INT_MUX_CTRL1_INTSEL22 Position */ 171 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL22 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL1_INTSEL22_POS)) /**< INT_MUX_CTRL1_INTSEL22 Mask */ 172 173 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL23_POS 24 /**< INT_MUX_CTRL1_INTSEL23 Position */ 174 #define MXC_F_HA_INT_MUX_CTRL1_INTSEL23 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL1_INTSEL23_POS)) /**< INT_MUX_CTRL1_INTSEL23 Mask */ 175 176 /**@} end of group HA_INT_MUX_CTRL1_Register */ 177 178 /** 179 * @ingroup ha_registers 180 * @defgroup HA_INT_MUX_CTRL2 HA_INT_MUX_CTRL2 181 * @brief Interrupt Mux Control 2. 182 * @{ 183 */ 184 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL24_POS 0 /**< INT_MUX_CTRL2_INTSEL24 Position */ 185 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL24 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL2_INTSEL24_POS)) /**< INT_MUX_CTRL2_INTSEL24 Mask */ 186 187 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL25_POS 8 /**< INT_MUX_CTRL2_INTSEL25 Position */ 188 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL25 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL2_INTSEL25_POS)) /**< INT_MUX_CTRL2_INTSEL25 Mask */ 189 190 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL26_POS 16 /**< INT_MUX_CTRL2_INTSEL26 Position */ 191 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL26 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL2_INTSEL26_POS)) /**< INT_MUX_CTRL2_INTSEL26 Mask */ 192 193 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL27_POS 24 /**< INT_MUX_CTRL2_INTSEL27 Position */ 194 #define MXC_F_HA_INT_MUX_CTRL2_INTSEL27 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL2_INTSEL27_POS)) /**< INT_MUX_CTRL2_INTSEL27 Mask */ 195 196 /**@} end of group HA_INT_MUX_CTRL2_Register */ 197 198 /** 199 * @ingroup ha_registers 200 * @defgroup HA_INT_MUX_CTRL3 HA_INT_MUX_CTRL3 201 * @brief Interrupt Mux Control 3. 202 * @{ 203 */ 204 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL28_POS 0 /**< INT_MUX_CTRL3_INTSEL28 Position */ 205 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL28 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL3_INTSEL28_POS)) /**< INT_MUX_CTRL3_INTSEL28 Mask */ 206 207 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL29_POS 8 /**< INT_MUX_CTRL3_INTSEL29 Position */ 208 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL29 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL3_INTSEL29_POS)) /**< INT_MUX_CTRL3_INTSEL29 Mask */ 209 210 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL30_POS 16 /**< INT_MUX_CTRL3_INTSEL30 Position */ 211 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL30 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL3_INTSEL30_POS)) /**< INT_MUX_CTRL3_INTSEL30 Mask */ 212 213 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL31_POS 24 /**< INT_MUX_CTRL3_INTSEL31 Position */ 214 #define MXC_F_HA_INT_MUX_CTRL3_INTSEL31 ((uint32_t)(0xFFUL << MXC_F_HA_INT_MUX_CTRL3_INTSEL31_POS)) /**< INT_MUX_CTRL3_INTSEL31 Mask */ 215 216 /**@} end of group HA_INT_MUX_CTRL3_Register */ 217 218 /** 219 * @ingroup ha_registers 220 * @defgroup HA_IP_ADDR HA_IP_ADDR 221 * @brief Configurable starting IP address for Q30E. 222 * @{ 223 */ 224 #define MXC_F_HA_IP_ADDR_START_IP_ADDR_POS 0 /**< IP_ADDR_START_IP_ADDR Position */ 225 #define MXC_F_HA_IP_ADDR_START_IP_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_HA_IP_ADDR_START_IP_ADDR_POS)) /**< IP_ADDR_START_IP_ADDR Mask */ 226 227 /**@} end of group HA_IP_ADDR_Register */ 228 229 /** 230 * @ingroup ha_registers 231 * @defgroup HA_CTRL HA_CTRL 232 * @brief Control Register. 233 * @{ 234 */ 235 #define MXC_F_HA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 236 #define MXC_F_HA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_HA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 237 238 /**@} end of group HA_CTRL_Register */ 239 240 /** 241 * @ingroup ha_registers 242 * @defgroup HA_INT_IN_CTRL HA_INT_IN_CTRL 243 * @brief Interrupt Input From CPU Control Register. 244 * @{ 245 */ 246 #define MXC_F_HA_INT_IN_CTRL_INTSET_POS 0 /**< INT_IN_CTRL_INTSET Position */ 247 #define MXC_F_HA_INT_IN_CTRL_INTSET ((uint32_t)(0x1UL << MXC_F_HA_INT_IN_CTRL_INTSET_POS)) /**< INT_IN_CTRL_INTSET Mask */ 248 249 /**@} end of group HA_INT_IN_CTRL_Register */ 250 251 /** 252 * @ingroup ha_registers 253 * @defgroup HA_INT_IN_FLAG HA_INT_IN_FLAG 254 * @brief Interrupt Input From CPU Flag. 255 * @{ 256 */ 257 #define MXC_F_HA_INT_IN_FLAG_INTFLAG_POS 0 /**< INT_IN_FLAG_INTFLAG Position */ 258 #define MXC_F_HA_INT_IN_FLAG_INTFLAG ((uint32_t)(0x1UL << MXC_F_HA_INT_IN_FLAG_INTFLAG_POS)) /**< INT_IN_FLAG_INTFLAG Mask */ 259 260 /**@} end of group HA_INT_IN_FLAG_Register */ 261 262 /** 263 * @ingroup ha_registers 264 * @defgroup HA_INT_IN_IE HA_INT_IN_IE 265 * @brief Interrupt Input From CPU Enable. 266 * @{ 267 */ 268 #define MXC_F_HA_INT_IN_IE_INT_IN_EN_POS 0 /**< INT_IN_IE_INT_IN_EN Position */ 269 #define MXC_F_HA_INT_IN_IE_INT_IN_EN ((uint32_t)(0x1UL << MXC_F_HA_INT_IN_IE_INT_IN_EN_POS)) /**< INT_IN_IE_INT_IN_EN Mask */ 270 271 /**@} end of group HA_INT_IN_IE_Register */ 272 273 /** 274 * @ingroup ha_registers 275 * @defgroup HA_IRQ_FLAG HA_IRQ_FLAG 276 * @brief Interrupt Output To CPU Flag. 277 * @{ 278 */ 279 #define MXC_F_HA_IRQ_FLAG_IRQ_FLAG_POS 0 /**< IRQ_FLAG_IRQ_FLAG Position */ 280 #define MXC_F_HA_IRQ_FLAG_IRQ_FLAG ((uint32_t)(0x1UL << MXC_F_HA_IRQ_FLAG_IRQ_FLAG_POS)) /**< IRQ_FLAG_IRQ_FLAG Mask */ 281 282 /**@} end of group HA_IRQ_FLAG_Register */ 283 284 /** 285 * @ingroup ha_registers 286 * @defgroup HA_IRQ_IE HA_IRQ_IE 287 * @brief Interrupt Output To CPU Control Register. 288 * @{ 289 */ 290 #define MXC_F_HA_IRQ_IE_IRQ_EN_POS 0 /**< IRQ_IE_IRQ_EN Position */ 291 #define MXC_F_HA_IRQ_IE_IRQ_EN ((uint32_t)(0x1UL << MXC_F_HA_IRQ_IE_IRQ_EN_POS)) /**< IRQ_IE_IRQ_EN Mask */ 292 293 /**@} end of group HA_IRQ_IE_Register */ 294 295 #ifdef __cplusplus 296 } 297 #endif 298 299 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_HA_REGS_H_ 300
