1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_GCR_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_GCR_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup gcr 66 * @defgroup gcr_registers GCR_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 68 * @details Global Control Registers. 69 */ 70 71 /** 72 * @ingroup gcr_registers 73 * Structure type to access the GCR Registers. 74 */ 75 typedef struct { 76 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 77 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 78 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 79 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 80 __R uint32_t rsv_0x10_0x17[2]; 81 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 82 __R uint32_t rsv_0x1c_0x23[2]; 83 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 84 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 85 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 86 __R uint32_t rsv_0x30; 87 __IO uint32_t scck; /**< <tt>\b 0x34:</tt> GCR SCCK Register */ 88 __R uint32_t rsv_0x38_0x3f[2]; 89 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 90 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 91 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 92 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 93 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 94 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 95 __IO uint32_t ipocnt; /**< <tt>\b 0x58:</tt> GCR IPOCNT Register */ 96 __R uint32_t rsv_0x5c_0x63[2]; 97 __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */ 98 __IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */ 99 __IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */ 100 __IO uint32_t eccaddr; /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */ 101 __IO uint32_t nfc_ldocr; /**< <tt>\b 0x74:</tt> GCR NFC_LDOCR Register */ 102 __IO uint32_t nfcldo_dly; /**< <tt>\b 0x78:</tt> GCR NFCLDO_DLY Register */ 103 } mxc_gcr_regs_t; 104 105 /* Register offsets for module GCR */ 106 /** 107 * @ingroup gcr_registers 108 * @defgroup GCR_Register_Offsets Register Offsets 109 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 110 * @{ 111 */ 112 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 113 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 114 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 115 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 116 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 117 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 118 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 119 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 120 #define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> 0x0034</tt> */ 121 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 122 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 123 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 124 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 125 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 126 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 127 #define MXC_R_GCR_IPOCNT ((uint32_t)0x00000058UL) /**< Offset from GCR Base Address: <tt> 0x0058</tt> */ 128 #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 129 #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 130 #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 131 #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 132 #define MXC_R_GCR_NFC_LDOCR ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: <tt> 0x0074</tt> */ 133 #define MXC_R_GCR_NFCLDO_DLY ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: <tt> 0x0078</tt> */ 134 /**@} end of group gcr_registers */ 135 136 /** 137 * @ingroup gcr_registers 138 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 139 * @brief System Control. 140 * @{ 141 */ 142 #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 0 /**< SYSCTRL_BSTAPEN Position */ 143 #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ 144 145 #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ 146 #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ 147 #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ 148 #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ 149 #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ 150 #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ 151 152 #define MXC_F_GCR_SYSCTRL_FLASH0_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH0_PAGE_FLIP Position */ 153 #define MXC_F_GCR_SYSCTRL_FLASH0_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH0_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH0_PAGE_FLIP Mask */ 154 155 #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ 156 #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ 157 158 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ 159 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ 160 161 #define MXC_F_GCR_SYSCTRL_SRCC_FLUSH_POS 7 /**< SYSCTRL_SRCC_FLUSH Position */ 162 #define MXC_F_GCR_SYSCTRL_SRCC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SRCC_FLUSH_POS)) /**< SYSCTRL_SRCC_FLUSH Mask */ 163 164 #define MXC_F_GCR_SYSCTRL_SRCC_DIS_POS 9 /**< SYSCTRL_SRCC_DIS Position */ 165 #define MXC_F_GCR_SYSCTRL_SRCC_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SRCC_DIS_POS)) /**< SYSCTRL_SRCC_DIS Mask */ 166 167 #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ 168 #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ 169 170 #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ 171 #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ 172 173 /**@} end of group GCR_SYSCTRL_Register */ 174 175 /** 176 * @ingroup gcr_registers 177 * @defgroup GCR_RST0 GCR_RST0 178 * @brief Reset. 179 * @{ 180 */ 181 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 182 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 183 184 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 185 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 186 187 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 188 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 189 190 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 191 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 192 193 #define MXC_F_GCR_RST0_GPIO2_POS 4 /**< RST0_GPIO2 Position */ 194 #define MXC_F_GCR_RST0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO2_POS)) /**< RST0_GPIO2 Mask */ 195 196 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 197 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 198 199 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 200 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 201 202 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 203 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 204 205 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 206 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 207 208 #define MXC_F_GCR_RST0_TMR4_POS 9 /**< RST0_TMR4 Position */ 209 #define MXC_F_GCR_RST0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR4_POS)) /**< RST0_TMR4 Mask */ 210 211 #define MXC_F_GCR_RST0_TMR5_POS 10 /**< RST0_TMR5 Position */ 212 #define MXC_F_GCR_RST0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR5_POS)) /**< RST0_TMR5 Mask */ 213 214 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 215 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 216 217 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 218 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 219 220 #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ 221 #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ 222 223 #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ 224 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 225 226 #define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ 227 #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ 228 229 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 230 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 231 232 #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ 233 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ 234 235 #define MXC_F_GCR_RST0_CRYPTO_POS 18 /**< RST0_CRYPTO Position */ 236 #define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS)) /**< RST0_CRYPTO Mask */ 237 238 #define MXC_F_GCR_RST0_TMR6_POS 20 /**< RST0_TMR6 Position */ 239 #define MXC_F_GCR_RST0_TMR6 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR6_POS)) /**< RST0_TMR6 Mask */ 240 241 #define MXC_F_GCR_RST0_TMR7_POS 21 /**< RST0_TMR7 Position */ 242 #define MXC_F_GCR_RST0_TMR7 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR7_POS)) /**< RST0_TMR7 Mask */ 243 244 #define MXC_F_GCR_RST0_CLCD_POS 22 /**< RST0_CLCD Position */ 245 #define MXC_F_GCR_RST0_CLCD ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CLCD_POS)) /**< RST0_CLCD Mask */ 246 247 #define MXC_F_GCR_RST0_USB_POS 23 /**< RST0_USB Position */ 248 #define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) /**< RST0_USB Mask */ 249 250 #define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ 251 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ 252 253 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 254 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 255 256 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 257 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 258 259 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 260 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 261 262 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 263 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 264 265 /**@} end of group GCR_RST0_Register */ 266 267 /** 268 * @ingroup gcr_registers 269 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 270 * @brief Clock Control. 271 * @{ 272 */ 273 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 274 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 275 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 276 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 277 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 278 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 279 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 280 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 281 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 282 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 283 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 284 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 285 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 286 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 287 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 288 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 289 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 290 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 291 292 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 293 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 294 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ 295 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ 296 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ 297 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ 298 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 299 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 300 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 301 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 302 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 303 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 304 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ 305 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ 306 307 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 308 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 309 310 #define MXC_F_GCR_CLKCTRL_CCD_POS 15 /**< CLKCTRL_CCD Position */ 311 #define MXC_F_GCR_CLKCTRL_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_CCD_POS)) /**< CLKCTRL_CCD Mask */ 312 313 #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ 314 #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ 315 316 #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 317 #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 318 319 #define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ 320 #define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ 321 322 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ 323 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 324 325 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 326 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 327 328 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 329 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 330 331 #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ 332 #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ 333 334 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ 335 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ 336 337 #define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ 338 #define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ 339 340 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ 341 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 342 343 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 344 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 345 346 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 347 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 348 349 /**@} end of group GCR_CLKCTRL_Register */ 350 351 /** 352 * @ingroup gcr_registers 353 * @defgroup GCR_PM GCR_PM 354 * @brief Power Management. 355 * @{ 356 */ 357 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 358 #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 359 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 360 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 361 #define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ 362 #define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ 363 #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ 364 #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ 365 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 366 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 367 368 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 369 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 370 371 #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ 372 #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ 373 374 #define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ 375 #define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ 376 377 #define MXC_F_GCR_PM_HA0_WE_POS 7 /**< PM_HA0_WE Position */ 378 #define MXC_F_GCR_PM_HA0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_HA0_WE_POS)) /**< PM_HA0_WE Mask */ 379 380 #define MXC_F_GCR_PM_HA1_WE_POS 9 /**< PM_HA1_WE Position */ 381 #define MXC_F_GCR_PM_HA1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_HA1_WE_POS)) /**< PM_HA1_WE Mask */ 382 383 #define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ 384 #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ 385 386 #define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ 387 #define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ 388 389 #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ 390 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 391 392 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 393 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 394 395 #define MXC_F_GCR_PM_NFC_PD_POS 18 /**< PM_NFC_PD Position */ 396 #define MXC_F_GCR_PM_NFC_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_NFC_PD_POS)) /**< PM_NFC_PD Mask */ 397 398 #define MXC_F_GCR_PM_XTALBP_POS 20 /**< PM_XTALBP Position */ 399 #define MXC_F_GCR_PM_XTALBP ((uint32_t)(0x1UL << MXC_F_GCR_PM_XTALBP_POS)) /**< PM_XTALBP Mask */ 400 401 /**@} end of group GCR_PM_Register */ 402 403 /** 404 * @ingroup gcr_registers 405 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 406 * @brief Peripheral Clock Divider. 407 * @{ 408 */ 409 #define MXC_F_GCR_PCLKDIV_PCF_POS 0 /**< PCLKDIV_PCF Position */ 410 #define MXC_F_GCR_PCLKDIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_PCF_POS)) /**< PCLKDIV_PCF Mask */ 411 #define MXC_V_GCR_PCLKDIV_PCF_96MHZ ((uint32_t)0x2UL) /**< PCLKDIV_PCF_96MHZ Value */ 412 #define MXC_S_GCR_PCLKDIV_PCF_96MHZ (MXC_V_GCR_PCLKDIV_PCF_96MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_96MHZ Setting */ 413 #define MXC_V_GCR_PCLKDIV_PCF_48MHZ ((uint32_t)0x3UL) /**< PCLKDIV_PCF_48MHZ Value */ 414 #define MXC_S_GCR_PCLKDIV_PCF_48MHZ (MXC_V_GCR_PCLKDIV_PCF_48MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_48MHZ Setting */ 415 #define MXC_V_GCR_PCLKDIV_PCF_24MHZ ((uint32_t)0x4UL) /**< PCLKDIV_PCF_24MHZ Value */ 416 #define MXC_S_GCR_PCLKDIV_PCF_24MHZ (MXC_V_GCR_PCLKDIV_PCF_24MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_24MHZ Setting */ 417 #define MXC_V_GCR_PCLKDIV_PCF_12MHZ ((uint32_t)0x5UL) /**< PCLKDIV_PCF_12MHZ Value */ 418 #define MXC_S_GCR_PCLKDIV_PCF_12MHZ (MXC_V_GCR_PCLKDIV_PCF_12MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_12MHZ Setting */ 419 #define MXC_V_GCR_PCLKDIV_PCF_6MHZ ((uint32_t)0x6UL) /**< PCLKDIV_PCF_6MHZ Value */ 420 #define MXC_S_GCR_PCLKDIV_PCF_6MHZ (MXC_V_GCR_PCLKDIV_PCF_6MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_6MHZ Setting */ 421 #define MXC_V_GCR_PCLKDIV_PCF_3MHZ ((uint32_t)0x7UL) /**< PCLKDIV_PCF_3MHZ Value */ 422 #define MXC_S_GCR_PCLKDIV_PCF_3MHZ (MXC_V_GCR_PCLKDIV_PCF_3MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_3MHZ Setting */ 423 424 #define MXC_F_GCR_PCLKDIV_PCFWEN_POS 3 /**< PCLKDIV_PCFWEN Position */ 425 #define MXC_F_GCR_PCLKDIV_PCFWEN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_PCFWEN_POS)) /**< PCLKDIV_PCFWEN Mask */ 426 427 #define MXC_F_GCR_PCLKDIV_SDHCFRQ_POS 7 /**< PCLKDIV_SDHCFRQ Position */ 428 #define MXC_F_GCR_PCLKDIV_SDHCFRQ ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_SDHCFRQ_POS)) /**< PCLKDIV_SDHCFRQ Mask */ 429 430 #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ 431 #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ 432 433 #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 14 /**< PCLKDIV_AON_CLKDIV Position */ 434 #define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ 435 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV_4 Value */ 436 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_4 Setting */ 437 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV_8 Value */ 438 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_8 Setting */ 439 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV_16 Value */ 440 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_16 Setting */ 441 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV_32 Value */ 442 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_32 Setting */ 443 444 /**@} end of group GCR_PCLKDIV_Register */ 445 446 /** 447 * @ingroup gcr_registers 448 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 449 * @brief Peripheral Clock Disable. 450 * @{ 451 */ 452 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 453 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 454 455 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 456 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 457 458 #define MXC_F_GCR_PCLKDIS0_GPIO2_POS 2 /**< PCLKDIS0_GPIO2 Position */ 459 #define MXC_F_GCR_PCLKDIS0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO2_POS)) /**< PCLKDIS0_GPIO2 Mask */ 460 461 #define MXC_F_GCR_PCLKDIS0_USB_POS 3 /**< PCLKDIS0_USB Position */ 462 #define MXC_F_GCR_PCLKDIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_USB_POS)) /**< PCLKDIS0_USB Mask */ 463 464 #define MXC_F_GCR_PCLKDIS0_CLCD_POS 4 /**< PCLKDIS0_CLCD Position */ 465 #define MXC_F_GCR_PCLKDIS0_CLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CLCD_POS)) /**< PCLKDIS0_CLCD Mask */ 466 467 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 468 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 469 470 #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ 471 #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ 472 473 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ 474 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 475 476 #define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ 477 #define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ 478 479 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 480 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 481 482 #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ 483 #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ 484 485 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 486 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 487 488 #define MXC_F_GCR_PCLKDIS0_CRYPTO_POS 14 /**< PCLKDIS0_CRYPTO Position */ 489 #define MXC_F_GCR_PCLKDIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CRYPTO_POS)) /**< PCLKDIS0_CRYPTO Mask */ 490 491 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 492 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 493 494 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 495 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 496 497 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 498 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 499 500 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 501 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 502 503 #define MXC_F_GCR_PCLKDIS0_TMR4_POS 19 /**< PCLKDIS0_TMR4 Position */ 504 #define MXC_F_GCR_PCLKDIS0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR4_POS)) /**< PCLKDIS0_TMR4 Mask */ 505 506 #define MXC_F_GCR_PCLKDIS0_TMR5_POS 20 /**< PCLKDIS0_TMR5 Position */ 507 #define MXC_F_GCR_PCLKDIS0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR5_POS)) /**< PCLKDIS0_TMR5 Mask */ 508 509 #define MXC_F_GCR_PCLKDIS0_KBD_POS 22 /**< PCLKDIS0_KBD Position */ 510 #define MXC_F_GCR_PCLKDIS0_KBD ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_KBD_POS)) /**< PCLKDIS0_KBD Mask */ 511 512 #define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ 513 #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ 514 515 #define MXC_F_GCR_PCLKDIS0_TMR6_POS 24 /**< PCLKDIS0_TMR6 Position */ 516 #define MXC_F_GCR_PCLKDIS0_TMR6 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR6_POS)) /**< PCLKDIS0_TMR6 Mask */ 517 518 #define MXC_F_GCR_PCLKDIS0_TMR7_POS 25 /**< PCLKDIS0_TMR7 Position */ 519 #define MXC_F_GCR_PCLKDIS0_TMR7 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR7_POS)) /**< PCLKDIS0_TMR7 Mask */ 520 521 #define MXC_F_GCR_PCLKDIS0_HTMR0_POS 26 /**< PCLKDIS0_HTMR0 Position */ 522 #define MXC_F_GCR_PCLKDIS0_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_HTMR0_POS)) /**< PCLKDIS0_HTMR0 Mask */ 523 524 #define MXC_F_GCR_PCLKDIS0_HTMR1_POS 27 /**< PCLKDIS0_HTMR1 Position */ 525 #define MXC_F_GCR_PCLKDIS0_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_HTMR1_POS)) /**< PCLKDIS0_HTMR1 Mask */ 526 527 #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ 528 #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ 529 530 #define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ 531 #define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ 532 533 #define MXC_F_GCR_PCLKDIS0_SPIXIP_POS 30 /**< PCLKDIS0_SPIXIP Position */ 534 #define MXC_F_GCR_PCLKDIS0_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIXIP_POS)) /**< PCLKDIS0_SPIXIP Mask */ 535 536 #define MXC_F_GCR_PCLKDIS0_SPIM_POS 31 /**< PCLKDIS0_SPIM Position */ 537 #define MXC_F_GCR_PCLKDIS0_SPIM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPIM_POS)) /**< PCLKDIS0_SPIM Mask */ 538 539 /**@} end of group GCR_PCLKDIS0_Register */ 540 541 /** 542 * @ingroup gcr_registers 543 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 544 * @brief Memory Clock Control Register. 545 * @{ 546 */ 547 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 548 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 549 550 #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ 551 #define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ 552 553 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 16 /**< MEMCTRL_RAM0LS_EN Position */ 554 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ 555 556 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 17 /**< MEMCTRL_RAM1LS_EN Position */ 557 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ 558 559 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 18 /**< MEMCTRL_RAM2LS_EN Position */ 560 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ 561 562 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 19 /**< MEMCTRL_RAM3LS_EN Position */ 563 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ 564 565 #define MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS 20 /**< MEMCTRL_RAM4LS_EN Position */ 566 #define MXC_F_GCR_MEMCTRL_RAM4LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS)) /**< MEMCTRL_RAM4LS_EN Mask */ 567 568 #define MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS 21 /**< MEMCTRL_RAM5LS_EN Position */ 569 #define MXC_F_GCR_MEMCTRL_RAM5LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS)) /**< MEMCTRL_RAM5LS_EN Mask */ 570 571 #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 24 /**< MEMCTRL_ICC0LS_EN Position */ 572 #define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ 573 574 #define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS 25 /**< MEMCTRL_ICCXIPLS_EN Position */ 575 #define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS)) /**< MEMCTRL_ICCXIPLS_EN Mask */ 576 577 #define MXC_F_GCR_MEMCTRL_SRCCLS_EN_POS 26 /**< MEMCTRL_SRCCLS_EN Position */ 578 #define MXC_F_GCR_MEMCTRL_SRCCLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SRCCLS_EN_POS)) /**< MEMCTRL_SRCCLS_EN Mask */ 579 580 #define MXC_F_GCR_MEMCTRL_CRYPTOLS_EN_POS 27 /**< MEMCTRL_CRYPTOLS_EN Position */ 581 #define MXC_F_GCR_MEMCTRL_CRYPTOLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_CRYPTOLS_EN_POS)) /**< MEMCTRL_CRYPTOLS_EN Mask */ 582 583 #define MXC_F_GCR_MEMCTRL_USBLS_EN_POS 28 /**< MEMCTRL_USBLS_EN Position */ 584 #define MXC_F_GCR_MEMCTRL_USBLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_USBLS_EN_POS)) /**< MEMCTRL_USBLS_EN Mask */ 585 586 #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 29 /**< MEMCTRL_ROMLS_EN Position */ 587 #define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ 588 589 /**@} end of group GCR_MEMCTRL_Register */ 590 591 /** 592 * @ingroup gcr_registers 593 * @defgroup GCR_MEMZ GCR_MEMZ 594 * @brief Memory Zeroize Control. 595 * @{ 596 */ 597 #define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ 598 #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ 599 600 #define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ 601 #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ 602 603 #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ 604 #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ 605 606 #define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ 607 #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ 608 609 #define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ 610 #define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ 611 612 #define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ 613 #define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ 614 615 #define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ 616 #define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ 617 618 #define MXC_F_GCR_MEMZ_ICC0_POS 8 /**< MEMZ_ICC0 Position */ 619 #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ 620 621 #define MXC_F_GCR_MEMZ_ICCXIP_POS 9 /**< MEMZ_ICCXIP Position */ 622 #define MXC_F_GCR_MEMZ_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICCXIP_POS)) /**< MEMZ_ICCXIP Mask */ 623 624 #define MXC_F_GCR_MEMZ_SCACHEDATA_POS 10 /**< MEMZ_SCACHEDATA Position */ 625 #define MXC_F_GCR_MEMZ_SCACHEDATA ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SCACHEDATA_POS)) /**< MEMZ_SCACHEDATA Mask */ 626 627 #define MXC_F_GCR_MEMZ_SCACHETAG_POS 11 /**< MEMZ_SCACHETAG Position */ 628 #define MXC_F_GCR_MEMZ_SCACHETAG ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SCACHETAG_POS)) /**< MEMZ_SCACHETAG Mask */ 629 630 #define MXC_F_GCR_MEMZ_CRYPTO_POS 12 /**< MEMZ_CRYPTO Position */ 631 #define MXC_F_GCR_MEMZ_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_CRYPTO_POS)) /**< MEMZ_CRYPTO Mask */ 632 633 #define MXC_F_GCR_MEMZ_USBFIFO_POS 13 /**< MEMZ_USBFIFO Position */ 634 #define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ 635 636 /**@} end of group GCR_MEMZ_Register */ 637 638 /** 639 * @ingroup gcr_registers 640 * @defgroup GCR_SCCK GCR_SCCK 641 * @brief Smart Card Clock Control. 642 * @{ 643 */ 644 #define MXC_F_GCR_SCCK_SC0CD_POS 0 /**< SCCK_SC0CD Position */ 645 #define MXC_F_GCR_SCCK_SC0CD ((uint32_t)(0x3FUL << MXC_F_GCR_SCCK_SC0CD_POS)) /**< SCCK_SC0CD Mask */ 646 647 #define MXC_F_GCR_SCCK_SC1CD_POS 8 /**< SCCK_SC1CD Position */ 648 #define MXC_F_GCR_SCCK_SC1CD ((uint32_t)(0x3FUL << MXC_F_GCR_SCCK_SC1CD_POS)) /**< SCCK_SC1CD Mask */ 649 650 /**@} end of group GCR_SCCK_Register */ 651 652 /** 653 * @ingroup gcr_registers 654 * @defgroup GCR_SYSST GCR_SYSST 655 * @brief System Status Register. 656 * @{ 657 */ 658 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 659 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 660 661 #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ 662 #define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ 663 664 #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ 665 #define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ 666 667 /**@} end of group GCR_SYSST_Register */ 668 669 /** 670 * @ingroup gcr_registers 671 * @defgroup GCR_RST1 GCR_RST1 672 * @brief Reset 1. 673 * @{ 674 */ 675 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 676 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 677 678 #define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ 679 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ 680 681 #define MXC_F_GCR_RST1_SPIXIP_POS 3 /**< RST1_SPIXIP Position */ 682 #define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) /**< RST1_SPIXIP Mask */ 683 684 #define MXC_F_GCR_RST1_XSPIM_POS 4 /**< RST1_XSPIM Position */ 685 #define MXC_F_GCR_RST1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS)) /**< RST1_XSPIM Mask */ 686 687 #define MXC_F_GCR_RST1_GPIO3_POS 5 /**< RST1_GPIO3 Position */ 688 #define MXC_F_GCR_RST1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_GPIO3_POS)) /**< RST1_GPIO3 Mask */ 689 690 #define MXC_F_GCR_RST1_SDHC_POS 6 /**< RST1_SDHC Position */ 691 #define MXC_F_GCR_RST1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS)) /**< RST1_SDHC Mask */ 692 693 #define MXC_F_GCR_RST1_OWIRE_POS 7 /**< RST1_OWIRE Position */ 694 #define MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS)) /**< RST1_OWIRE Mask */ 695 696 #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ 697 #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ 698 699 #define MXC_F_GCR_RST1_SPI3_POS 9 /**< RST1_SPI3 Position */ 700 #define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) /**< RST1_SPI3 Mask */ 701 702 #define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ 703 #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ 704 705 #define MXC_F_GCR_RST1_SPIXMEM_POS 15 /**< RST1_SPIXMEM Position */ 706 #define MXC_F_GCR_RST1_SPIXMEM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXMEM_POS)) /**< RST1_SPIXMEM Mask */ 707 708 #define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ 709 #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ 710 711 #define MXC_F_GCR_RST1_UART3_POS 18 /**< RST1_UART3 Position */ 712 #define MXC_F_GCR_RST1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART3_POS)) /**< RST1_UART3 Mask */ 713 714 #define MXC_F_GCR_RST1_UART4_POS 19 /**< RST1_UART4 Position */ 715 #define MXC_F_GCR_RST1_UART4 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART4_POS)) /**< RST1_UART4 Mask */ 716 717 #define MXC_F_GCR_RST1_UART5_POS 20 /**< RST1_UART5 Position */ 718 #define MXC_F_GCR_RST1_UART5 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART5_POS)) /**< RST1_UART5 Mask */ 719 720 #define MXC_F_GCR_RST1_KBD_POS 21 /**< RST1_KBD Position */ 721 #define MXC_F_GCR_RST1_KBD ((uint32_t)(0x1UL << MXC_F_GCR_RST1_KBD_POS)) /**< RST1_KBD Mask */ 722 723 #define MXC_F_GCR_RST1_ADC9_POS 22 /**< RST1_ADC9 Position */ 724 #define MXC_F_GCR_RST1_ADC9 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_ADC9_POS)) /**< RST1_ADC9 Mask */ 725 726 #define MXC_F_GCR_RST1_SC0_POS 23 /**< RST1_SC0 Position */ 727 #define MXC_F_GCR_RST1_SC0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SC0_POS)) /**< RST1_SC0 Mask */ 728 729 #define MXC_F_GCR_RST1_SC1_POS 24 /**< RST1_SC1 Position */ 730 #define MXC_F_GCR_RST1_SC1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SC1_POS)) /**< RST1_SC1 Mask */ 731 732 #define MXC_F_GCR_RST1_NFC_POS 25 /**< RST1_NFC Position */ 733 #define MXC_F_GCR_RST1_NFC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_NFC_POS)) /**< RST1_NFC Mask */ 734 735 #define MXC_F_GCR_RST1_EMAC_POS 26 /**< RST1_EMAC Position */ 736 #define MXC_F_GCR_RST1_EMAC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_EMAC_POS)) /**< RST1_EMAC Mask */ 737 738 #define MXC_F_GCR_RST1_PCIF_POS 27 /**< RST1_PCIF Position */ 739 #define MXC_F_GCR_RST1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PCIF_POS)) /**< RST1_PCIF Mask */ 740 741 #define MXC_F_GCR_RST1_HTMR0_POS 28 /**< RST1_HTMR0 Position */ 742 #define MXC_F_GCR_RST1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR0_POS)) /**< RST1_HTMR0 Mask */ 743 744 #define MXC_F_GCR_RST1_HTMR1_POS 29 /**< RST1_HTMR1 Position */ 745 #define MXC_F_GCR_RST1_HTMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_HTMR1_POS)) /**< RST1_HTMR1 Mask */ 746 747 /**@} end of group GCR_RST1_Register */ 748 749 /** 750 * @ingroup gcr_registers 751 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 752 * @brief Peripheral Clock Disable. 753 * @{ 754 */ 755 #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ 756 #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ 757 758 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 759 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 760 761 #define MXC_F_GCR_PCLKDIS1_WDT0_POS 4 /**< PCLKDIS1_WDT0 Position */ 762 #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ 763 764 #define MXC_F_GCR_PCLKDIS1_WDT1_POS 5 /**< PCLKDIS1_WDT1 Position */ 765 #define MXC_F_GCR_PCLKDIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT1_POS)) /**< PCLKDIS1_WDT1 Mask */ 766 767 #define MXC_F_GCR_PCLKDIS1_GPIO3_POS 6 /**< PCLKDIS1_GPIO3 Position */ 768 #define MXC_F_GCR_PCLKDIS1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_GPIO3_POS)) /**< PCLKDIS1_GPIO3 Mask */ 769 770 #define MXC_F_GCR_PCLKDIS1_SCACHE_POS 7 /**< PCLKDIS1_SCACHE Position */ 771 #define MXC_F_GCR_PCLKDIS1_SCACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SCACHE_POS)) /**< PCLKDIS1_SCACHE Mask */ 772 773 #define MXC_F_GCR_PCLKDIS1_HA0_POS 8 /**< PCLKDIS1_HA0 Position */ 774 #define MXC_F_GCR_PCLKDIS1_HA0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_HA0_POS)) /**< PCLKDIS1_HA0 Mask */ 775 776 #define MXC_F_GCR_PCLKDIS1_SDHC_POS 10 /**< PCLKDIS1_SDHC Position */ 777 #define MXC_F_GCR_PCLKDIS1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SDHC_POS)) /**< PCLKDIS1_SDHC Mask */ 778 779 #define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */ 780 #define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */ 781 782 #define MXC_F_GCR_PCLKDIS1_ICCXIP_POS 12 /**< PCLKDIS1_ICCXIP Position */ 783 #define MXC_F_GCR_PCLKDIS1_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICCXIP_POS)) /**< PCLKDIS1_ICCXIP Mask */ 784 785 #define MXC_F_GCR_PCLKDIS1_OWIRE_POS 13 /**< PCLKDIS1_OWIRE Position */ 786 #define MXC_F_GCR_PCLKDIS1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWIRE_POS)) /**< PCLKDIS1_OWIRE Mask */ 787 788 #define MXC_F_GCR_PCLKDIS1_SPI3_POS 14 /**< PCLKDIS1_SPI3 Position */ 789 #define MXC_F_GCR_PCLKDIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI3_POS)) /**< PCLKDIS1_SPI3 Mask */ 790 791 #define MXC_F_GCR_PCLKDIS1_SPIXIP_POS 20 /**< PCLKDIS1_SPIXIP Position */ 792 #define MXC_F_GCR_PCLKDIS1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPIXIP_POS)) /**< PCLKDIS1_SPIXIP Mask */ 793 794 #define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ 795 #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ 796 797 #define MXC_F_GCR_PCLKDIS1_UART3_POS 22 /**< PCLKDIS1_UART3 Position */ 798 #define MXC_F_GCR_PCLKDIS1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART3_POS)) /**< PCLKDIS1_UART3 Mask */ 799 800 #define MXC_F_GCR_PCLKDIS1_UART4_POS 23 /**< PCLKDIS1_UART4 Position */ 801 #define MXC_F_GCR_PCLKDIS1_UART4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART4_POS)) /**< PCLKDIS1_UART4 Mask */ 802 803 #define MXC_F_GCR_PCLKDIS1_UART5_POS 24 /**< PCLKDIS1_UART5 Position */ 804 #define MXC_F_GCR_PCLKDIS1_UART5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART5_POS)) /**< PCLKDIS1_UART5 Mask */ 805 806 #define MXC_F_GCR_PCLKDIS1_ADC9_POS 25 /**< PCLKDIS1_ADC9 Position */ 807 #define MXC_F_GCR_PCLKDIS1_ADC9 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ADC9_POS)) /**< PCLKDIS1_ADC9 Mask */ 808 809 #define MXC_F_GCR_PCLKDIS1_SC0_POS 26 /**< PCLKDIS1_SC0 Position */ 810 #define MXC_F_GCR_PCLKDIS1_SC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SC0_POS)) /**< PCLKDIS1_SC0 Mask */ 811 812 #define MXC_F_GCR_PCLKDIS1_SC1_POS 27 /**< PCLKDIS1_SC1 Position */ 813 #define MXC_F_GCR_PCLKDIS1_SC1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SC1_POS)) /**< PCLKDIS1_SC1 Mask */ 814 815 #define MXC_F_GCR_PCLKDIS1_NFC_POS 28 /**< PCLKDIS1_NFC Position */ 816 #define MXC_F_GCR_PCLKDIS1_NFC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_NFC_POS)) /**< PCLKDIS1_NFC Mask */ 817 818 #define MXC_F_GCR_PCLKDIS1_EMAC_POS 29 /**< PCLKDIS1_EMAC Position */ 819 #define MXC_F_GCR_PCLKDIS1_EMAC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_EMAC_POS)) /**< PCLKDIS1_EMAC Mask */ 820 821 #define MXC_F_GCR_PCLKDIS1_HA1_POS 30 /**< PCLKDIS1_HA1 Position */ 822 #define MXC_F_GCR_PCLKDIS1_HA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_HA1_POS)) /**< PCLKDIS1_HA1 Mask */ 823 824 #define MXC_F_GCR_PCLKDIS1_PCIF_POS 31 /**< PCLKDIS1_PCIF Position */ 825 #define MXC_F_GCR_PCLKDIS1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS)) /**< PCLKDIS1_PCIF Mask */ 826 827 /**@} end of group GCR_PCLKDIS1_Register */ 828 829 /** 830 * @ingroup gcr_registers 831 * @defgroup GCR_EVENTEN GCR_EVENTEN 832 * @brief Event Enable Register. 833 * @{ 834 */ 835 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 836 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 837 838 #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ 839 #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ 840 841 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 842 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 843 844 /**@} end of group GCR_EVENTEN_Register */ 845 846 /** 847 * @ingroup gcr_registers 848 * @defgroup GCR_REVISION GCR_REVISION 849 * @brief Revision Register. 850 * @{ 851 */ 852 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 853 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 854 855 /**@} end of group GCR_REVISION_Register */ 856 857 /** 858 * @ingroup gcr_registers 859 * @defgroup GCR_SYSIE GCR_SYSIE 860 * @brief System Status Interrupt Enable Register. 861 * @{ 862 */ 863 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 864 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 865 866 #define MXC_F_GCR_SYSIE_CIE_POS 1 /**< SYSIE_CIE Position */ 867 #define MXC_F_GCR_SYSIE_CIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_CIE_POS)) /**< SYSIE_CIE Mask */ 868 869 #define MXC_F_GCR_SYSIE_SCMF_POS 5 /**< SYSIE_SCMF Position */ 870 #define MXC_F_GCR_SYSIE_SCMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_SCMF_POS)) /**< SYSIE_SCMF Mask */ 871 872 /**@} end of group GCR_SYSIE_Register */ 873 874 /** 875 * @ingroup gcr_registers 876 * @defgroup GCR_IPOCNT GCR_IPOCNT 877 * @brief IPO Warmup Count Register. 878 * @{ 879 */ 880 #define MXC_F_GCR_IPOCNT_WMUPCNT_POS 0 /**< IPOCNT_WMUPCNT Position */ 881 #define MXC_F_GCR_IPOCNT_WMUPCNT ((uint32_t)(0x3FFUL << MXC_F_GCR_IPOCNT_WMUPCNT_POS)) /**< IPOCNT_WMUPCNT Mask */ 882 883 /**@} end of group GCR_IPOCNT_Register */ 884 885 /** 886 * @ingroup gcr_registers 887 * @defgroup GCR_ECCERR GCR_ECCERR 888 * @brief ECC Error Register 889 * @{ 890 */ 891 #define MXC_F_GCR_ECCERR_RAM0_POS 0 /**< ECCERR_RAM0 Position */ 892 #define MXC_F_GCR_ECCERR_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM0_POS)) /**< ECCERR_RAM0 Mask */ 893 894 #define MXC_F_GCR_ECCERR_RAM1_POS 1 /**< ECCERR_RAM1 Position */ 895 #define MXC_F_GCR_ECCERR_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM1_POS)) /**< ECCERR_RAM1 Mask */ 896 897 #define MXC_F_GCR_ECCERR_RAM2_POS 2 /**< ECCERR_RAM2 Position */ 898 #define MXC_F_GCR_ECCERR_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM2_POS)) /**< ECCERR_RAM2 Mask */ 899 900 #define MXC_F_GCR_ECCERR_RAM3_POS 3 /**< ECCERR_RAM3 Position */ 901 #define MXC_F_GCR_ECCERR_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM3_POS)) /**< ECCERR_RAM3 Mask */ 902 903 #define MXC_F_GCR_ECCERR_RAM4_POS 4 /**< ECCERR_RAM4 Position */ 904 #define MXC_F_GCR_ECCERR_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM4_POS)) /**< ECCERR_RAM4 Mask */ 905 906 #define MXC_F_GCR_ECCERR_RAM5_POS 5 /**< ECCERR_RAM5 Position */ 907 #define MXC_F_GCR_ECCERR_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM5_POS)) /**< ECCERR_RAM5 Mask */ 908 909 #define MXC_F_GCR_ECCERR_ICC0_POS 8 /**< ECCERR_ICC0 Position */ 910 #define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */ 911 912 #define MXC_F_GCR_ECCERR_ICSPIXF_POS 10 /**< ECCERR_ICSPIXF Position */ 913 #define MXC_F_GCR_ECCERR_ICSPIXF ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICSPIXF_POS)) /**< ECCERR_ICSPIXF Mask */ 914 915 #define MXC_F_GCR_ECCERR_FLASH0_POS 11 /**< ECCERR_FLASH0 Position */ 916 #define MXC_F_GCR_ECCERR_FLASH0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH0_POS)) /**< ECCERR_FLASH0 Mask */ 917 918 #define MXC_F_GCR_ECCERR_FLASH1_POS 12 /**< ECCERR_FLASH1 Position */ 919 #define MXC_F_GCR_ECCERR_FLASH1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH1_POS)) /**< ECCERR_FLASH1 Mask */ 920 921 /**@} end of group GCR_ECCERR_Register */ 922 923 /** 924 * @ingroup gcr_registers 925 * @defgroup GCR_ECCCED GCR_ECCCED 926 * @brief ECC Not Double Error Detect Register 927 * @{ 928 */ 929 #define MXC_F_GCR_ECCCED_RAM0_POS 0 /**< ECCCED_RAM0 Position */ 930 #define MXC_F_GCR_ECCCED_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM0_POS)) /**< ECCCED_RAM0 Mask */ 931 932 #define MXC_F_GCR_ECCCED_RAM1_POS 1 /**< ECCCED_RAM1 Position */ 933 #define MXC_F_GCR_ECCCED_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM1_POS)) /**< ECCCED_RAM1 Mask */ 934 935 #define MXC_F_GCR_ECCCED_RAM2_POS 2 /**< ECCCED_RAM2 Position */ 936 #define MXC_F_GCR_ECCCED_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM2_POS)) /**< ECCCED_RAM2 Mask */ 937 938 #define MXC_F_GCR_ECCCED_RAM3_POS 3 /**< ECCCED_RAM3 Position */ 939 #define MXC_F_GCR_ECCCED_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM3_POS)) /**< ECCCED_RAM3 Mask */ 940 941 #define MXC_F_GCR_ECCCED_RAM4_POS 4 /**< ECCCED_RAM4 Position */ 942 #define MXC_F_GCR_ECCCED_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM4_POS)) /**< ECCCED_RAM4 Mask */ 943 944 #define MXC_F_GCR_ECCCED_RAM5_POS 5 /**< ECCCED_RAM5 Position */ 945 #define MXC_F_GCR_ECCCED_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM5_POS)) /**< ECCCED_RAM5 Mask */ 946 947 #define MXC_F_GCR_ECCCED_ICC0_POS 8 /**< ECCCED_ICC0 Position */ 948 #define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */ 949 950 #define MXC_F_GCR_ECCCED_ICSPIXF_POS 10 /**< ECCCED_ICSPIXF Position */ 951 #define MXC_F_GCR_ECCCED_ICSPIXF ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICSPIXF_POS)) /**< ECCCED_ICSPIXF Mask */ 952 953 #define MXC_F_GCR_ECCCED_FLASH0_POS 11 /**< ECCCED_FLASH0 Position */ 954 #define MXC_F_GCR_ECCCED_FLASH0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH0_POS)) /**< ECCCED_FLASH0 Mask */ 955 956 #define MXC_F_GCR_ECCCED_FLASH1_POS 12 /**< ECCCED_FLASH1 Position */ 957 #define MXC_F_GCR_ECCCED_FLASH1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH1_POS)) /**< ECCCED_FLASH1 Mask */ 958 959 /**@} end of group GCR_ECCCED_Register */ 960 961 /** 962 * @ingroup gcr_registers 963 * @defgroup GCR_ECCIE GCR_ECCIE 964 * @brief ECC IRQ Enable Register 965 * @{ 966 */ 967 #define MXC_F_GCR_ECCIE_RAM0_POS 0 /**< ECCIE_RAM0 Position */ 968 #define MXC_F_GCR_ECCIE_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM0_POS)) /**< ECCIE_RAM0 Mask */ 969 970 #define MXC_F_GCR_ECCIE_RAM1_POS 1 /**< ECCIE_RAM1 Position */ 971 #define MXC_F_GCR_ECCIE_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM1_POS)) /**< ECCIE_RAM1 Mask */ 972 973 #define MXC_F_GCR_ECCIE_RAM2_POS 2 /**< ECCIE_RAM2 Position */ 974 #define MXC_F_GCR_ECCIE_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM2_POS)) /**< ECCIE_RAM2 Mask */ 975 976 #define MXC_F_GCR_ECCIE_RAM3_POS 3 /**< ECCIE_RAM3 Position */ 977 #define MXC_F_GCR_ECCIE_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM3_POS)) /**< ECCIE_RAM3 Mask */ 978 979 #define MXC_F_GCR_ECCIE_RAM4_POS 4 /**< ECCIE_RAM4 Position */ 980 #define MXC_F_GCR_ECCIE_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM4_POS)) /**< ECCIE_RAM4 Mask */ 981 982 #define MXC_F_GCR_ECCIE_RAM5_POS 5 /**< ECCIE_RAM5 Position */ 983 #define MXC_F_GCR_ECCIE_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM5_POS)) /**< ECCIE_RAM5 Mask */ 984 985 #define MXC_F_GCR_ECCIE_ICC0_POS 8 /**< ECCIE_ICC0 Position */ 986 #define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */ 987 988 #define MXC_F_GCR_ECCIE_ICSPIXF_POS 10 /**< ECCIE_ICSPIXF Position */ 989 #define MXC_F_GCR_ECCIE_ICSPIXF ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICSPIXF_POS)) /**< ECCIE_ICSPIXF Mask */ 990 991 #define MXC_F_GCR_ECCIE_FLASH0_POS 11 /**< ECCIE_FLASH0 Position */ 992 #define MXC_F_GCR_ECCIE_FLASH0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH0_POS)) /**< ECCIE_FLASH0 Mask */ 993 994 #define MXC_F_GCR_ECCIE_FLASH1_POS 12 /**< ECCIE_FLASH1 Position */ 995 #define MXC_F_GCR_ECCIE_FLASH1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH1_POS)) /**< ECCIE_FLASH1 Mask */ 996 997 /**@} end of group GCR_ECCIE_Register */ 998 999 /** 1000 * @ingroup gcr_registers 1001 * @defgroup GCR_ECCADDR GCR_ECCADDR 1002 * @brief ECC Error Address Register 1003 * @{ 1004 */ 1005 #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ 1006 #define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ 1007 1008 #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ 1009 #define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ 1010 1011 #define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ 1012 #define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ 1013 1014 #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ 1015 #define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ 1016 1017 #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ 1018 #define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ 1019 1020 #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ 1021 #define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ 1022 1023 /**@} end of group GCR_ECCADDR_Register */ 1024 1025 /** 1026 * @ingroup gcr_registers 1027 * @defgroup GCR_NFC_LDOCR GCR_NFC_LDOCR 1028 * @brief NFC LDO Control Register 1029 * @{ 1030 */ 1031 #define MXC_F_GCR_NFC_LDOCR_EN_POS 4 /**< NFC_LDOCR_EN Position */ 1032 #define MXC_F_GCR_NFC_LDOCR_EN ((uint32_t)(0x1UL << MXC_F_GCR_NFC_LDOCR_EN_POS)) /**< NFC_LDOCR_EN Mask */ 1033 1034 #define MXC_F_GCR_NFC_LDOCR_PULLD_POS 5 /**< NFC_LDOCR_PULLD Position */ 1035 #define MXC_F_GCR_NFC_LDOCR_PULLD ((uint32_t)(0x1UL << MXC_F_GCR_NFC_LDOCR_PULLD_POS)) /**< NFC_LDOCR_PULLD Mask */ 1036 1037 #define MXC_F_GCR_NFC_LDOCR_VSEL_POS 6 /**< NFC_LDOCR_VSEL Position */ 1038 #define MXC_F_GCR_NFC_LDOCR_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_NFC_LDOCR_VSEL_POS)) /**< NFC_LDOCR_VSEL Mask */ 1039 1040 #define MXC_F_GCR_NFC_LDOCR_BYPEN_POS 8 /**< NFC_LDOCR_BYPEN Position */ 1041 #define MXC_F_GCR_NFC_LDOCR_BYPEN ((uint32_t)(0x1UL << MXC_F_GCR_NFC_LDOCR_BYPEN_POS)) /**< NFC_LDOCR_BYPEN Mask */ 1042 1043 #define MXC_F_GCR_NFC_LDOCR_DISCH_POS 9 /**< NFC_LDOCR_DISCH Position */ 1044 #define MXC_F_GCR_NFC_LDOCR_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_NFC_LDOCR_DISCH_POS)) /**< NFC_LDOCR_DISCH Mask */ 1045 1046 #define MXC_F_GCR_NFC_LDOCR_EN_DLY_POS 15 /**< NFC_LDOCR_EN_DLY Position */ 1047 #define MXC_F_GCR_NFC_LDOCR_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_NFC_LDOCR_EN_DLY_POS)) /**< NFC_LDOCR_EN_DLY Mask */ 1048 1049 #define MXC_F_GCR_NFC_LDOCR_BYP_EN_DLY_POS 14 /**< NFC_LDOCR_BYP_EN_DLY Position */ 1050 #define MXC_F_GCR_NFC_LDOCR_BYP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_NFC_LDOCR_BYP_EN_DLY_POS)) /**< NFC_LDOCR_BYP_EN_DLY Mask */ 1051 1052 /**@} end of group GCR_NFC_LDOCR_Register */ 1053 1054 /** 1055 * @ingroup gcr_registers 1056 * @defgroup GCR_NFCLDO_DLY GCR_NFCLDO_DLY 1057 * @brief NFC LDO Delay Register 1058 * @{ 1059 */ 1060 #define MXC_F_GCR_NFCLDO_DLY_BYPCNT_POS 0 /**< NFCLDO_DLY_BYPCNT Position */ 1061 #define MXC_F_GCR_NFCLDO_DLY_BYPCNT ((uint32_t)(0xFFUL << MXC_F_GCR_NFCLDO_DLY_BYPCNT_POS)) /**< NFCLDO_DLY_BYPCNT Mask */ 1062 1063 #define MXC_F_GCR_NFCLDO_DLY_ENCNT_POS 8 /**< NFCLDO_DLY_ENCNT Position */ 1064 #define MXC_F_GCR_NFCLDO_DLY_ENCNT ((uint32_t)(0xFFUL << MXC_F_GCR_NFCLDO_DLY_ENCNT_POS)) /**< NFCLDO_DLY_ENCNT Mask */ 1065 1066 /**@} end of group GCR_NFCLDO_DLY_Register */ 1067 1068 #ifdef __cplusplus 1069 } 1070 #endif 1071 1072 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_GCR_REGS_H_ 1073
