1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_FLC_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_FLC_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup flc 66 * @defgroup flc_registers FLC_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 68 * @details Flash Memory Control. 69 */ 70 71 /** 72 * @ingroup flc_registers 73 * Structure type to access the FLC Registers. 74 */ 75 typedef struct { 76 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */ 77 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */ 78 __IO uint32_t cn; /**< <tt>\b 0x08:</tt> FLC CN Register */ 79 __R uint32_t rsv_0xc_0x23[6]; 80 __IO uint32_t intr; /**< <tt>\b 0x24:</tt> FLC INTR Register */ 81 __IO uint32_t ecc_data; /**< <tt>\b 0x28:</tt> FLC ECC_DATA Register */ 82 __R uint32_t rsv_0x2c; 83 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */ 84 } mxc_flc_regs_t; 85 86 /* Register offsets for module FLC */ 87 /** 88 * @ingroup flc_registers 89 * @defgroup FLC_Register_Offsets Register Offsets 90 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 97 #define MXC_R_FLC_ECC_DATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */ 98 #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 99 /**@} end of group flc_registers */ 100 101 /** 102 * @ingroup flc_registers 103 * @defgroup FLC_ADDR FLC_ADDR 104 * @brief Flash Write Address. 105 * @{ 106 */ 107 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 108 #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 109 110 /**@} end of group FLC_ADDR_Register */ 111 112 /** 113 * @ingroup flc_registers 114 * @defgroup FLC_CLKDIV FLC_CLKDIV 115 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 116 * MHz clock for Flash controller. 117 * @{ 118 */ 119 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 120 #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 121 122 /**@} end of group FLC_CLKDIV_Register */ 123 124 /** 125 * @ingroup flc_registers 126 * @defgroup FLC_CN FLC_CN 127 * @brief Flash Control Register. 128 * @{ 129 */ 130 #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ 131 #define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ 132 133 #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ 134 #define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ 135 136 #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ 137 #define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ 138 139 #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ 140 #define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ 141 #define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ 142 #define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ 143 #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ 144 #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */ 145 #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ 146 #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */ 147 148 #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ 149 #define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ 150 151 #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ 152 #define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ 153 #define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ 154 #define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ 155 #define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */ 156 #define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */ 157 158 /**@} end of group FLC_CN_Register */ 159 160 /** 161 * @ingroup flc_registers 162 * @defgroup FLC_INTR FLC_INTR 163 * @brief Flash Interrupt Register. 164 * @{ 165 */ 166 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ 167 #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ 168 169 #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ 170 #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ 171 172 #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ 173 #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ 174 175 #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ 176 #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ 177 178 /**@} end of group FLC_INTR_Register */ 179 180 /** 181 * @ingroup flc_registers 182 * @defgroup FLC_ECC_DATA FLC_ECC_DATA 183 * @brief ECC Data Register. 184 * @{ 185 */ 186 #define MXC_F_FLC_ECC_DATA_ECC_EVEN_POS 0 /**< ECC_DATA_ECC_EVEN Position */ 187 #define MXC_F_FLC_ECC_DATA_ECC_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECC_DATA_ECC_EVEN_POS)) /**< ECC_DATA_ECC_EVEN Mask */ 188 189 #define MXC_F_FLC_ECC_DATA_ECC_ODD_POS 16 /**< ECC_DATA_ECC_ODD Position */ 190 #define MXC_F_FLC_ECC_DATA_ECC_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECC_DATA_ECC_ODD_POS)) /**< ECC_DATA_ECC_ODD Mask */ 191 192 /**@} end of group FLC_ECC_DATA_Register */ 193 194 /** 195 * @ingroup flc_registers 196 * @defgroup FLC_DATA FLC_DATA 197 * @brief Flash Write Data. 198 * @{ 199 */ 200 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 201 #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 202 203 /**@} end of group FLC_DATA_Register */ 204 205 #ifdef __cplusplus 206 } 207 #endif 208 209 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_FLC_REGS_H_ 210
