1 /**
2  * @file    fcr_regs.h
3  * @brief   Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
4  * @note    This file is @generated.
5  */
6 
7 /******************************************************************************
8  *
9  * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
10  * Analog Devices, Inc.),
11  * Copyright (C) 2023-2024 Analog Devices, Inc.
12  *
13  * Licensed under the Apache License, Version 2.0 (the "License");
14  * you may not use this file except in compliance with the License.
15  * You may obtain a copy of the License at
16  *
17  *     http://www.apache.org/licenses/LICENSE-2.0
18  *
19  * Unless required by applicable law or agreed to in writing, software
20  * distributed under the License is distributed on an "AS IS" BASIS,
21  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22  * See the License for the specific language governing permissions and
23  * limitations under the License.
24  *
25  ******************************************************************************/
26 
27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_FCR_REGS_H_
28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_FCR_REGS_H_
29 
30 /* **** Includes **** */
31 #include <stdint.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 #if defined (__ICCARM__)
38   #pragma system_include
39 #endif
40 
41 #if defined (__CC_ARM)
42   #pragma anon_unions
43 #endif
44 /// @cond
45 /*
46     If types are not defined elsewhere (CMSIS) define them here
47 */
48 #ifndef __IO
49 #define __IO volatile
50 #endif
51 #ifndef __I
52 #define __I  volatile const
53 #endif
54 #ifndef __O
55 #define __O  volatile
56 #endif
57 #ifndef __R
58 #define __R  volatile const
59 #endif
60 /// @endcond
61 
62 /* **** Definitions **** */
63 
64 /**
65  * @ingroup     fcr
66  * @defgroup    fcr_registers FCR_Registers
67  * @brief       Registers, Bit Masks and Bit Positions for the FCR Peripheral Module.
68  * @details     Function Control Register.
69  */
70 
71 /**
72  * @ingroup fcr_registers
73  * Structure type to access the FCR Registers.
74  */
75 typedef struct {
76     __IO uint32_t fctrl0;               /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */
77     __IO uint32_t autocal0;             /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */
78     __IO uint32_t autocal1;             /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */
79     __IO uint32_t autocal2;             /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */
80 } mxc_fcr_regs_t;
81 
82 /* Register offsets for module FCR */
83 /**
84  * @ingroup    fcr_registers
85  * @defgroup   FCR_Register_Offsets Register Offsets
86  * @brief      FCR Peripheral Register Offsets from the FCR Base Peripheral Address.
87  * @{
88  */
89 #define MXC_R_FCR_FCTRL0                   ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
90 #define MXC_R_FCR_AUTOCAL0                 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */
91 #define MXC_R_FCR_AUTOCAL1                 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */
92 #define MXC_R_FCR_AUTOCAL2                 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */
93 /**@} end of group fcr_registers */
94 
95 /**
96  * @ingroup  fcr_registers
97  * @defgroup FCR_FCTRL0 FCR_FCTRL0
98  * @brief    Register 0.
99  * @{
100  */
101 #define MXC_F_FCR_FCTRL0_USB_EXTCLK_SEL_POS            16 /**< FCTRL0_USB_EXTCLK_SEL Position */
102 #define MXC_F_FCR_FCTRL0_USB_EXTCLK_SEL                ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_USB_EXTCLK_SEL_POS)) /**< FCTRL0_USB_EXTCLK_SEL Mask */
103 
104 #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS        20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */
105 #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */
106 
107 #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS        21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */
108 #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */
109 
110 #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS        22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */
111 #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */
112 
113 #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS        23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */
114 #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN            ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */
115 
116 #define MXC_F_FCR_FCTRL0_I2C2AF2_SDA_FILTER_EN_POS     24 /**< FCTRL0_I2C2AF2_SDA_FILTER_EN Position */
117 #define MXC_F_FCR_FCTRL0_I2C2AF2_SDA_FILTER_EN         ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2AF2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2AF2_SDA_FILTER_EN Mask */
118 
119 #define MXC_F_FCR_FCTRL0_I2C2AF2_SCL_FILTER_EN_POS     25 /**< FCTRL0_I2C2AF2_SCL_FILTER_EN Position */
120 #define MXC_F_FCR_FCTRL0_I2C2AF2_SCL_FILTER_EN         ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2AF2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2AF2_SCL_FILTER_EN Mask */
121 
122 #define MXC_F_FCR_FCTRL0_I2C2AF3_SDA_FILTER_EN_POS     26 /**< FCTRL0_I2C2AF3_SDA_FILTER_EN Position */
123 #define MXC_F_FCR_FCTRL0_I2C2AF3_SDA_FILTER_EN         ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2AF3_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2AF3_SDA_FILTER_EN Mask */
124 
125 #define MXC_F_FCR_FCTRL0_I2C2AF3_SCL_FILTER_EN_POS     27 /**< FCTRL0_I2C2AF3_SCL_FILTER_EN Position */
126 #define MXC_F_FCR_FCTRL0_I2C2AF3_SCL_FILTER_EN         ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2AF3_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2AF3_SCL_FILTER_EN Mask */
127 
128 #define MXC_F_FCR_FCTRL0_I2C2AF4_SDA_FILTER_EN_POS     28 /**< FCTRL0_I2C2AF4_SDA_FILTER_EN Position */
129 #define MXC_F_FCR_FCTRL0_I2C2AF4_SDA_FILTER_EN         ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2AF4_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2AF4_SDA_FILTER_EN Mask */
130 
131 #define MXC_F_FCR_FCTRL0_I2C2AF4_SCL_FILTER_EN_POS     29 /**< FCTRL0_I2C2AF4_SCL_FILTER_EN Position */
132 #define MXC_F_FCR_FCTRL0_I2C2AF4_SCL_FILTER_EN         ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2AF4_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2AF4_SCL_FILTER_EN Mask */
133 
134 /**@} end of group FCR_FCTRL0_Register */
135 
136 /**
137  * @ingroup  fcr_registers
138  * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0
139  * @brief    Register 1.
140  * @{
141  */
142 #define MXC_F_FCR_AUTOCAL0_SEL_POS                     0 /**< AUTOCAL0_SEL Position */
143 #define MXC_F_FCR_AUTOCAL0_SEL                         ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */
144 
145 #define MXC_F_FCR_AUTOCAL0_EN_POS                      1 /**< AUTOCAL0_EN Position */
146 #define MXC_F_FCR_AUTOCAL0_EN                          ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */
147 
148 #define MXC_F_FCR_AUTOCAL0_LOAD_POS                    2 /**< AUTOCAL0_LOAD Position */
149 #define MXC_F_FCR_AUTOCAL0_LOAD                        ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */
150 
151 #define MXC_F_FCR_AUTOCAL0_INVERT_POS                  3 /**< AUTOCAL0_INVERT Position */
152 #define MXC_F_FCR_AUTOCAL0_INVERT                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */
153 
154 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS                  4 /**< AUTOCAL0_ATOMIC Position */
155 #define MXC_F_FCR_AUTOCAL0_ATOMIC                      ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */
156 
157 #define MXC_F_FCR_AUTOCAL0_GAIN_POS                    8 /**< AUTOCAL0_GAIN Position */
158 #define MXC_F_FCR_AUTOCAL0_GAIN                        ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */
159 
160 #define MXC_F_FCR_AUTOCAL0_TRIM_POS                    23 /**< AUTOCAL0_TRIM Position */
161 #define MXC_F_FCR_AUTOCAL0_TRIM                        ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */
162 
163 /**@} end of group FCR_AUTOCAL0_Register */
164 
165 /**
166  * @ingroup  fcr_registers
167  * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1
168  * @brief    Register 2.
169  * @{
170  */
171 #define MXC_F_FCR_AUTOCAL1_NFC_FWD_EN_POS              0 /**< AUTOCAL1_NFC_FWD_EN Position */
172 #define MXC_F_FCR_AUTOCAL1_NFC_FWD_EN                  ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_NFC_FWD_EN_POS)) /**< AUTOCAL1_NFC_FWD_EN Mask */
173 
174 #define MXC_F_FCR_AUTOCAL1_NFC_CLK_EN_POS              1 /**< AUTOCAL1_NFC_CLK_EN Position */
175 #define MXC_F_FCR_AUTOCAL1_NFC_CLK_EN                  ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_NFC_CLK_EN_POS)) /**< AUTOCAL1_NFC_CLK_EN Mask */
176 
177 #define MXC_F_FCR_AUTOCAL1_NFC_FWD_TX_DATA_OVR_POS     2 /**< AUTOCAL1_NFC_FWD_TX_DATA_OVR Position */
178 #define MXC_F_FCR_AUTOCAL1_NFC_FWD_TX_DATA_OVR         ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_NFC_FWD_TX_DATA_OVR_POS)) /**< AUTOCAL1_NFC_FWD_TX_DATA_OVR Mask */
179 
180 #define MXC_F_FCR_AUTOCAL1_XO_EN_DGL_POS               3 /**< AUTOCAL1_XO_EN_DGL Position */
181 #define MXC_F_FCR_AUTOCAL1_XO_EN_DGL                   ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_XO_EN_DGL_POS)) /**< AUTOCAL1_XO_EN_DGL Mask */
182 
183 #define MXC_F_FCR_AUTOCAL1_RX_BIAS_PD_POS              4 /**< AUTOCAL1_RX_BIAS_PD Position */
184 #define MXC_F_FCR_AUTOCAL1_RX_BIAS_PD                  ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_RX_BIAS_PD_POS)) /**< AUTOCAL1_RX_BIAS_PD Mask */
185 
186 #define MXC_F_FCR_AUTOCAL1_RX_BIAS_EN_POS              5 /**< AUTOCAL1_RX_BIAS_EN Position */
187 #define MXC_F_FCR_AUTOCAL1_RX_BIAS_EN                  ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_RX_BIAS_EN_POS)) /**< AUTOCAL1_RX_BIAS_EN Mask */
188 
189 #define MXC_F_FCR_AUTOCAL1_RX_TM_VBG_VABUS_POS         6 /**< AUTOCAL1_RX_TM_VBG_VABUS Position */
190 #define MXC_F_FCR_AUTOCAL1_RX_TM_VBG_VABUS             ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_RX_TM_VBG_VABUS_POS)) /**< AUTOCAL1_RX_TM_VBG_VABUS Mask */
191 
192 #define MXC_F_FCR_AUTOCAL1_RX_TM_BIAS_POS              7 /**< AUTOCAL1_RX_TM_BIAS Position */
193 #define MXC_F_FCR_AUTOCAL1_RX_TM_BIAS                  ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_RX_TM_BIAS_POS)) /**< AUTOCAL1_RX_TM_BIAS Mask */
194 
195 #define MXC_F_FCR_AUTOCAL1_NFC_FWD_DOUT_POS            8 /**< AUTOCAL1_NFC_FWD_DOUT Position */
196 #define MXC_F_FCR_AUTOCAL1_NFC_FWD_DOUT                ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL1_NFC_FWD_DOUT_POS)) /**< AUTOCAL1_NFC_FWD_DOUT Mask */
197 
198 /**@} end of group FCR_AUTOCAL1_Register */
199 
200 /**
201  * @ingroup  fcr_registers
202  * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2
203  * @brief    Register 3.
204  * @{
205  */
206 #define MXC_F_FCR_AUTOCAL2_RUNTIME_POS                 0 /**< AUTOCAL2_RUNTIME Position */
207 #define MXC_F_FCR_AUTOCAL2_RUNTIME                     ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */
208 
209 /**@} end of group FCR_AUTOCAL2_Register */
210 
211 #ifdef __cplusplus
212 }
213 #endif
214 
215 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_FCR_REGS_H_
216