1 /** 2 * @file clcd_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CLCD Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_CLCD_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_CLCD_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup clcd 66 * @defgroup clcd_registers CLCD_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the CLCD Peripheral Module. 68 * @details Color LCD Controller 69 */ 70 71 /** 72 * @ingroup clcd_registers 73 * Structure type to access the CLCD Registers. 74 */ 75 typedef struct { 76 __IO uint32_t clk; /**< <tt>\b 0x000:</tt> CLCD CLK Register */ 77 __IO uint32_t vtim_0; /**< <tt>\b 0x004:</tt> CLCD VTIM_0 Register */ 78 __IO uint32_t vtim_1; /**< <tt>\b 0x008:</tt> CLCD VTIM_1 Register */ 79 __IO uint32_t htim; /**< <tt>\b 0x00C:</tt> CLCD HTIM Register */ 80 __IO uint32_t ctrl; /**< <tt>\b 0x010:</tt> CLCD CTRL Register */ 81 __R uint32_t rsv_0x14; 82 __IO uint32_t fr; /**< <tt>\b 0x18:</tt> CLCD FR Register */ 83 __R uint32_t rsv_0x1c; 84 __IO uint32_t int_en; /**< <tt>\b 0x020:</tt> CLCD INT_EN Register */ 85 __IO uint32_t stat; /**< <tt>\b 0x024:</tt> CLCD STAT Register */ 86 __R uint32_t rsv_0x28_0x3ff[246]; 87 __IO uint32_t palette[256]; /**< <tt>\b 0x400:</tt> CLCD PALETTE Register */ 88 } mxc_clcd_regs_t; 89 90 /* Register offsets for module CLCD */ 91 /** 92 * @ingroup clcd_registers 93 * @defgroup CLCD_Register_Offsets Register Offsets 94 * @brief CLCD Peripheral Register Offsets from the CLCD Base Peripheral Address. 95 * @{ 96 */ 97 #define MXC_R_CLCD_CLK ((uint32_t)0x00000000UL) /**< Offset from CLCD Base Address: <tt> 0x0000</tt> */ 98 #define MXC_R_CLCD_VTIM_0 ((uint32_t)0x00000004UL) /**< Offset from CLCD Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_CLCD_VTIM_1 ((uint32_t)0x00000008UL) /**< Offset from CLCD Base Address: <tt> 0x0008</tt> */ 100 #define MXC_R_CLCD_HTIM ((uint32_t)0x0000000CUL) /**< Offset from CLCD Base Address: <tt> 0x000C</tt> */ 101 #define MXC_R_CLCD_CTRL ((uint32_t)0x00000010UL) /**< Offset from CLCD Base Address: <tt> 0x0010</tt> */ 102 #define MXC_R_CLCD_FR ((uint32_t)0x00000018UL) /**< Offset from CLCD Base Address: <tt> 0x0018</tt> */ 103 #define MXC_R_CLCD_INT_EN ((uint32_t)0x00000020UL) /**< Offset from CLCD Base Address: <tt> 0x0020</tt> */ 104 #define MXC_R_CLCD_STAT ((uint32_t)0x00000024UL) /**< Offset from CLCD Base Address: <tt> 0x0024</tt> */ 105 #define MXC_R_CLCD_PALETTE ((uint32_t)0x00000400UL) /**< Offset from CLCD Base Address: <tt> 0x0400</tt> */ 106 /**@} end of group clcd_registers */ 107 108 /** 109 * @ingroup clcd_registers 110 * @defgroup CLCD_CLK CLCD_CLK 111 * @brief LCD Clock Control Register 112 * @{ 113 */ 114 #define MXC_F_CLCD_CLK_CLKDIV_POS 0 /**< CLK_CLKDIV Position */ 115 #define MXC_F_CLCD_CLK_CLKDIV ((uint32_t)(0xFFUL << MXC_F_CLCD_CLK_CLKDIV_POS)) /**< CLK_CLKDIV Mask */ 116 117 #define MXC_F_CLCD_CLK_ACB_POS 8 /**< CLK_ACB Position */ 118 #define MXC_F_CLCD_CLK_ACB ((uint32_t)(0xFFUL << MXC_F_CLCD_CLK_ACB_POS)) /**< CLK_ACB Mask */ 119 120 #define MXC_F_CLCD_CLK_DPOL_POS 16 /**< CLK_DPOL Position */ 121 #define MXC_F_CLCD_CLK_DPOL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_DPOL_POS)) /**< CLK_DPOL Mask */ 122 123 #define MXC_F_CLCD_CLK_VPOL_POS 17 /**< CLK_VPOL Position */ 124 #define MXC_F_CLCD_CLK_VPOL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_VPOL_POS)) /**< CLK_VPOL Mask */ 125 126 #define MXC_F_CLCD_CLK_HPOL_POS 18 /**< CLK_HPOL Position */ 127 #define MXC_F_CLCD_CLK_HPOL ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_HPOL_POS)) /**< CLK_HPOL Mask */ 128 129 #define MXC_F_CLCD_CLK_EDGE_POS 19 /**< CLK_EDGE Position */ 130 #define MXC_F_CLCD_CLK_EDGE ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_EDGE_POS)) /**< CLK_EDGE Mask */ 131 132 #define MXC_F_CLCD_CLK_PASCLK_POS 20 /**< CLK_PASCLK Position */ 133 #define MXC_F_CLCD_CLK_PASCLK ((uint32_t)(0x1UL << MXC_F_CLCD_CLK_PASCLK_POS)) /**< CLK_PASCLK Mask */ 134 135 /**@} end of group CLCD_CLK_Register */ 136 137 /** 138 * @ingroup clcd_registers 139 * @defgroup CLCD_VTIM_0 CLCD_VTIM_0 140 * @brief LCD Vertical Timing 0 Register 141 * @{ 142 */ 143 #define MXC_F_CLCD_VTIM_0_VLINES_POS 0 /**< VTIM_0_VLINES Position */ 144 #define MXC_F_CLCD_VTIM_0_VLINES ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_0_VLINES_POS)) /**< VTIM_0_VLINES Mask */ 145 146 #define MXC_F_CLCD_VTIM_0_VBACKPORCH_POS 16 /**< VTIM_0_VBACKPORCH Position */ 147 #define MXC_F_CLCD_VTIM_0_VBACKPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_0_VBACKPORCH_POS)) /**< VTIM_0_VBACKPORCH Mask */ 148 149 /**@} end of group CLCD_VTIM_0_Register */ 150 151 /** 152 * @ingroup clcd_registers 153 * @defgroup CLCD_VTIM_1 CLCD_VTIM_1 154 * @brief LCD Vertical Timing 1 Register 155 * @{ 156 */ 157 #define MXC_F_CLCD_VTIM_1_VSYNCWIDTH_POS 0 /**< VTIM_1_VSYNCWIDTH Position */ 158 #define MXC_F_CLCD_VTIM_1_VSYNCWIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_1_VSYNCWIDTH_POS)) /**< VTIM_1_VSYNCWIDTH Mask */ 159 160 #define MXC_F_CLCD_VTIM_1_VFRONTPORCH_POS 16 /**< VTIM_1_VFRONTPORCH Position */ 161 #define MXC_F_CLCD_VTIM_1_VFRONTPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_VTIM_1_VFRONTPORCH_POS)) /**< VTIM_1_VFRONTPORCH Mask */ 162 163 /**@} end of group CLCD_VTIM_1_Register */ 164 165 /** 166 * @ingroup clcd_registers 167 * @defgroup CLCD_HTIM CLCD_HTIM 168 * @brief LCD Horizontal Timing Register. 169 * @{ 170 */ 171 #define MXC_F_CLCD_HTIM_HSYNCWIDTH_POS 0 /**< HTIM_HSYNCWIDTH Position */ 172 #define MXC_F_CLCD_HTIM_HSYNCWIDTH ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HSYNCWIDTH_POS)) /**< HTIM_HSYNCWIDTH Mask */ 173 174 #define MXC_F_CLCD_HTIM_HFRONTPORCH_POS 8 /**< HTIM_HFRONTPORCH Position */ 175 #define MXC_F_CLCD_HTIM_HFRONTPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HFRONTPORCH_POS)) /**< HTIM_HFRONTPORCH Mask */ 176 177 #define MXC_F_CLCD_HTIM_HSIZE_POS 16 /**< HTIM_HSIZE Position */ 178 #define MXC_F_CLCD_HTIM_HSIZE ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HSIZE_POS)) /**< HTIM_HSIZE Mask */ 179 180 #define MXC_F_CLCD_HTIM_HBACKPORCH_POS 24 /**< HTIM_HBACKPORCH Position */ 181 #define MXC_F_CLCD_HTIM_HBACKPORCH ((uint32_t)(0xFFUL << MXC_F_CLCD_HTIM_HBACKPORCH_POS)) /**< HTIM_HBACKPORCH Mask */ 182 183 /**@} end of group CLCD_HTIM_Register */ 184 185 /** 186 * @ingroup clcd_registers 187 * @defgroup CLCD_CTRL CLCD_CTRL 188 * @brief LCD Control Register 189 * @{ 190 */ 191 #define MXC_F_CLCD_CTRL_LCDEN_POS 0 /**< CTRL_LCDEN Position */ 192 #define MXC_F_CLCD_CTRL_LCDEN ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_LCDEN_POS)) /**< CTRL_LCDEN Mask */ 193 194 #define MXC_F_CLCD_CTRL_VISEL_POS 1 /**< CTRL_VISEL Position */ 195 #define MXC_F_CLCD_CTRL_VISEL ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_VISEL_POS)) /**< CTRL_VISEL Mask */ 196 #define MXC_V_CLCD_CTRL_VISEL_ONVERTSYNC ((uint32_t)0x0UL) /**< CTRL_VISEL_ONVERTSYNC Value */ 197 #define MXC_S_CLCD_CTRL_VISEL_ONVERTSYNC (MXC_V_CLCD_CTRL_VISEL_ONVERTSYNC << MXC_F_CLCD_CTRL_VISEL_POS) /**< CTRL_VISEL_ONVERTSYNC Setting */ 198 #define MXC_V_CLCD_CTRL_VISEL_ONVERTBACKPORCH ((uint32_t)0x1UL) /**< CTRL_VISEL_ONVERTBACKPORCH Value */ 199 #define MXC_S_CLCD_CTRL_VISEL_ONVERTBACKPORCH (MXC_V_CLCD_CTRL_VISEL_ONVERTBACKPORCH << MXC_F_CLCD_CTRL_VISEL_POS) /**< CTRL_VISEL_ONVERTBACKPORCH Setting */ 200 #define MXC_V_CLCD_CTRL_VISEL_ONACTIVEVIDEO ((uint32_t)0x2UL) /**< CTRL_VISEL_ONACTIVEVIDEO Value */ 201 #define MXC_S_CLCD_CTRL_VISEL_ONACTIVEVIDEO (MXC_V_CLCD_CTRL_VISEL_ONACTIVEVIDEO << MXC_F_CLCD_CTRL_VISEL_POS) /**< CTRL_VISEL_ONACTIVEVIDEO Setting */ 202 #define MXC_V_CLCD_CTRL_VISEL_ONVERTFRONTPORCH ((uint32_t)0x3UL) /**< CTRL_VISEL_ONVERTFRONTPORCH Value */ 203 #define MXC_S_CLCD_CTRL_VISEL_ONVERTFRONTPORCH (MXC_V_CLCD_CTRL_VISEL_ONVERTFRONTPORCH << MXC_F_CLCD_CTRL_VISEL_POS) /**< CTRL_VISEL_ONVERTFRONTPORCH Setting */ 204 205 #define MXC_F_CLCD_CTRL_DISPTYPE_POS 4 /**< CTRL_DISPTYPE Position */ 206 #define MXC_F_CLCD_CTRL_DISPTYPE ((uint32_t)(0xFUL << MXC_F_CLCD_CTRL_DISPTYPE_POS)) /**< CTRL_DISPTYPE Mask */ 207 #define MXC_V_CLCD_CTRL_DISPTYPE_STNCOLOR8BIT ((uint32_t)0x4UL) /**< CTRL_DISPTYPE_STNCOLOR8BIT Value */ 208 #define MXC_S_CLCD_CTRL_DISPTYPE_STNCOLOR8BIT (MXC_V_CLCD_CTRL_DISPTYPE_STNCOLOR8BIT << MXC_F_CLCD_CTRL_DISPTYPE_POS) /**< CTRL_DISPTYPE_STNCOLOR8BIT Setting */ 209 #define MXC_V_CLCD_CTRL_DISPTYPE_CLCD ((uint32_t)0x8UL) /**< CTRL_DISPTYPE_CLCD Value */ 210 #define MXC_S_CLCD_CTRL_DISPTYPE_CLCD (MXC_V_CLCD_CTRL_DISPTYPE_CLCD << MXC_F_CLCD_CTRL_DISPTYPE_POS) /**< CTRL_DISPTYPE_CLCD Setting */ 211 212 #define MXC_F_CLCD_CTRL_BPP_POS 8 /**< CTRL_BPP Position */ 213 #define MXC_F_CLCD_CTRL_BPP ((uint32_t)(0x7UL << MXC_F_CLCD_CTRL_BPP_POS)) /**< CTRL_BPP Mask */ 214 #define MXC_V_CLCD_CTRL_BPP_BPP1 ((uint32_t)0x0UL) /**< CTRL_BPP_BPP1 Value */ 215 #define MXC_S_CLCD_CTRL_BPP_BPP1 (MXC_V_CLCD_CTRL_BPP_BPP1 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP1 Setting */ 216 #define MXC_V_CLCD_CTRL_BPP_BPP2 ((uint32_t)0x1UL) /**< CTRL_BPP_BPP2 Value */ 217 #define MXC_S_CLCD_CTRL_BPP_BPP2 (MXC_V_CLCD_CTRL_BPP_BPP2 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP2 Setting */ 218 #define MXC_V_CLCD_CTRL_BPP_BPP4 ((uint32_t)0x2UL) /**< CTRL_BPP_BPP4 Value */ 219 #define MXC_S_CLCD_CTRL_BPP_BPP4 (MXC_V_CLCD_CTRL_BPP_BPP4 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP4 Setting */ 220 #define MXC_V_CLCD_CTRL_BPP_BPP8 ((uint32_t)0x3UL) /**< CTRL_BPP_BPP8 Value */ 221 #define MXC_S_CLCD_CTRL_BPP_BPP8 (MXC_V_CLCD_CTRL_BPP_BPP8 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP8 Setting */ 222 #define MXC_V_CLCD_CTRL_BPP_BPP16 ((uint32_t)0x4UL) /**< CTRL_BPP_BPP16 Value */ 223 #define MXC_S_CLCD_CTRL_BPP_BPP16 (MXC_V_CLCD_CTRL_BPP_BPP16 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP16 Setting */ 224 #define MXC_V_CLCD_CTRL_BPP_BPP24 ((uint32_t)0x5UL) /**< CTRL_BPP_BPP24 Value */ 225 #define MXC_S_CLCD_CTRL_BPP_BPP24 (MXC_V_CLCD_CTRL_BPP_BPP24 << MXC_F_CLCD_CTRL_BPP_POS) /**< CTRL_BPP_BPP24 Setting */ 226 227 #define MXC_F_CLCD_CTRL_MODE565_POS 11 /**< CTRL_MODE565 Position */ 228 #define MXC_F_CLCD_CTRL_MODE565 ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_MODE565_POS)) /**< CTRL_MODE565 Mask */ 229 230 #define MXC_F_CLCD_CTRL_EMODE_POS 12 /**< CTRL_EMODE Position */ 231 #define MXC_F_CLCD_CTRL_EMODE ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_EMODE_POS)) /**< CTRL_EMODE Mask */ 232 #define MXC_V_CLCD_CTRL_EMODE_LLBP ((uint32_t)0x0UL) /**< CTRL_EMODE_LLBP Value */ 233 #define MXC_S_CLCD_CTRL_EMODE_LLBP (MXC_V_CLCD_CTRL_EMODE_LLBP << MXC_F_CLCD_CTRL_EMODE_POS) /**< CTRL_EMODE_LLBP Setting */ 234 #define MXC_V_CLCD_CTRL_EMODE_BBBP ((uint32_t)0x1UL) /**< CTRL_EMODE_BBBP Value */ 235 #define MXC_S_CLCD_CTRL_EMODE_BBBP (MXC_V_CLCD_CTRL_EMODE_BBBP << MXC_F_CLCD_CTRL_EMODE_POS) /**< CTRL_EMODE_BBBP Setting */ 236 #define MXC_V_CLCD_CTRL_EMODE_LBBP ((uint32_t)0x2UL) /**< CTRL_EMODE_LBBP Value */ 237 #define MXC_S_CLCD_CTRL_EMODE_LBBP (MXC_V_CLCD_CTRL_EMODE_LBBP << MXC_F_CLCD_CTRL_EMODE_POS) /**< CTRL_EMODE_LBBP Setting */ 238 #define MXC_V_CLCD_CTRL_EMODE_RFU ((uint32_t)0x3UL) /**< CTRL_EMODE_RFU Value */ 239 #define MXC_S_CLCD_CTRL_EMODE_RFU (MXC_V_CLCD_CTRL_EMODE_RFU << MXC_F_CLCD_CTRL_EMODE_POS) /**< CTRL_EMODE_RFU Setting */ 240 241 #define MXC_F_CLCD_CTRL_C24_POS 15 /**< CTRL_C24 Position */ 242 #define MXC_F_CLCD_CTRL_C24 ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_C24_POS)) /**< CTRL_C24 Mask */ 243 244 #define MXC_F_CLCD_CTRL_BURST_POS 19 /**< CTRL_BURST Position */ 245 #define MXC_F_CLCD_CTRL_BURST ((uint32_t)(0x3UL << MXC_F_CLCD_CTRL_BURST_POS)) /**< CTRL_BURST Mask */ 246 #define MXC_V_CLCD_CTRL_BURST_WORDS4 ((uint32_t)0x0UL) /**< CTRL_BURST_WORDS4 Value */ 247 #define MXC_S_CLCD_CTRL_BURST_WORDS4 (MXC_V_CLCD_CTRL_BURST_WORDS4 << MXC_F_CLCD_CTRL_BURST_POS) /**< CTRL_BURST_WORDS4 Setting */ 248 #define MXC_V_CLCD_CTRL_BURST_WORDS8 ((uint32_t)0x1UL) /**< CTRL_BURST_WORDS8 Value */ 249 #define MXC_S_CLCD_CTRL_BURST_WORDS8 (MXC_V_CLCD_CTRL_BURST_WORDS8 << MXC_F_CLCD_CTRL_BURST_POS) /**< CTRL_BURST_WORDS8 Setting */ 250 251 #define MXC_F_CLCD_CTRL_LPOL_POS 21 /**< CTRL_LPOL Position */ 252 #define MXC_F_CLCD_CTRL_LPOL ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_LPOL_POS)) /**< CTRL_LPOL Mask */ 253 254 #define MXC_F_CLCD_CTRL_PEN_POS 22 /**< CTRL_PEN Position */ 255 #define MXC_F_CLCD_CTRL_PEN ((uint32_t)(0x1UL << MXC_F_CLCD_CTRL_PEN_POS)) /**< CTRL_PEN Mask */ 256 257 /**@} end of group CLCD_CTRL_Register */ 258 259 /** 260 * @ingroup clcd_registers 261 * @defgroup CLCD_INT_EN CLCD_INT_EN 262 * @brief LCD Interrupt Enable Register. 263 * @{ 264 */ 265 #define MXC_F_CLCD_INT_EN_UFLO_POS 0 /**< INT_EN_UFLO Position */ 266 #define MXC_F_CLCD_INT_EN_UFLO ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_UFLO_POS)) /**< INT_EN_UFLO Mask */ 267 268 #define MXC_F_CLCD_INT_EN_ADRRDY_POS 1 /**< INT_EN_ADRRDY Position */ 269 #define MXC_F_CLCD_INT_EN_ADRRDY ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_ADRRDY_POS)) /**< INT_EN_ADRRDY Mask */ 270 271 #define MXC_F_CLCD_INT_EN_VCI_POS 2 /**< INT_EN_VCI Position */ 272 #define MXC_F_CLCD_INT_EN_VCI ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_VCI_POS)) /**< INT_EN_VCI Mask */ 273 274 #define MXC_F_CLCD_INT_EN_BERR_POS 3 /**< INT_EN_BERR Position */ 275 #define MXC_F_CLCD_INT_EN_BERR ((uint32_t)(0x1UL << MXC_F_CLCD_INT_EN_BERR_POS)) /**< INT_EN_BERR Mask */ 276 277 /**@} end of group CLCD_INT_EN_Register */ 278 279 /** 280 * @ingroup clcd_registers 281 * @defgroup CLCD_STAT CLCD_STAT 282 * @brief LCD Status Register. 283 * @{ 284 */ 285 #define MXC_F_CLCD_STAT_UFLO_POS 0 /**< STAT_UFLO Position */ 286 #define MXC_F_CLCD_STAT_UFLO ((uint32_t)(0x1UL << MXC_F_CLCD_STAT_UFLO_POS)) /**< STAT_UFLO Mask */ 287 288 #define MXC_F_CLCD_STAT_ADRRDY_POS 1 /**< STAT_ADRRDY Position */ 289 #define MXC_F_CLCD_STAT_ADRRDY ((uint32_t)(0x1UL << MXC_F_CLCD_STAT_ADRRDY_POS)) /**< STAT_ADRRDY Mask */ 290 291 #define MXC_F_CLCD_STAT_VCI_POS 2 /**< STAT_VCI Position */ 292 #define MXC_F_CLCD_STAT_VCI ((uint32_t)(0x1UL << MXC_F_CLCD_STAT_VCI_POS)) /**< STAT_VCI Mask */ 293 294 #define MXC_F_CLCD_STAT_BERR_POS 3 /**< STAT_BERR Position */ 295 #define MXC_F_CLCD_STAT_BERR ((uint32_t)(0x1UL << MXC_F_CLCD_STAT_BERR_POS)) /**< STAT_BERR Mask */ 296 297 #define MXC_F_CLCD_STAT_LCDIDLE_POS 8 /**< STAT_LCDIDLE Position */ 298 #define MXC_F_CLCD_STAT_LCDIDLE ((uint32_t)(0x1UL << MXC_F_CLCD_STAT_LCDIDLE_POS)) /**< STAT_LCDIDLE Mask */ 299 300 /**@} end of group CLCD_STAT_Register */ 301 302 /** 303 * @ingroup clcd_registers 304 * @defgroup CLCD_PALETTE CLCD_PALETTE 305 * @brief Palette 306 * @{ 307 */ 308 #define MXC_F_CLCD_PALETTE_RED_POS 0 /**< PALETTE_RED Position */ 309 #define MXC_F_CLCD_PALETTE_RED ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_RED_POS)) /**< PALETTE_RED Mask */ 310 311 #define MXC_F_CLCD_PALETTE_GREEN_POS 8 /**< PALETTE_GREEN Position */ 312 #define MXC_F_CLCD_PALETTE_GREEN ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_GREEN_POS)) /**< PALETTE_GREEN Mask */ 313 314 #define MXC_F_CLCD_PALETTE_BLUE_POS 16 /**< PALETTE_BLUE Position */ 315 #define MXC_F_CLCD_PALETTE_BLUE ((uint32_t)(0xFFUL << MXC_F_CLCD_PALETTE_BLUE_POS)) /**< PALETTE_BLUE Mask */ 316 317 /**@} end of group CLCD_PALETTE_Register */ 318 319 #ifdef __cplusplus 320 } 321 #endif 322 323 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_CLCD_REGS_H_ 324
