1 /** 2 * @file sfe_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SFE Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup sfe_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SFE_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SFE_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup sfe 67 * @defgroup sfe_registers SFE_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SFE Peripheral Module. 69 * @details Serial Flash Emulator. 70 */ 71 72 /** 73 * @ingroup sfe_registers 74 * Structure type to access the SFE Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0_0x3ff[256]; 78 __IO uint32_t cfg; /**< <tt>\b 0x0400:</tt> SFE CFG Register */ 79 __R uint32_t rsv_0x404; 80 __IO uint32_t hfsa; /**< <tt>\b 0x0408:</tt> SFE HFSA Register */ 81 __IO uint32_t hrsa; /**< <tt>\b 0x040C:</tt> SFE HRSA Register */ 82 __IO uint32_t sfdp_sba; /**< <tt>\b 0x0410:</tt> SFE SFDP_SBA Register */ 83 __IO uint32_t flash_sba; /**< <tt>\b 0x0414:</tt> SFE FLASH_SBA Register */ 84 __IO uint32_t flash_sta; /**< <tt>\b 0x0418:</tt> SFE FLASH_STA Register */ 85 __IO uint32_t ram_sba; /**< <tt>\b 0x041C:</tt> SFE RAM_SBA Register */ 86 __IO uint32_t ram_sta; /**< <tt>\b 0x0420:</tt> SFE RAM_STA Register */ 87 } mxc_sfe_regs_t; 88 89 /* Register offsets for module SFE */ 90 /** 91 * @ingroup sfe_registers 92 * @defgroup SFE_Register_Offsets Register Offsets 93 * @brief SFE Peripheral Register Offsets from the SFE Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_SFE_CFG ((uint32_t)0x00000400UL) /**< Offset from SFE Base Address: <tt> 0x0400</tt> */ 97 #define MXC_R_SFE_HFSA ((uint32_t)0x00000408UL) /**< Offset from SFE Base Address: <tt> 0x0408</tt> */ 98 #define MXC_R_SFE_HRSA ((uint32_t)0x0000040CUL) /**< Offset from SFE Base Address: <tt> 0x040C</tt> */ 99 #define MXC_R_SFE_SFDP_SBA ((uint32_t)0x00000410UL) /**< Offset from SFE Base Address: <tt> 0x0410</tt> */ 100 #define MXC_R_SFE_FLASH_SBA ((uint32_t)0x00000414UL) /**< Offset from SFE Base Address: <tt> 0x0414</tt> */ 101 #define MXC_R_SFE_FLASH_STA ((uint32_t)0x00000418UL) /**< Offset from SFE Base Address: <tt> 0x0418</tt> */ 102 #define MXC_R_SFE_RAM_SBA ((uint32_t)0x0000041CUL) /**< Offset from SFE Base Address: <tt> 0x041C</tt> */ 103 #define MXC_R_SFE_RAM_STA ((uint32_t)0x00000420UL) /**< Offset from SFE Base Address: <tt> 0x0420</tt> */ 104 /**@} end of group sfe_registers */ 105 106 /** 107 * @ingroup sfe_registers 108 * @defgroup SFE_CFG SFE_CFG 109 * @brief SFE Configuration Register. 110 * @{ 111 */ 112 #define MXC_F_SFE_CFG_DRLE_POS 0 /**< CFG_DRLE Position */ 113 #define MXC_F_SFE_CFG_DRLE ((uint32_t)(0x1UL << MXC_F_SFE_CFG_DRLE_POS)) /**< CFG_DRLE Mask */ 114 115 #define MXC_F_SFE_CFG_FLOCK_POS 15 /**< CFG_FLOCK Position */ 116 #define MXC_F_SFE_CFG_FLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_FLOCK_POS)) /**< CFG_FLOCK Mask */ 117 118 #define MXC_F_SFE_CFG_RD_EN_POS 16 /**< CFG_RD_EN Position */ 119 #define MXC_F_SFE_CFG_RD_EN ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RD_EN_POS)) /**< CFG_RD_EN Mask */ 120 121 #define MXC_F_SFE_CFG_WR_EN_POS 17 /**< CFG_WR_EN Position */ 122 #define MXC_F_SFE_CFG_WR_EN ((uint32_t)(0x1UL << MXC_F_SFE_CFG_WR_EN_POS)) /**< CFG_WR_EN Mask */ 123 124 #define MXC_F_SFE_CFG_RRLOCK_POS 22 /**< CFG_RRLOCK Position */ 125 #define MXC_F_SFE_CFG_RRLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RRLOCK_POS)) /**< CFG_RRLOCK Mask */ 126 127 #define MXC_F_SFE_CFG_RWLOCK_POS 23 /**< CFG_RWLOCK Position */ 128 #define MXC_F_SFE_CFG_RWLOCK ((uint32_t)(0x1UL << MXC_F_SFE_CFG_RWLOCK_POS)) /**< CFG_RWLOCK Mask */ 129 130 /**@} end of group SFE_CFG_Register */ 131 132 /** 133 * @ingroup sfe_registers 134 * @defgroup SFE_HFSA SFE_HFSA 135 * @brief SFE Host Flash Start Address Register. 136 * @{ 137 */ 138 #define MXC_F_SFE_HFSA_HFSA_POS 10 /**< HFSA_HFSA Position */ 139 #define MXC_F_SFE_HFSA_HFSA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_HFSA_HFSA_POS)) /**< HFSA_HFSA Mask */ 140 141 /**@} end of group SFE_HFSA_Register */ 142 143 /** 144 * @ingroup sfe_registers 145 * @defgroup SFE_HRSA SFE_HRSA 146 * @brief SFE Host RAM Start Address Register. 147 * @{ 148 */ 149 #define MXC_F_SFE_HRSA_HRSA_POS 10 /**< HRSA_HRSA Position */ 150 #define MXC_F_SFE_HRSA_HRSA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_HRSA_HRSA_POS)) /**< HRSA_HRSA Mask */ 151 152 /**@} end of group SFE_HRSA_Register */ 153 154 /** 155 * @ingroup sfe_registers 156 * @defgroup SFE_SFDP_SBA SFE_SFDP_SBA 157 * @brief SFE Discoverable Parameter System Base Register. 158 * @{ 159 */ 160 #define MXC_F_SFE_SFDP_SBA_SFDP_SBA_POS 8 /**< SFDP_SBA_SFDP_SBA Position */ 161 #define MXC_F_SFE_SFDP_SBA_SFDP_SBA ((uint32_t)(0xFFFFFFUL << MXC_F_SFE_SFDP_SBA_SFDP_SBA_POS)) /**< SFDP_SBA_SFDP_SBA Mask */ 162 163 /**@} end of group SFE_SFDP_SBA_Register */ 164 165 /** 166 * @ingroup sfe_registers 167 * @defgroup SFE_FLASH_SBA SFE_FLASH_SBA 168 * @brief Flash System Base Address Register. 169 * @{ 170 */ 171 #define MXC_F_SFE_FLASH_SBA_FLASH_SBA_POS 10 /**< FLASH_SBA_FLASH_SBA Position */ 172 #define MXC_F_SFE_FLASH_SBA_FLASH_SBA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_FLASH_SBA_FLASH_SBA_POS)) /**< FLASH_SBA_FLASH_SBA Mask */ 173 174 /**@} end of group SFE_FLASH_SBA_Register */ 175 176 /** 177 * @ingroup sfe_registers 178 * @defgroup SFE_FLASH_STA SFE_FLASH_STA 179 * @brief Flash System Top Address Register. 180 * @{ 181 */ 182 #define MXC_F_SFE_FLASH_STA_FLASH_STA_POS 10 /**< FLASH_STA_FLASH_STA Position */ 183 #define MXC_F_SFE_FLASH_STA_FLASH_STA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_FLASH_STA_FLASH_STA_POS)) /**< FLASH_STA_FLASH_STA Mask */ 184 185 /**@} end of group SFE_FLASH_STA_Register */ 186 187 /** 188 * @ingroup sfe_registers 189 * @defgroup SFE_RAM_SBA SFE_RAM_SBA 190 * @brief RAM System Base Address Register. 191 * @{ 192 */ 193 #define MXC_F_SFE_RAM_SBA_RAM_SBA_POS 10 /**< RAM_SBA_RAM_SBA Position */ 194 #define MXC_F_SFE_RAM_SBA_RAM_SBA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_RAM_SBA_RAM_SBA_POS)) /**< RAM_SBA_RAM_SBA Mask */ 195 196 /**@} end of group SFE_RAM_SBA_Register */ 197 198 /** 199 * @ingroup sfe_registers 200 * @defgroup SFE_RAM_STA SFE_RAM_STA 201 * @brief RAM System Top Address Register. 202 * @{ 203 */ 204 #define MXC_F_SFE_RAM_STA_RAM_STA_POS 10 /**< RAM_STA_RAM_STA Position */ 205 #define MXC_F_SFE_RAM_STA_RAM_STA ((uint32_t)(0x3FFFFFUL << MXC_F_SFE_RAM_STA_RAM_STA_POS)) /**< RAM_STA_RAM_STA Mask */ 206 207 /**@} end of group SFE_RAM_STA_Register */ 208 209 #ifdef __cplusplus 210 } 211 #endif 212 213 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SFE_REGS_H_ 214
