1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpcn; /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */ 78 __IO uint32_t lpwkst0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */ 81 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 82 __R uint32_t rsv_0x14_0x2f[7]; 83 __IO uint32_t lppwkst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKST Register */ 84 __R uint32_t rsv_0x34_0x3f[3]; 85 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 86 __R uint32_t rsv_0x44; 87 __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */ 88 __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */ 89 } mxc_pwrseq_regs_t; 90 91 /* Register offsets for module PWRSEQ */ 92 /** 93 * @ingroup pwrseq_registers 94 * @defgroup PWRSEQ_Register_Offsets Register Offsets 95 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 96 * @{ 97 */ 98 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 99 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 100 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 101 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 102 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 103 #define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 104 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 105 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 106 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 107 /**@} end of group pwrseq_registers */ 108 109 /** 110 * @ingroup pwrseq_registers 111 * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN 112 * @brief Low Power Control Register. 113 * @{ 114 */ 115 #define MXC_F_PWRSEQ_LPCN_RAMRET_EN_POS 0 /**< LPCN_RAMRET_EN Position */ 116 #define MXC_F_PWRSEQ_LPCN_RAMRET_EN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_EN_POS)) /**< LPCN_RAMRET_EN Mask */ 117 118 #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ 119 #define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ 120 121 #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ 122 #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ 123 124 #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ 125 #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ 126 127 /**@} end of group PWRSEQ_LPCN_Register */ 128 129 /** 130 * @ingroup pwrseq_registers 131 * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 132 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 133 * wakeup status for GPIO0. 134 * @{ 135 */ 136 #define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ 137 #define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0xFFFFUL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ 138 139 /**@} end of group PWRSEQ_LPWKST0_Register */ 140 141 /** 142 * @ingroup pwrseq_registers 143 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 144 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 145 * functionality for GPIO0. 146 * @{ 147 */ 148 #define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ 149 #define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0xFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ 150 151 /**@} end of group PWRSEQ_LPWKEN0_Register */ 152 153 /** 154 * @ingroup pwrseq_registers 155 * @defgroup PWRSEQ_LPWKST1 PWRSEQ_LPWKST1 156 * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power 157 * wakeup status for GPIO1. 158 * @{ 159 */ 160 #define MXC_F_PWRSEQ_LPWKST1_ST_POS 0 /**< LPWKST1_ST Position */ 161 #define MXC_F_PWRSEQ_LPWKST1_ST ((uint32_t)(0x7FFUL << MXC_F_PWRSEQ_LPWKST1_ST_POS)) /**< LPWKST1_ST Mask */ 162 163 /**@} end of group PWRSEQ_LPWKST1_Register */ 164 165 /** 166 * @ingroup pwrseq_registers 167 * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1 168 * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup 169 * functionality for GPIO1. 170 * @{ 171 */ 172 #define MXC_F_PWRSEQ_LPWKEN1_EN_POS 0 /**< LPWKEN1_EN Position */ 173 #define MXC_F_PWRSEQ_LPWKEN1_EN ((uint32_t)(0x7FFUL << MXC_F_PWRSEQ_LPWKEN1_EN_POS)) /**< LPWKEN1_EN Mask */ 174 175 /**@} end of group PWRSEQ_LPWKEN1_Register */ 176 177 /** 178 * @ingroup pwrseq_registers 179 * @defgroup PWRSEQ_LPPWKST PWRSEQ_LPPWKST 180 * @brief Low Power Peripheral Wakeup Status Register. 181 * @{ 182 */ 183 #define MXC_F_PWRSEQ_LPPWKST_BBMOD_POS 16 /**< LPPWKST_BBMOD Position */ 184 #define MXC_F_PWRSEQ_LPPWKST_BBMOD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_BBMOD_POS)) /**< LPPWKST_BBMOD Mask */ 185 186 #define MXC_F_PWRSEQ_LPPWKST_RST_POS 17 /**< LPPWKST_RST Position */ 187 #define MXC_F_PWRSEQ_LPPWKST_RST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_RST_POS)) /**< LPPWKST_RST Mask */ 188 189 #define MXC_F_PWRSEQ_LPPWKST_SDMA1_POS 18 /**< LPPWKST_SDMA1 Position */ 190 #define MXC_F_PWRSEQ_LPPWKST_SDMA1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_SDMA1_POS)) /**< LPPWKST_SDMA1 Mask */ 191 192 /**@} end of group PWRSEQ_LPPWKST_Register */ 193 194 /** 195 * @ingroup pwrseq_registers 196 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 197 * @brief Low Power Memory Shutdown Control. 198 * @{ 199 */ 200 #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ 201 #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ 202 203 #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ 204 #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ 205 206 #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ 207 #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ 208 209 #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ 210 #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ 211 212 #define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS 4 /**< LPMEMSD_RAM4 Position */ 213 #define MXC_F_PWRSEQ_LPMEMSD_RAM4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) /**< LPMEMSD_RAM4 Mask */ 214 215 #define MXC_F_PWRSEQ_LPMEMSD_ICACHE_POS 7 /**< LPMEMSD_ICACHE Position */ 216 #define MXC_F_PWRSEQ_LPMEMSD_ICACHE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHE_POS)) /**< LPMEMSD_ICACHE Mask */ 217 218 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP_POS 8 /**< LPMEMSD_ICACHEXIP Position */ 219 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIP_POS)) /**< LPMEMSD_ICACHEXIP Mask */ 220 221 #define MXC_F_PWRSEQ_LPMEMSD_ROM_POS 12 /**< LPMEMSD_ROM Position */ 222 #define MXC_F_PWRSEQ_LPMEMSD_ROM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM_POS)) /**< LPMEMSD_ROM Mask */ 223 224 /**@} end of group PWRSEQ_LPMEMSD_Register */ 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_PWRSEQ_REGS_H_ 231
