1<?xml version='1.0' encoding='utf-8'?> 2<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <vendor>Maxim-Integrated</vendor> 4 <vendorID>Maxim</vendorID> 5 <name>max32520</name> 6 <series>ARMCM4</series> 7 <version>1.0</version> 8 <description>MAX32520 32-bit ARM Cortex-M4 microcontroller, 1024KB of flash, 760KB of system RAM, 128KB of Boot ROM.</description> 9 <cpu> 10 <name>CM4</name> 11 <revision>r2p1</revision> 12 <endian>little</endian> 13 <mpuPresent>true</mpuPresent> 14 <fpuPresent>true</fpuPresent> 15 <nvicPrioBits>3</nvicPrioBits> 16 <vendorSystickConfig>false</vendorSystickConfig> 17 </cpu> 18 <addressUnitBits>8</addressUnitBits> 19 <width>32</width> 20 <size>0x20</size> 21 <access>read-write</access> 22 <resetValue>0x00000000</resetValue> 23 <resetMask>0xFFFFFFFF</resetMask> 24 <peripherals> 25 <peripheral> 26 <name>AESKEYS</name> 27 <description>AES Keys.</description> 28 <baseAddress>0x40005000</baseAddress> 29 <addressBlock> 30 <offset>0x00</offset> 31 <size>0x400</size> 32 <usage>registers</usage> 33 </addressBlock> 34 <registers> 35 <register> 36 <name>SRAM_KEY</name> 37 <description>AES SRAM KEY</description> 38 <addressOffset>0x000</addressOffset> 39 <size>32</size> 40 </register> 41 <register> 42 <name>CODE_KEY</name> 43 <description>AES CODE Key </description> 44 <addressOffset>0x080</addressOffset> 45 </register> 46 <register> 47 <name>DATA_KEY</name> 48 <description>AES DATA KEY</description> 49 <addressOffset>0x100</addressOffset> 50 </register> 51 </registers> 52 </peripheral> 53<!--AESKEYS AES Keys.--> 54 <peripheral> 55 <name>CTB</name> 56 <description>The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.</description> 57 <baseAddress>0x40001000</baseAddress> 58 <addressBlock> 59 <offset>0x00</offset> 60 <size>0x1000</size> 61 <usage>registers</usage> 62 </addressBlock> 63 <interrupt> 64 <name>Crypto_Engine</name> 65 <description>Crypto Engine interrupt.</description> 66 <value>27</value> 67 </interrupt> 68 <registers> 69 <register> 70 <name>CRYPTO_CTRL</name> 71 <description>Crypto Control Register.</description> 72 <addressOffset>0x00</addressOffset> 73 <resetValue>0xC0000000</resetValue> 74 <fields> 75 <field> 76 <name>RST</name> 77 <description>Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.</description> 78 <bitOffset>0</bitOffset> 79 <bitWidth>1</bitWidth> 80 </field> 81 <field> 82 <name>INT</name> 83 <description>Interrupt Enable. Generates an interrupt when done or error set.</description> 84 <bitOffset>1</bitOffset> 85 <bitWidth>1</bitWidth> 86 <enumeratedValues> 87 <enumeratedValue> 88 <name>dis</name> 89 <description>Disable</description> 90 <value>0</value> 91 </enumeratedValue> 92 <enumeratedValue> 93 <name>en</name> 94 <description>Enable</description> 95 <value>1</value> 96 </enumeratedValue> 97 </enumeratedValues> 98 </field> 99 <field> 100 <name>SRC</name> 101 <description>Source Select. This bit selects the hash function and CRC generator input source.</description> 102 <bitOffset>2</bitOffset> 103 <bitWidth>1</bitWidth> 104 <enumeratedValues> 105 <enumeratedValue> 106 <name>inputFIFO</name> 107 <description>Input FIFO</description> 108 <value>0</value> 109 </enumeratedValue> 110 <enumeratedValue> 111 <name>outputFIFO</name> 112 <description>Output FIFO</description> 113 <value>1</value> 114 </enumeratedValue> 115 </enumeratedValues> 116 </field> 117 <field> 118 <name>BSO</name> 119 <description>Byte Swap Output. Note. No byte swap will occur if there is not a full word.</description> 120 <bitOffset>4</bitOffset> 121 <bitWidth>1</bitWidth> 122 </field> 123 <field> 124 <name>BSI</name> 125 <description>Byte Swap Input. Note. No byte swap will occur if there is not a full word.</description> 126 <bitOffset>5</bitOffset> 127 <bitWidth>1</bitWidth> 128 </field> 129 <field> 130 <name>WAIT_EN</name> 131 <description>Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.</description> 132 <bitOffset>6</bitOffset> 133 <bitWidth>1</bitWidth> 134 </field> 135 <field> 136 <name>WAIT_POL</name> 137 <description>Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.</description> 138 <bitOffset>7</bitOffset> 139 <bitWidth>1</bitWidth> 140 <enumeratedValues> 141 <enumeratedValue> 142 <name>activeLo</name> 143 <description>Active Low.</description> 144 <value>0</value> 145 </enumeratedValue> 146 <enumeratedValue> 147 <name>activeHi</name> 148 <description>Active High.</description> 149 <value>1</value> 150 </enumeratedValue> 151 </enumeratedValues> 152 </field> 153 <field> 154 <name>WRSRC</name> 155 <description>Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.</description> 156 <bitOffset>8</bitOffset> 157 <bitWidth>2</bitWidth> 158 <enumeratedValues> 159 <enumeratedValue> 160 <name>none</name> 161 <description>None.</description> 162 <value>0</value> 163 </enumeratedValue> 164 <enumeratedValue> 165 <name>cipherOutput</name> 166 <description>Cipher Output.</description> 167 <value>1</value> 168 </enumeratedValue> 169 <enumeratedValue> 170 <name>readFIFO</name> 171 <description>Read FIFO.</description> 172 <value>2</value> 173 </enumeratedValue> 174 </enumeratedValues> 175 </field> 176 <field> 177 <name>RDSRC</name> 178 <description>Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.</description> 179 <bitOffset>10</bitOffset> 180 <bitWidth>2</bitWidth> 181 <enumeratedValues> 182 <enumeratedValue> 183 <name>dmaDisabled</name> 184 <description>DMA Disable.</description> 185 <value>0</value> 186 </enumeratedValue> 187 <enumeratedValue> 188 <name>dmaOrApb</name> 189 <description>DMA Or APB.</description> 190 <value>1</value> 191 </enumeratedValue> 192 <enumeratedValue> 193 <name>rng</name> 194 <description>RNG.</description> 195 <value>2</value> 196 </enumeratedValue> 197 </enumeratedValues> 198 </field> 199 <field> 200 <name>FLAG_MODE</name> 201 <description>Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.</description> 202 <bitOffset>14</bitOffset> 203 <bitWidth>1</bitWidth> 204 <enumeratedValues> 205 <enumeratedValue> 206 <name>unres_wr</name> 207 <description>Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.</description> 208 <value>0</value> 209 </enumeratedValue> 210 <enumeratedValue> 211 <name>res_wr</name> 212 <description>Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.</description> 213 <value>1</value> 214 </enumeratedValue> 215 </enumeratedValues> 216 </field> 217 <field> 218 <name>DMADNEMSK</name> 219 <description>DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.</description> 220 <bitOffset>15</bitOffset> 221 <bitWidth>1</bitWidth> 222 <enumeratedValues> 223 <enumeratedValue> 224 <name>not_used</name> 225 <description>DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.</description> 226 <value>0</value> 227 </enumeratedValue> 228 <enumeratedValue> 229 <name>used</name> 230 <description>DMA_DONE used in setting CRYPTO_CTRL.DONE bit.</description> 231 <value>1</value> 232 </enumeratedValue> 233 </enumeratedValues> 234 </field> 235 <field> 236 <name>DMA_DONE</name> 237 <description>DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.</description> 238 <bitOffset>24</bitOffset> 239 <bitWidth>1</bitWidth> 240 <enumeratedValues> 241 <enumeratedValue> 242 <name>notDone</name> 243 <description>Not Done.</description> 244 <value>0</value> 245 </enumeratedValue> 246 <enumeratedValue> 247 <name>done</name> 248 <description>Done.</description> 249 <value>1</value> 250 </enumeratedValue> 251 </enumeratedValues> 252 </field> 253 <field derivedFrom="DMA_DONE"> 254 <name>GLS_DONE</name> 255 <description>Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.</description> 256 <bitOffset>25</bitOffset> 257 <bitWidth>1</bitWidth> 258 </field> 259 <field derivedFrom="DMA_DONE"> 260 <name>HSH_DONE</name> 261 <description>Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.</description> 262 <bitOffset>26</bitOffset> 263 <bitWidth>1</bitWidth> 264 </field> 265 <field derivedFrom="DMA_DONE"> 266 <name>CPH_DONE</name> 267 <description>Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.</description> 268 <bitOffset>27</bitOffset> 269 <bitWidth>1</bitWidth> 270 </field> 271 <field> 272 <name>ERR</name> 273 <description>AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.</description> 274 <bitOffset>29</bitOffset> 275 <bitWidth>1</bitWidth> 276 <access>read-only</access> 277 <enumeratedValues> 278 <enumeratedValue> 279 <name>noError</name> 280 <description>No Error.</description> 281 <value>0</value> 282 </enumeratedValue> 283 <enumeratedValue> 284 <name>error</name> 285 <description>Error.</description> 286 <value>1</value> 287 </enumeratedValue> 288 </enumeratedValues> 289 </field> 290 <field> 291 <name>RDY</name> 292 <description>Ready. Crypto block ready for more data.</description> 293 <bitOffset>30</bitOffset> 294 <bitWidth>1</bitWidth> 295 <access>read-only</access> 296 <enumeratedValues> 297 <enumeratedValue> 298 <name>busy</name> 299 <description>Busy.</description> 300 <value>0</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>ready</name> 304 <description>Ready.</description> 305 <value>1</value> 306 </enumeratedValue> 307 </enumeratedValues> 308 </field> 309 <field derivedFrom="DMA_DONE"> 310 <name>DONE</name> 311 <description>Done. One or more cryptographic calculations complete (logical OR of done flags).</description> 312 <bitOffset>31</bitOffset> 313 <bitWidth>1</bitWidth> 314 <access>read-only</access> 315 </field> 316 </fields> 317 </register> 318 <register> 319 <name>CIPHER_CTRL</name> 320 <description>Cipher Control Register.</description> 321 <addressOffset>0x04</addressOffset> 322 <fields> 323 <field> 324 <name>ENC</name> 325 <description>Encrypt. Select encryption or decryption of input data.</description> 326 <bitOffset>0</bitOffset> 327 <bitWidth>1</bitWidth> 328 <enumeratedValues> 329 <enumeratedValue> 330 <name>encrypt</name> 331 <description>Encrypt.</description> 332 <value>0</value> 333 </enumeratedValue> 334 <enumeratedValue> 335 <name>decrypt</name> 336 <description>Decrypt.</description> 337 <value>1</value> 338 </enumeratedValue> 339 </enumeratedValues> 340 </field> 341 <field> 342 <name>KEY</name> 343 <description>Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.</description> 344 <bitOffset>1</bitOffset> 345 <bitWidth>1</bitWidth> 346 <enumeratedValues> 347 <enumeratedValue> 348 <name>complete</name> 349 <description>No operation/complete.</description> 350 <value>0</value> 351 </enumeratedValue> 352 <enumeratedValue> 353 <name>start</name> 354 <description>Start operation.</description> 355 <value>1</value> 356 </enumeratedValue> 357 </enumeratedValues> 358 </field> 359 <field> 360 <name>SRC</name> 361 <description>Source of Random key.</description> 362 <bitOffset>2</bitOffset> 363 <bitWidth>2</bitWidth> 364 <enumeratedValues> 365 <enumeratedValue> 366 <name>cipherKey</name> 367 <description>User cipher key (0x4000_1060).</description> 368 <value>0</value> 369 </enumeratedValue> 370 <enumeratedValue> 371 <name>regFile</name> 372 <description>Key from battery-backed register file (0x4000_5000 to 0x4000_501F).</description> 373 <value>2</value> 374 </enumeratedValue> 375 <enumeratedValue> 376 <name>qspiKey_regFile</name> 377 <description>Key from battery-backed register file (0x4000_5020 to 0x4000_502F).</description> 378 <value>3</value> 379 </enumeratedValue> 380 </enumeratedValues> 381 </field> 382 <field> 383 <name>CIPHER</name> 384 <description>Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.</description> 385 <bitOffset>4</bitOffset> 386 <bitWidth>3</bitWidth> 387 <enumeratedValues> 388 <enumeratedValue> 389 <name>dis</name> 390 <description>Disabled.</description> 391 <value>0</value> 392 </enumeratedValue> 393 <enumeratedValue> 394 <name>aes128</name> 395 <description>AES 128.</description> 396 <value>1</value> 397 </enumeratedValue> 398 <enumeratedValue> 399 <name>aes192</name> 400 <description>AES 192.</description> 401 <value>2</value> 402 </enumeratedValue> 403 <enumeratedValue> 404 <name>aes256</name> 405 <description>AES 256.</description> 406 <value>3</value> 407 </enumeratedValue> 408 <enumeratedValue> 409 <name>des</name> 410 <description>DES.</description> 411 <value>4</value> 412 </enumeratedValue> 413 <enumeratedValue> 414 <name>tdes</name> 415 <description>Triple DES.</description> 416 <value>5</value> 417 </enumeratedValue> 418 </enumeratedValues> 419 </field> 420 <field> 421 <name>MODE</name> 422 <description>Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.</description> 423 <bitOffset>8</bitOffset> 424 <bitWidth>3</bitWidth> 425 <enumeratedValues> 426 <enumeratedValue> 427 <name>ECB</name> 428 <description>ECB Mode.</description> 429 <value>0</value> 430 </enumeratedValue> 431 <enumeratedValue> 432 <name>CBC</name> 433 <description>CBC Mode.</description> 434 <value>1</value> 435 </enumeratedValue> 436 <enumeratedValue> 437 <name>CFB</name> 438 <description>CFB (AES only).</description> 439 <value>2</value> 440 </enumeratedValue> 441 <enumeratedValue> 442 <name>OFB</name> 443 <description>OFB (AES only).</description> 444 <value>3</value> 445 </enumeratedValue> 446 <enumeratedValue> 447 <name>CTR</name> 448 <description>CTR (AES only).</description> 449 <value>4</value> 450 </enumeratedValue> 451 </enumeratedValues> 452 </field> 453 <field> 454 <name>COMPH</name> 455 <description>H Vector Computation.</description> 456 <bitOffset>11</bitOffset> 457 <bitWidth>1</bitWidth> 458 <access>read-only</access> 459 </field> 460 <field> 461 <name>DTYPE</name> 462 <description>GCM/CCM data type.</description> 463 <bitOffset>12</bitOffset> 464 <bitWidth>1</bitWidth> 465 <access>read-only</access> 466 </field> 467 <field> 468 <name>CCMM</name> 469 <description>CCM M Parameter.</description> 470 <bitOffset>13</bitOffset> 471 <bitWidth>3</bitWidth> 472 <access>read-only</access> 473 </field> 474 <field> 475 <name>CCML</name> 476 <description>CCM L Parameter.</description> 477 <bitOffset>16</bitOffset> 478 <bitWidth>3</bitWidth> 479 <access>read-only</access> 480 </field> 481 </fields> 482 </register> 483 <register> 484 <name>HASH_CTRL</name> 485 <description>HASH Control Register.</description> 486 <addressOffset>0x08</addressOffset> 487 <fields> 488 <field> 489 <name>INIT</name> 490 <description>Initialize. Initializes hash registers with standard constants.</description> 491 <bitOffset>0</bitOffset> 492 <bitWidth>1</bitWidth> 493 <enumeratedValues> 494 <enumeratedValue> 495 <name>nop</name> 496 <description>No operation/complete.</description> 497 <value>0</value> 498 </enumeratedValue> 499 <enumeratedValue> 500 <name>start</name> 501 <description>Start operation.</description> 502 <value>1</value> 503 </enumeratedValue> 504 </enumeratedValues> 505 </field> 506 <field> 507 <name>XOR</name> 508 <description>XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.</description> 509 <bitOffset>1</bitOffset> 510 <bitWidth>1</bitWidth> 511 <enumeratedValues> 512 <enumeratedValue> 513 <name>dis</name> 514 <description>Disable.</description> 515 <value>0</value> 516 </enumeratedValue> 517 <enumeratedValue> 518 <name>en</name> 519 <description>Enable.</description> 520 <value>1</value> 521 </enumeratedValue> 522 </enumeratedValues> 523 </field> 524 <field> 525 <name>HASH</name> 526 <description>Hash function selection.</description> 527 <bitOffset>2</bitOffset> 528 <bitWidth>3</bitWidth> 529 <enumeratedValues> 530 <enumeratedValue> 531 <name>dis</name> 532 <description>Disabled.</description> 533 <value>0</value> 534 </enumeratedValue> 535 <enumeratedValue> 536 <name>sha1</name> 537 <description>SHA-1.</description> 538 <value>1</value> 539 </enumeratedValue> 540 <enumeratedValue> 541 <name>sha224</name> 542 <description>SHA 224.</description> 543 <value>2</value> 544 </enumeratedValue> 545 <enumeratedValue> 546 <name>sha256</name> 547 <description>SHA 256.</description> 548 <value>3</value> 549 </enumeratedValue> 550 <enumeratedValue> 551 <name>sha384</name> 552 <description>SHA 384.</description> 553 <value>4</value> 554 </enumeratedValue> 555 <enumeratedValue> 556 <name>sha512</name> 557 <description>SHA 512.</description> 558 <value>5</value> 559 </enumeratedValue> 560 </enumeratedValues> 561 </field> 562 <field> 563 <name>LAST</name> 564 <description>Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.</description> 565 <bitOffset>5</bitOffset> 566 <bitWidth>1</bitWidth> 567 <enumeratedValues> 568 <enumeratedValue> 569 <name>noEffect</name> 570 <description>No Effect.</description> 571 <value>0</value> 572 </enumeratedValue> 573 <enumeratedValue> 574 <name>lastMsgData</name> 575 <description>Last Message Data.</description> 576 <value>1</value> 577 </enumeratedValue> 578 </enumeratedValues> 579 </field> 580 </fields> 581 </register> 582 <register> 583 <name>CRC_CTRL</name> 584 <description>CRC Control Register.</description> 585 <addressOffset>0x0C</addressOffset> 586 <fields> 587 <field> 588 <name>CRC</name> 589 <description>Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.</description> 590 <bitOffset>0</bitOffset> 591 <bitWidth>1</bitWidth> 592 <enumeratedValues> 593 <enumeratedValue> 594 <name>dis</name> 595 <description>Disable.</description> 596 <value>0</value> 597 </enumeratedValue> 598 <enumeratedValue> 599 <name>en</name> 600 <description>Enable.</description> 601 <value>1</value> 602 </enumeratedValue> 603 </enumeratedValues> 604 </field> 605 <field> 606 <name>MSB</name> 607 <description>MSB select. This bit selects the order of calculating CRC on data.</description> 608 <bitOffset>1</bitOffset> 609 <bitWidth>1</bitWidth> 610 <enumeratedValues> 611 <enumeratedValue> 612 <name>lsbFirst</name> 613 <description>LSB First.</description> 614 <value>0</value> 615 </enumeratedValue> 616 <enumeratedValue> 617 <name>msbFirst</name> 618 <description>MSB First.</description> 619 <value>1</value> 620 </enumeratedValue> 621 </enumeratedValues> 622 </field> 623 <field derivedFrom="CRC"> 624 <name>PRNG</name> 625 <description>Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.</description> 626 <bitOffset>2</bitOffset> 627 <bitWidth>1</bitWidth> 628 </field> 629 <field derivedFrom="CRC"> 630 <name>ENT</name> 631 <description>Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.</description> 632 <bitOffset>3</bitOffset> 633 <bitWidth>1</bitWidth> 634 </field> 635 <field derivedFrom="CRC"> 636 <name>HAM</name> 637 <description>Hamming Code Enable. Enable hamming code calculation.</description> 638 <bitOffset>4</bitOffset> 639 <bitWidth>1</bitWidth> 640 </field> 641 <field> 642 <name>HRST</name> 643 <description>Hamming Reset. Reset Hamming code ECC generator for next block.</description> 644 <bitOffset>5</bitOffset> 645 <bitWidth>1</bitWidth> 646 <access>write-only</access> 647 <enumeratedValues> 648 <usage>write</usage> 649 <enumeratedValue> 650 <name>reset</name> 651 <description>Starts reset operation.</description> 652 <value>1</value> 653 </enumeratedValue> 654 </enumeratedValues> 655 </field> 656 </fields> 657 </register> 658 <register> 659 <name>DMA_SRC</name> 660 <description>Crypto DMA Source Address.</description> 661 <addressOffset>0x10</addressOffset> 662 <fields> 663 <field> 664 <name>ADDR</name> 665 <description>DMA Source Address.</description> 666 <bitOffset>0</bitOffset> 667 <bitWidth>32</bitWidth> 668 </field> 669 </fields> 670 </register> 671 <register> 672 <name>DMA_DEST</name> 673 <description>Crypto DMA Destination Address.</description> 674 <addressOffset>0x14</addressOffset> 675 <fields> 676 <field> 677 <name>ADDR</name> 678 <description>DMA Destination Address.</description> 679 <bitOffset>0</bitOffset> 680 <bitWidth>32</bitWidth> 681 </field> 682 </fields> 683 </register> 684 <register> 685 <name>DMA_CNT</name> 686 <description>Crypto DMA Byte Count.</description> 687 <addressOffset>0x18</addressOffset> 688 <fields> 689 <field> 690 <name>CNT</name> 691 <description>DMA Byte Address.</description> 692 <bitOffset>0</bitOffset> 693 <bitWidth>32</bitWidth> 694 </field> 695 </fields> 696 </register> 697 <register> 698 <dim>4</dim> 699 <dimIncrement>4</dimIncrement> 700 <name>CRYPTO_DIN[%s]</name> 701 <description>Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.</description> 702 <addressOffset>0x20</addressOffset> 703 <access>write-only</access> 704 <fields> 705 <field> 706 <name>DATA</name> 707 <description>Crypto Data Input. Input can be written to this register instead of using DMA.</description> 708 <bitOffset>0</bitOffset> 709 <bitWidth>32</bitWidth> 710 </field> 711 </fields> 712 </register> 713 <register> 714 <dim>4</dim> 715 <dimIncrement>4</dimIncrement> 716 <name>CRYPTO_DOUT[%s]</name> 717 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.</description> 718 <addressOffset>0x30</addressOffset> 719 <access>read-only</access> 720 <fields> 721 <field> 722 <name>DATA</name> 723 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.</description> 724 <bitOffset>0</bitOffset> 725 <bitWidth>32</bitWidth> 726 </field> 727 </fields> 728 </register> 729 <register> 730 <name>CRC_POLY</name> 731 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 732 <addressOffset>0x40</addressOffset> 733 <resetValue>0xEDB88320</resetValue> 734 <fields> 735 <field> 736 <name>POLY</name> 737 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 738 <bitOffset>0</bitOffset> 739 <bitWidth>32</bitWidth> 740 </field> 741 </fields> 742 </register> 743 <register> 744 <name>CRC_VAL</name> 745 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.</description> 746 <addressOffset>0x44</addressOffset> 747 <resetValue>0xFFFFFFFF</resetValue> 748 <fields> 749 <field> 750 <name>VAL</name> 751 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.</description> 752 <bitOffset>0</bitOffset> 753 <bitWidth>32</bitWidth> 754 </field> 755 </fields> 756 </register> 757 <register> 758 <name>CRC_PRNG</name> 759 <description>Pseudo-Random Number Generator. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled.</description> 760 <addressOffset>0x48</addressOffset> 761 <resetValue>0</resetValue> 762 <fields> 763 <field> 764 <name>PRNG</name> 765 <description>Pseudo-Random Number Generator. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled.</description> 766 <bitOffset>0</bitOffset> 767 <bitWidth>32</bitWidth> 768 </field> 769 </fields> 770 </register> 771 <register> 772 <name>HAM_ECC</name> 773 <description>Hamming ECC Register.</description> 774 <addressOffset>0x4C</addressOffset> 775 <fields> 776 <field> 777 <name>ECC</name> 778 <description>Hamming ECC Value. These bits are the even parity of their corresponding bit groups.</description> 779 <bitOffset>0</bitOffset> 780 <bitWidth>16</bitWidth> 781 </field> 782 <field> 783 <name>PAR</name> 784 <description>Parity. This is the parity of the entire array.</description> 785 <bitOffset>16</bitOffset> 786 <bitWidth>1</bitWidth> 787 <enumeratedValues> 788 <enumeratedValue> 789 <name>even</name> 790 <description>Even.</description> 791 <value>0</value> 792 </enumeratedValue> 793 <enumeratedValue> 794 <name>odd</name> 795 <description>Odd.</description> 796 <value>1</value> 797 </enumeratedValue> 798 </enumeratedValues> 799 </field> 800 </fields> 801 </register> 802 <register> 803 <dim>4</dim> 804 <dimIncrement>4</dimIncrement> 805 <name>CIPHER_INIT[%s]</name> 806 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 807 <addressOffset>0x50</addressOffset> 808 <fields> 809 <field> 810 <name>IVEC</name> 811 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 812 <bitOffset>0</bitOffset> 813 <bitWidth>32</bitWidth> 814 </field> 815 </fields> 816 </register> 817 <register> 818 <dim>8</dim> 819 <dimIncrement>4</dimIncrement> 820 <name>CIPHER_KEY[%s]</name> 821 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.</description> 822 <addressOffset>0x60</addressOffset> 823 <access>write-only</access> 824 <fields> 825 <field> 826 <name>KEY</name> 827 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.</description> 828 <bitOffset>0</bitOffset> 829 <bitWidth>32</bitWidth> 830 </field> 831 </fields> 832 </register> 833 <register> 834 <dim>16</dim> 835 <dimIncrement>4</dimIncrement> 836 <name>HASH_DIGEST[%s]</name> 837 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 838 <addressOffset>0x80</addressOffset> 839 <fields> 840 <field> 841 <name>HASH</name> 842 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 843 <bitOffset>0</bitOffset> 844 <bitWidth>32</bitWidth> 845 </field> 846 </fields> 847 </register> 848 <register> 849 <dim>4</dim> 850 <dimIncrement>4</dimIncrement> 851 <name>HASH_MSG_SZ[%s]</name> 852 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 853 <addressOffset>0xC0</addressOffset> 854 <fields> 855 <field> 856 <name>MSGSZ</name> 857 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 858 <bitOffset>0</bitOffset> 859 <bitWidth>32</bitWidth> 860 </field> 861 </fields> 862 </register> 863 <register> 864 <name>A_LENGTH_0</name> 865 <description>.AAD Length Register 0.</description> 866 <addressOffset>0xD0</addressOffset> 867 <resetValue>0x0</resetValue> 868 <fields> 869 <field> 870 <name>A_LENGTH</name> 871 <description>AAD length in bytes for AES GCM and CCM operations.</description> 872 <bitOffset>0</bitOffset> 873 <bitWidth>32</bitWidth> 874 </field> 875 </fields> 876 </register> 877 <register> 878 <name>A_LENGTH_1</name> 879 <description>.AAD Length Register 1.</description> 880 <addressOffset>0xD4</addressOffset> 881 <resetValue>0x0</resetValue> 882 <fields> 883 <field> 884 <name>A_LENGTH</name> 885 <description>AAD length in bytes for AES GCM and CCM operations.</description> 886 <bitOffset>0</bitOffset> 887 <bitWidth>32</bitWidth> 888 </field> 889 </fields> 890 </register> 891 <register> 892 <name>PLD_LENGTH_0</name> 893 <description>.PLD Length Register 0.</description> 894 <addressOffset>0xD8</addressOffset> 895 <resetValue>0x0</resetValue> 896 <fields> 897 <field> 898 <name>PLD_LENGTH</name> 899 <description>PLD length in bytes for AES GCM and CCM operations.</description> 900 <bitOffset>0</bitOffset> 901 <bitWidth>32</bitWidth> 902 </field> 903 </fields> 904 </register> 905 <register> 906 <name>PLD_LENGTH_1</name> 907 <description>.LENGTH.</description> 908 <addressOffset>0xDC</addressOffset> 909 <resetValue>0x0</resetValue> 910 <fields> 911 <field> 912 <name>PLD_LENGTH</name> 913 <description>PLD length in bytes for AES GCM and CCM operations.</description> 914 <bitOffset>0</bitOffset> 915 <bitWidth>32</bitWidth> 916 </field> 917 </fields> 918 </register> 919 <register> 920 <dim>4</dim> 921 <dimIncrement>4</dimIncrement> 922 <name>TAGMIC[%s]</name> 923 <description>TAG/MIC Registers.</description> 924 <addressOffset>0xE0</addressOffset> 925 <fields> 926 <field> 927 <name>TAGMIC</name> 928 <description>TAG/MIC output for AES GCM and CCM operations.</description> 929 <bitOffset>0</bitOffset> 930 <bitWidth>32</bitWidth> 931 </field> 932 </fields> 933 </register> 934 <register> 935 <name>SCA_CN</name> 936 <description>SCA Control 0 Register.</description> 937 <addressOffset>0x100</addressOffset> 938 <fields> 939 <field> 940 <name>STC</name> 941 <description>Start Calculation.</description> 942 <bitOffset>0</bitOffset> 943 <bitWidth>1</bitWidth> 944 </field> 945 <field> 946 <name>SCAIE</name> 947 <description>SCA Interrupt Enable.</description> 948 <bitOffset>1</bitOffset> 949 <bitWidth>1</bitWidth> 950 <enumeratedValues> 951 <enumeratedValue> 952 <name>disable</name> 953 <description>Disable</description> 954 <value>0</value> 955 </enumeratedValue> 956 <enumeratedValue> 957 <name>enable</name> 958 <description>Enable</description> 959 <value>1</value> 960 </enumeratedValue> 961 </enumeratedValues> 962 </field> 963 <field> 964 <name>ABORT</name> 965 <description>Abort Operation.</description> 966 <bitOffset>2</bitOffset> 967 <bitWidth>1</bitWidth> 968 </field> 969 <field> 970 <name>ERMEM</name> 971 <description>Erase Cryptographic Memory.</description> 972 <bitOffset>4</bitOffset> 973 <bitWidth>1</bitWidth> 974 </field> 975 <field> 976 <name>MANPARAM</name> 977 <description>ECC Parameter Source.</description> 978 <bitOffset>5</bitOffset> 979 <bitWidth>1</bitWidth> 980 </field> 981 <field> 982 <name>HWKEY</name> 983 <description>Hardware Key Select.</description> 984 <bitOffset>6</bitOffset> 985 <bitWidth>1</bitWidth> 986 </field> 987 <field> 988 <name>OPCODE</name> 989 <description>SCA Opcode.</description> 990 <bitOffset>8</bitOffset> 991 <bitWidth>5</bitWidth> 992 </field> 993 <field> 994 <name>MODADDR</name> 995 <description>MODULO Address Offset.</description> 996 <bitOffset>16</bitOffset> 997 <bitWidth>5</bitWidth> 998 </field> 999 <field> 1000 <name>ECCSIZE</name> 1001 <description>ECC Size.</description> 1002 <bitOffset>24</bitOffset> 1003 <bitWidth>2</bitWidth> 1004 </field> 1005 </fields> 1006 </register> 1007 <register> 1008 <name>SCA_ACN</name> 1009 <description>SCA Advanced Control Register.</description> 1010 <addressOffset>0x104</addressOffset> 1011 <fields> 1012 <field> 1013 <name>MAN</name> 1014 <description>SCA Mode.</description> 1015 <bitOffset>0</bitOffset> 1016 <bitWidth>1</bitWidth> 1017 <enumeratedValues> 1018 <enumeratedValue> 1019 <name>auto</name> 1020 <description>Auto Mode</description> 1021 <value>0</value> 1022 </enumeratedValue> 1023 <enumeratedValue> 1024 <name>manual</name> 1025 <description>Manual Mode</description> 1026 <value>1</value> 1027 </enumeratedValue> 1028 </enumeratedValues> 1029 </field> 1030 <field> 1031 <name>AUTOCARRY</name> 1032 <description>Automatically propagate the carry for the next operation.</description> 1033 <bitOffset>1</bitOffset> 1034 <bitWidth>1</bitWidth> 1035 </field> 1036 <field> 1037 <name>PLUSONE</name> 1038 <description>Enable Carry propagation for the next operation.</description> 1039 <bitOffset>2</bitOffset> 1040 <bitWidth>1</bitWidth> 1041 </field> 1042 <field> 1043 <name>RESSELECT</name> 1044 <description>ALU Selection.</description> 1045 <bitOffset>3</bitOffset> 1046 <bitWidth>2</bitWidth> 1047 </field> 1048 <field> 1049 <name>CARRYPOS</name> 1050 <description>To set Carry location.</description> 1051 <bitOffset>8</bitOffset> 1052 <bitWidth>10</bitWidth> 1053 </field> 1054 </fields> 1055 </register> 1056 <register> 1057 <name>SCA_ST</name> 1058 <description>SCA Status Register.</description> 1059 <addressOffset>0x108</addressOffset> 1060 <fields> 1061 <field> 1062 <name>BUSY</name> 1063 <description>SCA Busy.</description> 1064 <bitOffset>0</bitOffset> 1065 <bitWidth>1</bitWidth> 1066 </field> 1067 <field> 1068 <name>SCAIF</name> 1069 <description>SCA Interrupt Flag.</description> 1070 <bitOffset>1</bitOffset> 1071 <bitWidth>1</bitWidth> 1072 </field> 1073 <field> 1074 <name>PVF1</name> 1075 <description>Point 1 Verification Failed.</description> 1076 <bitOffset>2</bitOffset> 1077 <bitWidth>1</bitWidth> 1078 </field> 1079 <field> 1080 <name>PVF2</name> 1081 <description>Point 2 Verification Failed.</description> 1082 <bitOffset>3</bitOffset> 1083 <bitWidth>1</bitWidth> 1084 </field> 1085 <field> 1086 <name>FSMERR</name> 1087 <description>FSM Transition Error.</description> 1088 <bitOffset>4</bitOffset> 1089 <bitWidth>1</bitWidth> 1090 </field> 1091 <field> 1092 <name>COMPERR</name> 1093 <description>EC Computation Error.</description> 1094 <bitOffset>5</bitOffset> 1095 <bitWidth>1</bitWidth> 1096 </field> 1097 <field> 1098 <name>MEMERR</name> 1099 <description>SCA Memory Access Error.</description> 1100 <bitOffset>6</bitOffset> 1101 <bitWidth>1</bitWidth> 1102 </field> 1103 <field> 1104 <name>CARRY</name> 1105 <description>Carry on ongoing operation.</description> 1106 <bitOffset>8</bitOffset> 1107 <bitWidth>1</bitWidth> 1108 </field> 1109 <field> 1110 <name>GTE2I2</name> 1111 <description>Modulo 2x Result.</description> 1112 <bitOffset>9</bitOffset> 1113 <bitWidth>1</bitWidth> 1114 </field> 1115 <field> 1116 <name>ALUNEG1</name> 1117 <description>ALU 2 SubSign of the subtraction result for ALU_2.</description> 1118 <bitOffset>10</bitOffset> 1119 <bitWidth>1</bitWidth> 1120 </field> 1121 <field> 1122 <name>ALUNEG2</name> 1123 <description>ALU 2 SubSign of the subtraction result for ALU_2.</description> 1124 <bitOffset>11</bitOffset> 1125 <bitWidth>1</bitWidth> 1126 </field> 1127 </fields> 1128 </register> 1129 <register> 1130 <name>SCA_PPX_ADDR</name> 1131 <description>PPX Coordinate Data Pointer Register.</description> 1132 <addressOffset>0x10C</addressOffset> 1133 <resetValue>0x0</resetValue> 1134 <fields> 1135 <field> 1136 <name>PPX_ADDR</name> 1137 <description>Point P Coordinate Data Pointer.</description> 1138 <bitOffset>0</bitOffset> 1139 <bitWidth>32</bitWidth> 1140 </field> 1141 </fields> 1142 </register> 1143 <register> 1144 <name>SCA_PPY_ADDR</name> 1145 <description>PPY Coordinate Data Pointer Register.</description> 1146 <addressOffset>0x110</addressOffset> 1147 <resetValue>0x0</resetValue> 1148 <fields> 1149 <field> 1150 <name>PPY_ADDR</name> 1151 <description>Point P Coordinate Data Pointer.</description> 1152 <bitOffset>0</bitOffset> 1153 <bitWidth>32</bitWidth> 1154 </field> 1155 </fields> 1156 </register> 1157 <register> 1158 <name>SCA_PPZ_ADDR</name> 1159 <description>PPZ Coordinate Data Pointer Register.</description> 1160 <addressOffset>0x114</addressOffset> 1161 <resetValue>0x0</resetValue> 1162 <fields> 1163 <field> 1164 <name>PPZ_ADDR</name> 1165 <description>Point P Coordinate Data Pointer.</description> 1166 <bitOffset>0</bitOffset> 1167 <bitWidth>32</bitWidth> 1168 </field> 1169 </fields> 1170 </register> 1171 <register> 1172 <name>SCA_PQX_ADDR</name> 1173 <description>PQX Coordinate Data Pointer Register.</description> 1174 <addressOffset>0x118</addressOffset> 1175 <resetValue>0x0</resetValue> 1176 <fields> 1177 <field> 1178 <name>PQX_ADDR</name> 1179 <description>Point Q Coordinate Data Pointer.</description> 1180 <bitOffset>0</bitOffset> 1181 <bitWidth>32</bitWidth> 1182 </field> 1183 </fields> 1184 </register> 1185 <register> 1186 <name>SCA_PQY_ADDR</name> 1187 <description>PQY Coordinate Data Pointer Register.</description> 1188 <addressOffset>0x11C</addressOffset> 1189 <resetValue>0x0</resetValue> 1190 <fields> 1191 <field> 1192 <name>PQY_ADDR</name> 1193 <description>Point Q Coordinate Data Pointer.</description> 1194 <bitOffset>0</bitOffset> 1195 <bitWidth>32</bitWidth> 1196 </field> 1197 </fields> 1198 </register> 1199 <register> 1200 <name>SCA_PQZ_ADDR</name> 1201 <description>PQZ Coordinate Data Pointer Register.</description> 1202 <addressOffset>0x120</addressOffset> 1203 <resetValue>0x0</resetValue> 1204 <fields> 1205 <field> 1206 <name>PQZ_ADDR</name> 1207 <description>Point Q Coordinate Data Pointer.</description> 1208 <bitOffset>0</bitOffset> 1209 <bitWidth>32</bitWidth> 1210 </field> 1211 </fields> 1212 </register> 1213 <register> 1214 <name>SCA_RDSA_ADDR</name> 1215 <description>SCA RDSA Address Register.</description> 1216 <addressOffset>0x124</addressOffset> 1217 <resetValue>0x0</resetValue> 1218 <fields> 1219 <field> 1220 <name>RDSA_ADDR</name> 1221 <description>The starting address of the R portion for R, S ECDSA signature.</description> 1222 <bitOffset>0</bitOffset> 1223 <bitWidth>32</bitWidth> 1224 </field> 1225 </fields> 1226 </register> 1227 <register> 1228 <name>SCA_RES_ADDR</name> 1229 <description>SCA Result Address Register.</description> 1230 <addressOffset>0x128</addressOffset> 1231 <resetValue>0x0</resetValue> 1232 <fields> 1233 <field> 1234 <name>RES_ADDR</name> 1235 <description>Starting address of result storage.</description> 1236 <bitOffset>0</bitOffset> 1237 <bitWidth>32</bitWidth> 1238 </field> 1239 </fields> 1240 </register> 1241 <register> 1242 <name>SCA_OP_BUFF_ADDR</name> 1243 <description>SCA Operation Buffer Address Register.</description> 1244 <addressOffset>0x12C</addressOffset> 1245 <resetValue>0x0</resetValue> 1246 <fields> 1247 <field> 1248 <name>OPBUFF_ADDR</name> 1249 <description>Starting address of operation buffer.</description> 1250 <bitOffset>0</bitOffset> 1251 <bitWidth>32</bitWidth> 1252 </field> 1253 </fields> 1254 </register> 1255 <register> 1256 <name>SCA_MODDATA</name> 1257 <description>SCA Modulo Data Input Register.</description> 1258 <addressOffset>0x130</addressOffset> 1259 <resetValue>0x0</resetValue> 1260 <fields> 1261 <field> 1262 <name>MODDATA</name> 1263 <description>Used to load the SCA modulo for modular operations.</description> 1264 <bitOffset>0</bitOffset> 1265 <bitWidth>32</bitWidth> 1266 </field> 1267 </fields> 1268 </register> 1269 </registers> 1270 </peripheral> 1271<!--CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.--> 1272 <peripheral> 1273 <name>DMA</name> 1274 <description>DMA Controller Fully programmable, chaining capable DMA channels.</description> 1275 <baseAddress>0x40028000</baseAddress> 1276 <size>32</size> 1277 <addressBlock> 1278 <offset>0x00</offset> 1279 <size>0x1000</size> 1280 <usage>registers</usage> 1281 </addressBlock> 1282 <interrupt> 1283 <name>DMA0</name> 1284 <value>28</value> 1285 </interrupt> 1286 <interrupt> 1287 <name>DMA1</name> 1288 <value>29</value> 1289 </interrupt> 1290 <interrupt> 1291 <name>DMA2</name> 1292 <value>30</value> 1293 </interrupt> 1294 <interrupt> 1295 <name>DMA3</name> 1296 <value>31</value> 1297 </interrupt> 1298 <registers> 1299 <register> 1300 <name>CN</name> 1301 <description>DMA Control Register.</description> 1302 <addressOffset>0x000</addressOffset> 1303 <fields> 1304 <field> 1305 <name>CHIEN</name> 1306 <description>Channel 0-3 Interrupt Enable.</description> 1307 <bitOffset>0</bitOffset> 1308 <bitWidth>4</bitWidth> 1309 <enumeratedValues> 1310 <enumeratedValue> 1311 <name>dis</name> 1312 <description>Disable.</description> 1313 <value>0</value> 1314 </enumeratedValue> 1315 <enumeratedValue> 1316 <name>en</name> 1317 <description>Enable.</description> 1318 <value>1</value> 1319 </enumeratedValue> 1320 </enumeratedValues> 1321 </field> 1322 </fields> 1323 </register> 1324 <register> 1325 <name>INTR</name> 1326 <description>DMA Interrupt Register.</description> 1327 <addressOffset>0x004</addressOffset> 1328 <access>read-only</access> 1329 <fields> 1330 <field> 1331 <name>IPEND</name> 1332 <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description> 1333 <bitOffset>0</bitOffset> 1334 <bitWidth>4</bitWidth> 1335 <enumeratedValues> 1336 <enumeratedValue> 1337 <name>inactive</name> 1338 <description>No interrupt is pending.</description> 1339 <value>0</value> 1340 </enumeratedValue> 1341 <enumeratedValue> 1342 <name>pending</name> 1343 <description>An interrupt is pending.</description> 1344 <value>1</value> 1345 </enumeratedValue> 1346 </enumeratedValues> 1347 </field> 1348 </fields> 1349 </register> 1350 <cluster> 1351 <dim>8</dim> 1352 <dimIncrement>0x20</dimIncrement> 1353 <name>CH[%s]</name> 1354 <description>DMA Channel registers.</description> 1355 <headerStructName>dma_ch</headerStructName> 1356 <addressOffset>0x100</addressOffset> 1357 <access>read-write</access> 1358 <register> 1359 <name>CFG</name> 1360 <description>DMA Channel Configuration Register.</description> 1361 <addressOffset>0x000</addressOffset> 1362 <fields> 1363 <field> 1364 <name>CHIEN</name> 1365 <description>Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description> 1366 <bitOffset>0</bitOffset> 1367 <bitWidth>1</bitWidth> 1368 <enumeratedValues> 1369 <enumeratedValue> 1370 <name>dis</name> 1371 <description>Disable.</description> 1372 <value>0</value> 1373 </enumeratedValue> 1374 <enumeratedValue> 1375 <name>en</name> 1376 <description>Enable.</description> 1377 <value>1</value> 1378 </enumeratedValue> 1379 </enumeratedValues> 1380 </field> 1381 <field> 1382 <name>RLDEN</name> 1383 <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description> 1384 <bitOffset>1</bitOffset> 1385 <bitWidth>1</bitWidth> 1386 <enumeratedValues> 1387 <enumeratedValue> 1388 <name>dis</name> 1389 <description>Disable.</description> 1390 <value>0</value> 1391 </enumeratedValue> 1392 <enumeratedValue> 1393 <name>en</name> 1394 <description>Enable.</description> 1395 <value>1</value> 1396 </enumeratedValue> 1397 </enumeratedValues> 1398 </field> 1399 <field> 1400 <name>PRI</name> 1401 <description>DMA Priority.</description> 1402 <bitOffset>2</bitOffset> 1403 <bitWidth>2</bitWidth> 1404 <enumeratedValues> 1405 <enumeratedValue> 1406 <name>high</name> 1407 <description>Highest Priority.</description> 1408 <value>0</value> 1409 </enumeratedValue> 1410 <enumeratedValue> 1411 <name>medHigh</name> 1412 <description>Medium High Priority.</description> 1413 <value>1</value> 1414 </enumeratedValue> 1415 <enumeratedValue> 1416 <name>medLow</name> 1417 <description>Medium Low Priority.</description> 1418 <value>2</value> 1419 </enumeratedValue> 1420 <enumeratedValue> 1421 <name>low</name> 1422 <description>Lowest Priority.</description> 1423 <value>3</value> 1424 </enumeratedValue> 1425 </enumeratedValues> 1426 </field> 1427 <field> 1428 <name>REQSEL</name> 1429 <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description> 1430 <bitOffset>4</bitOffset> 1431 <bitWidth>6</bitWidth> 1432 <enumeratedValues> 1433 <enumeratedValue> 1434 <name>MEMTOMEM</name> 1435 <description>Memory To Memory</description> 1436 <value>0x00</value> 1437 </enumeratedValue> 1438 <enumeratedValue> 1439 <name>SPI0RX</name> 1440 <description>SPI0 RX</description> 1441 <value>0x01</value> 1442 </enumeratedValue> 1443 <enumeratedValue> 1444 <name>SPI1RX</name> 1445 <description>SPI1 RX</description> 1446 <value>0x02</value> 1447 </enumeratedValue> 1448 <enumeratedValue> 1449 <name>I2C0RX</name> 1450 <description>I2C0 RX</description> 1451 <value>0x07</value> 1452 </enumeratedValue> 1453 <enumeratedValue> 1454 <name>UART0RX</name> 1455 <description>UART0 RX</description> 1456 <value>0x1C</value> 1457 </enumeratedValue> 1458 <enumeratedValue> 1459 <name>SPI0TX</name> 1460 <description>SPI0 TX</description> 1461 <value>0x21</value> 1462 </enumeratedValue> 1463 <enumeratedValue> 1464 <name>SPI1TX</name> 1465 <description>SPI1 TX</description> 1466 <value>0x22</value> 1467 </enumeratedValue> 1468 <enumeratedValue> 1469 <name>I2C0TX</name> 1470 <description>I2C0 TX</description> 1471 <value>0x27</value> 1472 </enumeratedValue> 1473 <enumeratedValue> 1474 <name>UART0TX</name> 1475 <description>UART0 TX</description> 1476 <value>0x3C</value> 1477 </enumeratedValue> 1478 </enumeratedValues> 1479 </field> 1480 <field> 1481 <name>REQWAIT</name> 1482 <description>Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.</description> 1483 <bitOffset>10</bitOffset> 1484 <bitWidth>1</bitWidth> 1485 <enumeratedValues> 1486 <enumeratedValue> 1487 <name>dis</name> 1488 <description>Disable.</description> 1489 <value>0</value> 1490 </enumeratedValue> 1491 <enumeratedValue> 1492 <name>en</name> 1493 <description>Enable.</description> 1494 <value>1</value> 1495 </enumeratedValue> 1496 </enumeratedValues> 1497 </field> 1498 <field> 1499 <name>TOSEL</name> 1500 <description>Timeout Period Select.</description> 1501 <bitOffset>11</bitOffset> 1502 <bitWidth>3</bitWidth> 1503 <enumeratedValues> 1504 <enumeratedValue> 1505 <name>to4</name> 1506 <description>Timeout of 3 to 4 prescale clocks.</description> 1507 <value>0</value> 1508 </enumeratedValue> 1509 <enumeratedValue> 1510 <name>to8</name> 1511 <description>Timeout of 7 to 8 prescale clocks.</description> 1512 <value>1</value> 1513 </enumeratedValue> 1514 <enumeratedValue> 1515 <name>to16</name> 1516 <description>Timeout of 15 to 16 prescale clocks.</description> 1517 <value>2</value> 1518 </enumeratedValue> 1519 <enumeratedValue> 1520 <name>to32</name> 1521 <description>Timeout of 31 to 32 prescale clocks.</description> 1522 <value>3</value> 1523 </enumeratedValue> 1524 <enumeratedValue> 1525 <name>to64</name> 1526 <description>Timeout of 63 to 64 prescale clocks.</description> 1527 <value>4</value> 1528 </enumeratedValue> 1529 <enumeratedValue> 1530 <name>to128</name> 1531 <description>Timeout of 127 to 128 prescale clocks.</description> 1532 <value>5</value> 1533 </enumeratedValue> 1534 <enumeratedValue> 1535 <name>to256</name> 1536 <description>Timeout of 255 to 256 prescale clocks.</description> 1537 <value>6</value> 1538 </enumeratedValue> 1539 <enumeratedValue> 1540 <name>to512</name> 1541 <description>Timeout of 511 to 512 prescale clocks.</description> 1542 <value>7</value> 1543 </enumeratedValue> 1544 </enumeratedValues> 1545 </field> 1546 <field> 1547 <name>PSSEL</name> 1548 <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description> 1549 <bitOffset>14</bitOffset> 1550 <bitWidth>2</bitWidth> 1551 <enumeratedValues> 1552 <enumeratedValue> 1553 <name>dis</name> 1554 <description>Disable timer.</description> 1555 <value>0</value> 1556 </enumeratedValue> 1557 <enumeratedValue> 1558 <name>div256</name> 1559 <description>hclk / 256.</description> 1560 <value>1</value> 1561 </enumeratedValue> 1562 <enumeratedValue> 1563 <name>div64k</name> 1564 <description>hclk / 64k.</description> 1565 <value>2</value> 1566 </enumeratedValue> 1567 <enumeratedValue> 1568 <name>div16M</name> 1569 <description>hclk / 16M.</description> 1570 <value>3</value> 1571 </enumeratedValue> 1572 </enumeratedValues> 1573 </field> 1574 <field> 1575 <name>SRCWD</name> 1576 <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description> 1577 <bitOffset>16</bitOffset> 1578 <bitWidth>2</bitWidth> 1579 <enumeratedValues> 1580 <enumeratedValue> 1581 <name>byte</name> 1582 <description>Byte.</description> 1583 <value>0</value> 1584 </enumeratedValue> 1585 <enumeratedValue> 1586 <name>halfWord</name> 1587 <description>Halfword.</description> 1588 <value>1</value> 1589 </enumeratedValue> 1590 <enumeratedValue> 1591 <name>word</name> 1592 <description>Word.</description> 1593 <value>2</value> 1594 </enumeratedValue> 1595 </enumeratedValues> 1596 </field> 1597 <field> 1598 <name>SRCINC</name> 1599 <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description> 1600 <bitOffset>18</bitOffset> 1601 <bitWidth>1</bitWidth> 1602 <enumeratedValues> 1603 <enumeratedValue> 1604 <name>dis</name> 1605 <description>Disable.</description> 1606 <value>0</value> 1607 </enumeratedValue> 1608 <enumeratedValue> 1609 <name>en</name> 1610 <description>Enable.</description> 1611 <value>1</value> 1612 </enumeratedValue> 1613 </enumeratedValues> 1614 </field> 1615 <field> 1616 <name>DSTWD</name> 1617 <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description> 1618 <bitOffset>20</bitOffset> 1619 <bitWidth>2</bitWidth> 1620 <enumeratedValues> 1621 <enumeratedValue> 1622 <name>byte</name> 1623 <description>Byte.</description> 1624 <value>0</value> 1625 </enumeratedValue> 1626 <enumeratedValue> 1627 <name>halfWord</name> 1628 <description>Halfword.</description> 1629 <value>1</value> 1630 </enumeratedValue> 1631 <enumeratedValue> 1632 <name>word</name> 1633 <description>Word.</description> 1634 <value>2</value> 1635 </enumeratedValue> 1636 </enumeratedValues> 1637 </field> 1638 <field> 1639 <name>DSTINC</name> 1640 <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description> 1641 <bitOffset>22</bitOffset> 1642 <bitWidth>1</bitWidth> 1643 <enumeratedValues> 1644 <enumeratedValue> 1645 <name>dis</name> 1646 <description>Disable.</description> 1647 <value>0</value> 1648 </enumeratedValue> 1649 <enumeratedValue> 1650 <name>en</name> 1651 <description>Enable.</description> 1652 <value>1</value> 1653 </enumeratedValue> 1654 </enumeratedValues> 1655 </field> 1656 <field> 1657 <name>BRST</name> 1658 <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.</description> 1659 <bitOffset>24</bitOffset> 1660 <bitWidth>5</bitWidth> 1661 </field> 1662 <field> 1663 <name>CHDIEN</name> 1664 <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description> 1665 <bitOffset>30</bitOffset> 1666 <bitWidth>1</bitWidth> 1667 <enumeratedValues> 1668 <enumeratedValue> 1669 <name>dis</name> 1670 <description>Disable.</description> 1671 <value>0</value> 1672 </enumeratedValue> 1673 <enumeratedValue> 1674 <name>en</name> 1675 <description>Enable.</description> 1676 <value>1</value> 1677 </enumeratedValue> 1678 </enumeratedValues> 1679 </field> 1680 <field> 1681 <name>CTZIEN</name> 1682 <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description> 1683 <bitOffset>31</bitOffset> 1684 <bitWidth>1</bitWidth> 1685 <enumeratedValues> 1686 <enumeratedValue> 1687 <name>dis</name> 1688 <description>Disable.</description> 1689 <value>0</value> 1690 </enumeratedValue> 1691 <enumeratedValue> 1692 <name>en</name> 1693 <description>Enable.</description> 1694 <value>1</value> 1695 </enumeratedValue> 1696 </enumeratedValues> 1697 </field> 1698 </fields> 1699 </register> 1700 <register> 1701 <name>ST</name> 1702 <description>DMA Channel Status Register.</description> 1703 <addressOffset>0x004</addressOffset> 1704 <fields> 1705 <field> 1706 <name>CH_ST</name> 1707 <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description> 1708 <bitOffset>0</bitOffset> 1709 <bitWidth>1</bitWidth> 1710 <access>read-only</access> 1711 <enumeratedValues> 1712 <enumeratedValue> 1713 <name>dis</name> 1714 <description>Disable.</description> 1715 <value>0</value> 1716 </enumeratedValue> 1717 <enumeratedValue> 1718 <name>en</name> 1719 <description>Enable.</description> 1720 <value>1</value> 1721 </enumeratedValue> 1722 </enumeratedValues> 1723 </field> 1724 <field> 1725 <name>IPEND</name> 1726 <description>Channel Interrupt.</description> 1727 <bitOffset>1</bitOffset> 1728 <bitWidth>1</bitWidth> 1729 <access>read-only</access> 1730 <enumeratedValues> 1731 <enumeratedValue> 1732 <name>inactive</name> 1733 <description>No interrupt is pending.</description> 1734 <value>0</value> 1735 </enumeratedValue> 1736 <enumeratedValue> 1737 <name>pending</name> 1738 <description>An interrupt is pending.</description> 1739 <value>1</value> 1740 </enumeratedValue> 1741 </enumeratedValues> 1742 </field> 1743 <field> 1744 <name>CTZ_ST</name> 1745 <description>Count-to-Zero (CTZ) Event Interrupt Flag</description> 1746 <bitOffset>2</bitOffset> 1747 <bitWidth>1</bitWidth> 1748 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1749 </field> 1750 <field> 1751 <name>RLD_ST</name> 1752 <description>Reload Event Interrupt Flag.</description> 1753 <bitOffset>3</bitOffset> 1754 <bitWidth>1</bitWidth> 1755 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1756 </field> 1757 <field> 1758 <name>BUS_ERR</name> 1759 <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description> 1760 <bitOffset>4</bitOffset> 1761 <bitWidth>1</bitWidth> 1762 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1763 </field> 1764 <field> 1765 <name>TO_ST</name> 1766 <description>Time-Out Event Interrupt Flag.</description> 1767 <bitOffset>6</bitOffset> 1768 <bitWidth>1</bitWidth> 1769 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1770 </field> 1771 </fields> 1772 </register> 1773 <register> 1774 <name>SRC</name> 1775 <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description> 1776 <addressOffset>0x008</addressOffset> 1777 <fields> 1778 <field> 1779 <name>SRC</name> 1780 <bitOffset>0</bitOffset> 1781 <bitWidth>32</bitWidth> 1782 </field> 1783 </fields> 1784 </register> 1785 <register> 1786 <name>DST</name> 1787 <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description> 1788 <addressOffset>0x00C</addressOffset> 1789 <fields> 1790 <field> 1791 <name>DST</name> 1792 <bitOffset>0</bitOffset> 1793 <bitWidth>32</bitWidth> 1794 </field> 1795 </fields> 1796 </register> 1797 <register> 1798 <name>CNT</name> 1799 <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description> 1800 <addressOffset>0x010</addressOffset> 1801 <fields> 1802 <field> 1803 <name>CNT</name> 1804 <description>DMA Counter.</description> 1805 <bitOffset>0</bitOffset> 1806 <bitWidth>24</bitWidth> 1807 </field> 1808 </fields> 1809 </register> 1810 <register> 1811 <name>SRC_RLD</name> 1812 <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description> 1813 <addressOffset>0x014</addressOffset> 1814 <fields> 1815 <field> 1816 <name>SRC_RLD</name> 1817 <description>Source Address Reload Value.</description> 1818 <bitOffset>0</bitOffset> 1819 <bitWidth>31</bitWidth> 1820 </field> 1821 </fields> 1822 </register> 1823 <register> 1824 <name>DST_RLD</name> 1825 <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description> 1826 <addressOffset>0x018</addressOffset> 1827 <fields> 1828 <field> 1829 <name>DST_RLD</name> 1830 <description>Destination Address Reload Value.</description> 1831 <bitOffset>0</bitOffset> 1832 <bitWidth>31</bitWidth> 1833 </field> 1834 </fields> 1835 </register> 1836 <register> 1837 <name>CNT_RLD</name> 1838 <description>DMA Channel Count Reload Register.</description> 1839 <addressOffset>0x01C</addressOffset> 1840 <fields> 1841 <field> 1842 <name>CNT_RLD</name> 1843 <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description> 1844 <bitOffset>0</bitOffset> 1845 <bitWidth>24</bitWidth> 1846 </field> 1847 <field> 1848 <name>RLDEN</name> 1849 <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description> 1850 <bitOffset>31</bitOffset> 1851 <bitWidth>1</bitWidth> 1852 <enumeratedValues> 1853 <enumeratedValue> 1854 <name>dis</name> 1855 <description>Disable.</description> 1856 <value>0</value> 1857 </enumeratedValue> 1858 <enumeratedValue> 1859 <name>en</name> 1860 <description>Enable.</description> 1861 <value>1</value> 1862 </enumeratedValue> 1863 </enumeratedValues> 1864 </field> 1865 </fields> 1866 </register> 1867 </cluster> 1868 </registers> 1869 </peripheral> 1870<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.--> 1871 <peripheral> 1872 <name>FCR</name> 1873 <description>Function Control Register.</description> 1874 <baseAddress>0x40000800</baseAddress> 1875 <addressBlock> 1876 <offset>0x00</offset> 1877 <size>0x400</size> 1878 <usage>registers</usage> 1879 </addressBlock> 1880 <registers> 1881 <register> 1882 <name>FCTRL0</name> 1883 <description>Register 0.</description> 1884 <addressOffset>0x00</addressOffset> 1885 <access>read-write</access> 1886 <fields> 1887 <field> 1888 <name>I2C0_SDA_FILTER_EN</name> 1889 <description>I2C0 SDA Glitch Filter Enable.</description> 1890 <bitOffset>20</bitOffset> 1891 <bitWidth>1</bitWidth> 1892 <enumeratedValues> 1893 <enumeratedValue> 1894 <name>dis</name> 1895 <description>Filter disabled.</description> 1896 <value>0</value> 1897 </enumeratedValue> 1898 <enumeratedValue> 1899 <name>en</name> 1900 <description>Filter enabled.</description> 1901 <value>1</value> 1902 </enumeratedValue> 1903 </enumeratedValues> 1904 </field> 1905 <field> 1906 <name>I2C0_SCL_FILTER_EN</name> 1907 <description>I2C0 SCL Glitch Filter Enable.</description> 1908 <bitOffset>21</bitOffset> 1909 <bitWidth>1</bitWidth> 1910 <enumeratedValues> 1911 <enumeratedValue> 1912 <name>dis</name> 1913 <description>Filter disabled.</description> 1914 <value>0</value> 1915 </enumeratedValue> 1916 <enumeratedValue> 1917 <name>en</name> 1918 <description>Filter enabled.</description> 1919 <value>1</value> 1920 </enumeratedValue> 1921 </enumeratedValues> 1922 </field> 1923 </fields> 1924 </register> 1925 </registers> 1926 </peripheral> 1927<!--FCR Function Control Register.--> 1928 <peripheral> 1929 <name>FLC</name> 1930 <description>Flash Memory Control.</description> 1931 <prependToName>FLSH_</prependToName> 1932 <baseAddress>0x40029000</baseAddress> 1933 <addressBlock> 1934 <offset>0x00</offset> 1935 <size>0x1000</size> 1936 <usage>registers</usage> 1937 </addressBlock> 1938 <interrupt> 1939 <name>Flash_Controller</name> 1940 <description>Flash Controller interrupt.</description> 1941 <value>23</value> 1942 </interrupt> 1943 <registers> 1944 <register> 1945 <name>FLSH_ADDR</name> 1946 <description>Flash Write Address.</description> 1947 <addressOffset>0x00</addressOffset> 1948 <fields> 1949 <field> 1950 <name>ADDR</name> 1951 <description>Address for next operation.</description> 1952 <bitOffset>0</bitOffset> 1953 <bitWidth>32</bitWidth> 1954 </field> 1955 </fields> 1956 </register> 1957 <register> 1958 <name>FLSH_CLKDIV</name> 1959 <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description> 1960 <addressOffset>0x04</addressOffset> 1961 <resetValue>0x00000064</resetValue> 1962 <fields> 1963 <field> 1964 <name>CLKDIV</name> 1965 <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description> 1966 <bitOffset>0</bitOffset> 1967 <bitWidth>8</bitWidth> 1968 </field> 1969 </fields> 1970 </register> 1971 <register> 1972 <name>FLSH_CN</name> 1973 <description>Flash Control Register.</description> 1974 <addressOffset>0x08</addressOffset> 1975 <fields> 1976 <field> 1977 <name>WR</name> 1978 <description>Write. This bit is automatically cleared after the operation.</description> 1979 <bitOffset>0</bitOffset> 1980 <bitWidth>1</bitWidth> 1981 <enumeratedValues> 1982 <enumeratedValue> 1983 <name>complete</name> 1984 <description>No operation/complete.</description> 1985 <value>0</value> 1986 </enumeratedValue> 1987 <enumeratedValue> 1988 <name>start</name> 1989 <description>Start operation.</description> 1990 <value>1</value> 1991 </enumeratedValue> 1992 </enumeratedValues> 1993 </field> 1994 <field derivedFrom="WR"> 1995 <name>ME</name> 1996 <description>Mass Erase. This bit is automatically cleared after the operation.</description> 1997 <bitOffset>1</bitOffset> 1998 <bitWidth>1</bitWidth> 1999 </field> 2000 <field derivedFrom="WR"> 2001 <name>PGE</name> 2002 <description>Page Erase. This bit is automatically cleared after the operation.</description> 2003 <bitOffset>2</bitOffset> 2004 <bitWidth>1</bitWidth> 2005 </field> 2006 <field> 2007 <name>ERASE_CODE</name> 2008 <description>Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description> 2009 <bitOffset>8</bitOffset> 2010 <bitWidth>8</bitWidth> 2011 <enumeratedValues> 2012 <enumeratedValue> 2013 <name>nop</name> 2014 <description>No operation.</description> 2015 <value>0</value> 2016 </enumeratedValue> 2017 <enumeratedValue> 2018 <name>erasePage</name> 2019 <description>Enable Page Erase.</description> 2020 <value>0x55</value> 2021 </enumeratedValue> 2022 <enumeratedValue> 2023 <name>eraseAll</name> 2024 <description>Enable Mass Erase. The debug port must be enabled.</description> 2025 <value>0xAA</value> 2026 </enumeratedValue> 2027 </enumeratedValues> 2028 </field> 2029 <field> 2030 <name>PEND</name> 2031 <description>Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description> 2032 <bitOffset>24</bitOffset> 2033 <bitWidth>1</bitWidth> 2034 <access>read-only</access> 2035 <enumeratedValues> 2036 <enumeratedValue> 2037 <name>idle</name> 2038 <description>Idle.</description> 2039 <value>0</value> 2040 </enumeratedValue> 2041 <enumeratedValue> 2042 <name>busy</name> 2043 <description>Busy.</description> 2044 <value>1</value> 2045 </enumeratedValue> 2046 </enumeratedValues> 2047 </field> 2048 <field> 2049 <name>UNLOCK</name> 2050 <description>Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description> 2051 <bitOffset>28</bitOffset> 2052 <bitWidth>4</bitWidth> 2053 <enumeratedValues> 2054 <enumeratedValue> 2055 <name>unlocked</name> 2056 <description>Flash Unlocked.</description> 2057 <value>2</value> 2058 </enumeratedValue> 2059 <enumeratedValue> 2060 <name>locked</name> 2061 <description>Flash Locked.</description> 2062 <value>3</value> 2063 </enumeratedValue> 2064 </enumeratedValues> 2065 </field> 2066 </fields> 2067 </register> 2068 <register> 2069 <name>FLSH_INT</name> 2070 <description>Flash Interrupt Register.</description> 2071 <addressOffset>0x24</addressOffset> 2072 <fields> 2073 <field> 2074 <name>DONE</name> 2075 <description>Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.</description> 2076 <bitOffset>0</bitOffset> 2077 <bitWidth>1</bitWidth> 2078 <enumeratedValues> 2079 <enumeratedValue> 2080 <name>inactive</name> 2081 <description>No interrupt is pending.</description> 2082 <value>0</value> 2083 </enumeratedValue> 2084 <enumeratedValue> 2085 <name>pending</name> 2086 <description>An interrupt is pending.</description> 2087 <value>1</value> 2088 </enumeratedValue> 2089 </enumeratedValues> 2090 </field> 2091 <field> 2092 <name>AF</name> 2093 <description>Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description> 2094 <bitOffset>1</bitOffset> 2095 <bitWidth>1</bitWidth> 2096 <enumeratedValues> 2097 <enumeratedValue> 2098 <name>noError</name> 2099 <description>No Failure.</description> 2100 <value>0</value> 2101 </enumeratedValue> 2102 <enumeratedValue> 2103 <name>error</name> 2104 <description>Failure occurs.</description> 2105 <value>1</value> 2106 </enumeratedValue> 2107 </enumeratedValues> 2108 </field> 2109 <field> 2110 <name>DONEIE</name> 2111 <description>Flash Done Interrupt Enable.</description> 2112 <bitOffset>8</bitOffset> 2113 <bitWidth>1</bitWidth> 2114 <enumeratedValues> 2115 <enumeratedValue> 2116 <name>disable</name> 2117 <description>Disable.</description> 2118 <value>0</value> 2119 </enumeratedValue> 2120 <enumeratedValue> 2121 <name>enable</name> 2122 <description>Enable.</description> 2123 <value>1</value> 2124 </enumeratedValue> 2125 </enumeratedValues> 2126 </field> 2127 <field derivedFrom="DONEIE"> 2128 <name>AFIE</name> 2129 <bitOffset>9</bitOffset> 2130 <bitWidth>1</bitWidth> 2131 </field> 2132 </fields> 2133 </register> 2134 <register> 2135 <dim>4</dim> 2136 <dimIncrement>4</dimIncrement> 2137 <name>FLSH_DATA[%s]</name> 2138 <description>Flash Write Data.</description> 2139 <addressOffset>0x30</addressOffset> 2140 <fields> 2141 <field> 2142 <name>DATA</name> 2143 <description>Data next operation.</description> 2144 <bitOffset>0</bitOffset> 2145 <bitWidth>32</bitWidth> 2146 </field> 2147 </fields> 2148 </register> 2149 <register> 2150 <name>ACNTL</name> 2151 <description>Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: 2152 pflc-actrl = 0x3a7f5ca3; 2153 pflc-actrl = 0xa1e34f20; 2154 pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.</description> 2155 <addressOffset>0x40</addressOffset> 2156 <access>write-only</access> 2157 <fields> 2158 <field> 2159 <name>ADATA</name> 2160 <description>Access control.</description> 2161 <bitOffset>0</bitOffset> 2162 <bitWidth>32</bitWidth> 2163 </field> 2164 </fields> 2165 </register> 2166 </registers> 2167 </peripheral> 2168<!--FLC Flash Memory Control.--> 2169 <peripheral> 2170 <name>GCR</name> 2171 <description>Global Control Registers.</description> 2172 <baseAddress>0x40000000</baseAddress> 2173 <addressBlock> 2174 <offset>0</offset> 2175 <size>0x400</size> 2176 <usage>registers</usage> 2177 </addressBlock> 2178 <registers> 2179 <register> 2180 <name>SYSCTRL</name> 2181 <description>System Control.</description> 2182 <addressOffset>0x00</addressOffset> 2183 <resetMask>0xFFFFFFFE</resetMask> 2184 <fields> 2185 <field> 2186 <name>BSTAPEN</name> 2187 <description>Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.</description> 2188 <bitOffset>0</bitOffset> 2189 <bitWidth>1</bitWidth> 2190 <enumeratedValues> 2191 <enumeratedValue> 2192 <name>dis</name> 2193 <description>Boundary Scan TAP port disabled.</description> 2194 <value>0</value> 2195 </enumeratedValue> 2196 <enumeratedValue> 2197 <name>en</name> 2198 <description>Boundary Scan TAP port enabled.</description> 2199 <value>1</value> 2200 </enumeratedValue> 2201 </enumeratedValues> 2202 </field> 2203 <field> 2204 <name>FLASH0_PAGE_FLIP</name> 2205 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 2206 <bitOffset>4</bitOffset> 2207 <bitWidth>1</bitWidth> 2208 <enumeratedValues> 2209 <enumeratedValue> 2210 <name>normal</name> 2211 <description>Physical layout matches logical layout.</description> 2212 <value>0</value> 2213 </enumeratedValue> 2214 <enumeratedValue> 2215 <name>swapped</name> 2216 <description>Bottom half mapped to logical top half and vice versa.</description> 2217 <value>1</value> 2218 </enumeratedValue> 2219 </enumeratedValues> 2220 </field> 2221 <field> 2222 <name>ICC0_FLUSH</name> 2223 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 2224 <bitOffset>6</bitOffset> 2225 <bitWidth>1</bitWidth> 2226 <enumeratedValues> 2227 <enumeratedValue> 2228 <name>normal</name> 2229 <description>Normal Code Cache Operation</description> 2230 <value>0</value> 2231 </enumeratedValue> 2232 <enumeratedValue> 2233 <name>flush</name> 2234 <description>Code Caches and CPU instruction buffer are flushed </description> 2235 <value>1</value> 2236 </enumeratedValue> 2237 </enumeratedValues> 2238 </field> 2239 <field> 2240 <name>CCHK</name> 2241 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 2242 <bitOffset>13</bitOffset> 2243 <bitWidth>1</bitWidth> 2244 <enumeratedValues> 2245 <enumeratedValue> 2246 <name>complete</name> 2247 <description>No operation/complete.</description> 2248 <value>0</value> 2249 </enumeratedValue> 2250 <enumeratedValue> 2251 <name>start</name> 2252 <description>Start operation.</description> 2253 <value>1</value> 2254 </enumeratedValue> 2255 </enumeratedValues> 2256 </field> 2257 <field> 2258 <name>CHKRES</name> 2259 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 2260 <bitOffset>15</bitOffset> 2261 <bitWidth>1</bitWidth> 2262 <enumeratedValues> 2263 <enumeratedValue> 2264 <name>pass</name> 2265 <description>ROM Checksum Correct.</description> 2266 <value>0</value> 2267 </enumeratedValue> 2268 <enumeratedValue> 2269 <name>fail</name> 2270 <description>ROM Checksum Fail.</description> 2271 <value>1</value> 2272 </enumeratedValue> 2273 </enumeratedValues> 2274 </field> 2275 <field> 2276 <name>MDU_KEYSZ</name> 2277 <description>MDU Key Size. This register defines the size of AES key that is used in the memory protection logic.</description> 2278 <bitOffset>21</bitOffset> 2279 <bitWidth>1</bitWidth> 2280 <enumeratedValues> 2281 <enumeratedValue> 2282 <name>128b</name> 2283 <description>128 bit key</description> 2284 <value>0</value> 2285 </enumeratedValue> 2286 <enumeratedValue> 2287 <name>256b</name> 2288 <description>256 bit key</description> 2289 <value>1</value> 2290 </enumeratedValue> 2291 </enumeratedValues> 2292 </field> 2293 </fields> 2294 </register> 2295 <register> 2296 <name>RST0</name> 2297 <description>Reset.</description> 2298 <addressOffset>0x04</addressOffset> 2299 <fields> 2300 <field> 2301 <name>DMA</name> 2302 <description>DMA Reset.</description> 2303 <bitOffset>0</bitOffset> 2304 <bitWidth>1</bitWidth> 2305 </field> 2306 <field derivedFrom="DMA"> 2307 <name>WDT0</name> 2308 <description>Watchdog Timer Reset.</description> 2309 <bitOffset>1</bitOffset> 2310 <bitWidth>1</bitWidth> 2311 </field> 2312 <field derivedFrom="DMA"> 2313 <name>GPIO0</name> 2314 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 2315 <bitOffset>2</bitOffset> 2316 <bitWidth>1</bitWidth> 2317 </field> 2318 <field derivedFrom="DMA"> 2319 <name>GPIO1</name> 2320 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 2321 <bitOffset>3</bitOffset> 2322 <bitWidth>1</bitWidth> 2323 </field> 2324 <field derivedFrom="DMA"> 2325 <name>TMR0</name> 2326 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 2327 <bitOffset>5</bitOffset> 2328 <bitWidth>1</bitWidth> 2329 </field> 2330 <field derivedFrom="DMA"> 2331 <name>TMR1</name> 2332 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 2333 <bitOffset>6</bitOffset> 2334 <bitWidth>1</bitWidth> 2335 </field> 2336 <field derivedFrom="DMA"> 2337 <name>TMR2</name> 2338 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 2339 <bitOffset>7</bitOffset> 2340 <bitWidth>1</bitWidth> 2341 </field> 2342 <field derivedFrom="DMA"> 2343 <name>TMR3</name> 2344 <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 2345 <bitOffset>8</bitOffset> 2346 <bitWidth>1</bitWidth> 2347 </field> 2348 <field derivedFrom="DMA"> 2349 <name>UART0</name> 2350 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 2351 <bitOffset>11</bitOffset> 2352 <bitWidth>1</bitWidth> 2353 </field> 2354 <field derivedFrom="DMA"> 2355 <name>SPI0</name> 2356 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 2357 <bitOffset>13</bitOffset> 2358 <bitWidth>1</bitWidth> 2359 </field> 2360 <field derivedFrom="DMA"> 2361 <name>SPI1</name> 2362 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 2363 <bitOffset>14</bitOffset> 2364 <bitWidth>1</bitWidth> 2365 </field> 2366 <field derivedFrom="DMA"> 2367 <name>I2C0</name> 2368 <description>I2C0 Reset.</description> 2369 <bitOffset>16</bitOffset> 2370 <bitWidth>1</bitWidth> 2371 </field> 2372 <field derivedFrom="DMA"> 2373 <name>CRYPTO</name> 2374 <description>Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.</description> 2375 <bitOffset>18</bitOffset> 2376 <bitWidth>1</bitWidth> 2377 </field> 2378 <field derivedFrom="DMA"> 2379 <name>SOFT</name> 2380 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 2381 <bitOffset>29</bitOffset> 2382 <bitWidth>1</bitWidth> 2383 </field> 2384 <field derivedFrom="DMA"> 2385 <name>PERIPH</name> 2386 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 2387 <bitOffset>30</bitOffset> 2388 <bitWidth>1</bitWidth> 2389 </field> 2390 <field derivedFrom="DMA"> 2391 <name>SYS</name> 2392 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 2393 <bitOffset>31</bitOffset> 2394 <bitWidth>1</bitWidth> 2395 </field> 2396 </fields> 2397 </register> 2398 <register> 2399 <name>CLKCTRL</name> 2400 <description>Clock Control.</description> 2401 <addressOffset>0x08</addressOffset> 2402 <resetValue>0x00000008</resetValue> 2403 <fields> 2404 <field> 2405 <name>SYSCLK_DIV</name> 2406 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 2407 <bitOffset>6</bitOffset> 2408 <bitWidth>3</bitWidth> 2409 <enumeratedValues> 2410 <enumeratedValue> 2411 <name>div1</name> 2412 <description>Divide by 1.</description> 2413 <value>0</value> 2414 </enumeratedValue> 2415 <enumeratedValue> 2416 <name>div2</name> 2417 <description>Divide by 2.</description> 2418 <value>1</value> 2419 </enumeratedValue> 2420 <enumeratedValue> 2421 <name>div4</name> 2422 <description>Divide by 4.</description> 2423 <value>2</value> 2424 </enumeratedValue> 2425 <enumeratedValue> 2426 <name>div8</name> 2427 <description>Divide by 8.</description> 2428 <value>3</value> 2429 </enumeratedValue> 2430 <enumeratedValue> 2431 <name>div16</name> 2432 <description>Divide by 16.</description> 2433 <value>4</value> 2434 </enumeratedValue> 2435 <enumeratedValue> 2436 <name>div32</name> 2437 <description>Divide by 32.</description> 2438 <value>5</value> 2439 </enumeratedValue> 2440 <enumeratedValue> 2441 <name>div64</name> 2442 <description>Divide by 64.</description> 2443 <value>6</value> 2444 </enumeratedValue> 2445 <enumeratedValue> 2446 <name>div128</name> 2447 <description>Divide by 128.</description> 2448 <value>7</value> 2449 </enumeratedValue> 2450 </enumeratedValues> 2451 </field> 2452 <field> 2453 <name>SYSCLK_SEL</name> 2454 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 2455 <bitOffset>9</bitOffset> 2456 <bitWidth>3</bitWidth> 2457 <enumeratedValues> 2458 <enumeratedValue> 2459 <name>IPO</name> 2460 <description>Internal Primary Oscilatior Clock</description> 2461 <value>0</value> 2462 </enumeratedValue> 2463 <enumeratedValue> 2464 <name>INRO</name> 2465 <description>8kHz Internal Nano Ring Oscillator is used for the system clock.</description> 2466 <value>3</value> 2467 </enumeratedValue> 2468 <enumeratedValue> 2469 <name>IBRO</name> 2470 <description>The internal Baud Rate oscillator is used for the system clock.</description> 2471 <value>5</value> 2472 </enumeratedValue> 2473 </enumeratedValues> 2474 </field> 2475 <field> 2476 <name>SYSCLK_RDY</name> 2477 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 2478 <bitOffset>13</bitOffset> 2479 <bitWidth>1</bitWidth> 2480 <access>read-only</access> 2481 <enumeratedValues> 2482 <enumeratedValue> 2483 <name>busy</name> 2484 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 2485 <value>0</value> 2486 </enumeratedValue> 2487 <enumeratedValue> 2488 <name>ready</name> 2489 <description>System clock running from CLKSEL clock source.</description> 2490 <value>1</value> 2491 </enumeratedValue> 2492 </enumeratedValues> 2493 </field> 2494 <field> 2495 <name>CCD</name> 2496 <description>Cryptographic clock divider</description> 2497 <bitOffset>15</bitOffset> 2498 <bitWidth>1</bitWidth> 2499 <access>read-only</access> 2500 <enumeratedValues> 2501 <enumeratedValue> 2502 <name>non_div</name> 2503 <description>The cryptographic accelerator clock is running in non-divided mode.</description> 2504 <value>0</value> 2505 </enumeratedValue> 2506 <enumeratedValue> 2507 <name>div</name> 2508 <description>The cryptographic accelerator clock is running in divided mode.</description> 2509 <value>1</value> 2510 </enumeratedValue> 2511 </enumeratedValues> 2512 </field> 2513 <field> 2514 <name>IPO_EN</name> 2515 <description>96MHz High Frequency Internal Reference Clock Enable.</description> 2516 <bitOffset>18</bitOffset> 2517 <bitWidth>1</bitWidth> 2518 </field> 2519 <field derivedFrom="IPO_EN"> 2520 <name>IBRO_EN</name> 2521 <description>8MHz High Frequency Internal Reference Clock Enable.</description> 2522 <bitOffset>20</bitOffset> 2523 <bitWidth>1</bitWidth> 2524 </field> 2525 <field> 2526 <name>IBRO_VS</name> 2527 <description>7.3728MHz Internal Oscillator Voltage Source Select</description> 2528 <bitOffset>21</bitOffset> 2529 <bitWidth>1</bitWidth> 2530 </field> 2531 <field> 2532 <name>IPO_RDY</name> 2533 <description>Internal Primary Oscillator Ready.</description> 2534 <bitOffset>26</bitOffset> 2535 <bitWidth>1</bitWidth> 2536 </field> 2537 <field derivedFrom="IPO_RDY"> 2538 <name>IBRO_RDY</name> 2539 <description>Internal Baud Rate Oscillator Ready.</description> 2540 <bitOffset>28</bitOffset> 2541 <bitWidth>1</bitWidth> 2542 </field> 2543 <field derivedFrom="IPO_RDY"> 2544 <name>INRO_RDY</name> 2545 <description>Internal Nano Ring Oscillator Low Frequency Reference Clock Ready.</description> 2546 <bitOffset>29</bitOffset> 2547 <bitWidth>1</bitWidth> 2548 </field> 2549 </fields> 2550 </register> 2551 <register> 2552 <name>PM</name> 2553 <description>Power Management.</description> 2554 <addressOffset>0x0C</addressOffset> 2555 <fields> 2556 <field> 2557 <name>MODE</name> 2558 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 2559 <bitOffset>0</bitOffset> 2560 <bitWidth>3</bitWidth> 2561 <enumeratedValues> 2562 <enumeratedValue> 2563 <name>active</name> 2564 <description>Active Mode.</description> 2565 <value>0</value> 2566 </enumeratedValue> 2567 <enumeratedValue> 2568 <name>deepsleep</name> 2569 <description>DeepSleep Mode.</description> 2570 <value>2</value> 2571 </enumeratedValue> 2572 <enumeratedValue> 2573 <name>shutdown</name> 2574 <description>Shutdown Mode.</description> 2575 <value>3</value> 2576 </enumeratedValue> 2577 <enumeratedValue> 2578 <name>backup</name> 2579 <description>Backup Mode.</description> 2580 <value>4</value> 2581 </enumeratedValue> 2582 </enumeratedValues> 2583 </field> 2584 <field> 2585 <name>GPIO_WE</name> 2586 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 2587 <bitOffset>4</bitOffset> 2588 <bitWidth>1</bitWidth> 2589 </field> 2590 <field> 2591 <name>IPO_PD</name> 2592 <description>Internal Primary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. </description> 2593 <bitOffset>15</bitOffset> 2594 <bitWidth>1</bitWidth> 2595 <enumeratedValues> 2596 <enumeratedValue> 2597 <name>active</name> 2598 <description>Mode is Active.</description> 2599 <value>0</value> 2600 </enumeratedValue> 2601 <enumeratedValue> 2602 <name>deepsleep</name> 2603 <description>Powered down in DEEPSLEEP.</description> 2604 <value>1</value> 2605 </enumeratedValue> 2606 </enumeratedValues> 2607 </field> 2608 <field> 2609 <name>IBRO_PD</name> 2610 <description>Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. </description> 2611 <bitOffset>17</bitOffset> 2612 <bitWidth>1</bitWidth> 2613 <enumeratedValues> 2614 <enumeratedValue> 2615 <name>active</name> 2616 <description>Mode is Active.</description> 2617 <value>0</value> 2618 </enumeratedValue> 2619 <enumeratedValue> 2620 <name>deepsleep</name> 2621 <description>Powered down in DEEPSLEEP.</description> 2622 <value>1</value> 2623 </enumeratedValue> 2624 </enumeratedValues> 2625 </field> 2626 </fields> 2627 </register> 2628 <register> 2629 <name>PCLKDIV</name> 2630 <description>Peripheral Clock Divider.</description> 2631 <addressOffset>0x18</addressOffset> 2632 <resetValue>0x00000001</resetValue> 2633 <fields> 2634 <field> 2635 <name>PCF</name> 2636 <description>These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware.</description> 2637 <bitOffset>0</bitOffset> 2638 <bitWidth>3</bitWidth> 2639 <enumeratedValues> 2640 <enumeratedValue> 2641 <name>96MHz</name> 2642 <value>2</value> 2643 </enumeratedValue> 2644 <enumeratedValue> 2645 <name>48MHz</name> 2646 <value>3</value> 2647 </enumeratedValue> 2648 <enumeratedValue> 2649 <name>24MHz</name> 2650 <value>4</value> 2651 </enumeratedValue> 2652 <enumeratedValue> 2653 <name>12MHz</name> 2654 <value>5</value> 2655 </enumeratedValue> 2656 <enumeratedValue> 2657 <name>6MHz</name> 2658 <value>6</value> 2659 </enumeratedValue> 2660 <enumeratedValue> 2661 <name>3MHz</name> 2662 <value>7</value> 2663 </enumeratedValue> 2664 </enumeratedValues> 2665 </field> 2666 <field> 2667 <name>PCFWEN</name> 2668 <description>PCF Write Enable. This bit allows the PCF Register bits to be updated by Software.</description> 2669 <bitOffset>3</bitOffset> 2670 <bitWidth>1</bitWidth> 2671 <enumeratedValues> 2672 <enumeratedValue> 2673 <name>blocked</name> 2674 <description>Writes to PCF are blocked.</description> 2675 <value>0</value> 2676 </enumeratedValue> 2677 <enumeratedValue> 2678 <name>allowed</name> 2679 <description>Writes to PCF are allowed</description> 2680 <value>1</value> 2681 </enumeratedValue> 2682 </enumeratedValues> 2683 </field> 2684 <field> 2685 <name>AON_CLKDIV</name> 2686 <description>Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider.</description> 2687 <bitOffset>14</bitOffset> 2688 <bitWidth>2</bitWidth> 2689 <enumeratedValues> 2690 <enumeratedValue> 2691 <name>div_4</name> 2692 <description>PCLK divide by 4.</description> 2693 <value>0</value> 2694 </enumeratedValue> 2695 <enumeratedValue> 2696 <name>div_8</name> 2697 <description>PCLK divide by 8.</description> 2698 <value>1</value> 2699 </enumeratedValue> 2700 <enumeratedValue> 2701 <name>div_16</name> 2702 <description>PCLK divide by 16.</description> 2703 <value>2</value> 2704 </enumeratedValue> 2705 <enumeratedValue> 2706 <name>div_32</name> 2707 <description>PCLK divide by 32.</description> 2708 <value>3</value> 2709 </enumeratedValue> 2710 </enumeratedValues> 2711 </field> 2712 </fields> 2713 </register> 2714 <register> 2715 <name>PCLKDIS0</name> 2716 <description>Peripheral Clock Disable.</description> 2717 <addressOffset>0x24</addressOffset> 2718 <fields> 2719 <field> 2720 <name>GPIO0</name> 2721 <description>GPIO0 Clock Disable.</description> 2722 <bitOffset>0</bitOffset> 2723 <bitWidth>1</bitWidth> 2724 <enumeratedValues> 2725 <enumeratedValue> 2726 <name>en</name> 2727 <description>enable it.</description> 2728 <value>0</value> 2729 </enumeratedValue> 2730 <enumeratedValue> 2731 <name>dis</name> 2732 <description>disable it.</description> 2733 <value>1</value> 2734 </enumeratedValue> 2735 </enumeratedValues> 2736 </field> 2737 <field derivedFrom="GPIO0"> 2738 <name>GPIO1</name> 2739 <description>GPIO1 Disable.</description> 2740 <bitOffset>1</bitOffset> 2741 <bitWidth>1</bitWidth> 2742 </field> 2743 <field derivedFrom="GPIO0"> 2744 <name>DMA</name> 2745 <description>DMA Disable.</description> 2746 <bitOffset>5</bitOffset> 2747 <bitWidth>1</bitWidth> 2748 </field> 2749 <field derivedFrom="GPIO0"> 2750 <name>SPI0</name> 2751 <description>SPI 0 Disable.</description> 2752 <bitOffset>6</bitOffset> 2753 <bitWidth>1</bitWidth> 2754 </field> 2755 <field derivedFrom="GPIO0"> 2756 <name>SPI1</name> 2757 <description>SPI 1 Disable.</description> 2758 <bitOffset>7</bitOffset> 2759 <bitWidth>1</bitWidth> 2760 </field> 2761 <field derivedFrom="GPIO0"> 2762 <name>UART0</name> 2763 <description>UART 0 Disable.</description> 2764 <bitOffset>9</bitOffset> 2765 <bitWidth>1</bitWidth> 2766 </field> 2767 <field derivedFrom="GPIO0"> 2768 <name>I2C0</name> 2769 <description>I2C 0 Disable.</description> 2770 <bitOffset>13</bitOffset> 2771 <bitWidth>1</bitWidth> 2772 </field> 2773 <field derivedFrom="GPIO0"> 2774 <name>CRYPTO</name> 2775 <description>Crypto Disable.</description> 2776 <bitOffset>14</bitOffset> 2777 <bitWidth>1</bitWidth> 2778 </field> 2779 <field derivedFrom="GPIO0"> 2780 <name>TMR0</name> 2781 <description>Timer 0 Disable.</description> 2782 <bitOffset>15</bitOffset> 2783 <bitWidth>1</bitWidth> 2784 </field> 2785 <field derivedFrom="GPIO0"> 2786 <name>TMR1</name> 2787 <description>Timer 1 Disable.</description> 2788 <bitOffset>16</bitOffset> 2789 <bitWidth>1</bitWidth> 2790 </field> 2791 <field derivedFrom="GPIO0"> 2792 <name>TMR2</name> 2793 <description>Timer 2 Disable.</description> 2794 <bitOffset>17</bitOffset> 2795 <bitWidth>1</bitWidth> 2796 </field> 2797 <field derivedFrom="GPIO0"> 2798 <name>TMR3</name> 2799 <description>Timer 3 Disable.</description> 2800 <bitOffset>18</bitOffset> 2801 <bitWidth>1</bitWidth> 2802 </field> 2803 </fields> 2804 </register> 2805 <register> 2806 <name>MEMCTRL</name> 2807 <description>Memory Clock Control Register.</description> 2808 <addressOffset>0x28</addressOffset> 2809 <fields> 2810 <field> 2811 <name>FWS</name> 2812 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 2813 <bitOffset>0</bitOffset> 2814 <bitWidth>3</bitWidth> 2815 </field> 2816 <field> 2817 <name>RAMWS_EN</name> 2818 <description>SRAM Wait State Enable</description> 2819 <bitOffset>4</bitOffset> 2820 <bitWidth>1</bitWidth> 2821 </field> 2822 <field> 2823 <name>RAM0LS_EN</name> 2824 <description>System RAM 0 Light Sleep Mode.</description> 2825 <bitOffset>16</bitOffset> 2826 <bitWidth>1</bitWidth> 2827 <enumeratedValues> 2828 <enumeratedValue> 2829 <name>active</name> 2830 <description>RAM is active.</description> 2831 <value>0</value> 2832 </enumeratedValue> 2833 <enumeratedValue> 2834 <name>light_sleep</name> 2835 <description>RAM is in Light Sleep mode.</description> 2836 <value>1</value> 2837 </enumeratedValue> 2838 </enumeratedValues> 2839 </field> 2840 <field derivedFrom="RAM0LS_EN"> 2841 <name>RAM1LS_EN</name> 2842 <description>System RAM 1 Light Sleep Mode.</description> 2843 <bitOffset>17</bitOffset> 2844 <bitWidth>1</bitWidth> 2845 </field> 2846 <field derivedFrom="RAM0LS_EN"> 2847 <name>RAM2LS_EN</name> 2848 <description>System RAM 2 Light Sleep Mode.</description> 2849 <bitOffset>18</bitOffset> 2850 <bitWidth>1</bitWidth> 2851 </field> 2852 <field derivedFrom="RAM0LS_EN"> 2853 <name>RAM3LS_EN</name> 2854 <description>System RAM 3 Light Sleep Mode.</description> 2855 <bitOffset>19</bitOffset> 2856 <bitWidth>1</bitWidth> 2857 </field> 2858 <field derivedFrom="RAM0LS_EN"> 2859 <name>RAM4LS_EN</name> 2860 <description>System RAM 4 Light Sleep Mode.</description> 2861 <bitOffset>20</bitOffset> 2862 <bitWidth>1</bitWidth> 2863 </field> 2864 <field derivedFrom="RAM0LS_EN"> 2865 <name>ICC0LS_EN</name> 2866 <description>ICache RAM Light Sleep Mode.</description> 2867 <bitOffset>24</bitOffset> 2868 <bitWidth>1</bitWidth> 2869 </field> 2870 <field derivedFrom="RAM0LS_EN"> 2871 <name>ROMLS_EN</name> 2872 <description>ROM Light Sleep Mode.</description> 2873 <bitOffset>29</bitOffset> 2874 <bitWidth>1</bitWidth> 2875 </field> 2876 </fields> 2877 </register> 2878 <register> 2879 <name>MEMZ</name> 2880 <description>Memory Zeroize Control.</description> 2881 <addressOffset>0x2C</addressOffset> 2882 <fields> 2883 <field> 2884 <name>RAM0</name> 2885 <description>System RAM Block 0.</description> 2886 <bitOffset>0</bitOffset> 2887 <bitWidth>1</bitWidth> 2888 <enumeratedValues> 2889 <enumeratedValue> 2890 <name>nop</name> 2891 <description>No operation/complete.</description> 2892 <value>0</value> 2893 </enumeratedValue> 2894 <enumeratedValue> 2895 <name>start</name> 2896 <description>Start operation.</description> 2897 <value>1</value> 2898 </enumeratedValue> 2899 </enumeratedValues> 2900 </field> 2901 <field derivedFrom="RAM0"> 2902 <name>RAM1</name> 2903 <description>System RAM Block 1.</description> 2904 <bitOffset>1</bitOffset> 2905 <bitWidth>1</bitWidth> 2906 </field> 2907 <field derivedFrom="RAM0"> 2908 <name>RAM2</name> 2909 <description>System RAM Block 2.</description> 2910 <bitOffset>2</bitOffset> 2911 <bitWidth>1</bitWidth> 2912 </field> 2913 <field derivedFrom="RAM0"> 2914 <name>RAM3</name> 2915 <description>System RAM Block 3.</description> 2916 <bitOffset>3</bitOffset> 2917 <bitWidth>1</bitWidth> 2918 </field> 2919 <field derivedFrom="RAM0"> 2920 <name>RAM4</name> 2921 <description>System RAM Block 4.</description> 2922 <bitOffset>4</bitOffset> 2923 <bitWidth>1</bitWidth> 2924 </field> 2925 <field derivedFrom="RAM0"> 2926 <name>ICC0</name> 2927 <description>Instruction Cache.</description> 2928 <bitOffset>8</bitOffset> 2929 <bitWidth>1</bitWidth> 2930 </field> 2931 </fields> 2932 </register> 2933 <register> 2934 <name>SYSST</name> 2935 <description>System Status Register.</description> 2936 <addressOffset>0x40</addressOffset> 2937 <fields> 2938 <field> 2939 <name>ICELOCK</name> 2940 <description>ARM ICE Lock Status.</description> 2941 <bitOffset>0</bitOffset> 2942 <bitWidth>1</bitWidth> 2943 <enumeratedValues> 2944 <enumeratedValue> 2945 <name>unlocked</name> 2946 <description>ICE is unlocked.</description> 2947 <value>0</value> 2948 </enumeratedValue> 2949 <enumeratedValue> 2950 <name>locked</name> 2951 <description>ICE is locked.</description> 2952 <value>1</value> 2953 </enumeratedValue> 2954 </enumeratedValues> 2955 </field> 2956 </fields> 2957 </register> 2958 <register> 2959 <name>RST1</name> 2960 <description>Reset 1.</description> 2961 <addressOffset>0x44</addressOffset> 2962 <fields> 2963 <field> 2964 <name>WDT1</name> 2965 <description>WDT1 Reset.</description> 2966 <bitOffset>8</bitOffset> 2967 <bitWidth>1</bitWidth> 2968 </field> 2969 <field derivedFrom="WDT1"> 2970 <name>SFES</name> 2971 <description>Serial Flash Emulation Slave Reset.</description> 2972 <bitOffset>28</bitOffset> 2973 <bitWidth>1</bitWidth> 2974 </field> 2975 </fields> 2976 </register> 2977 <register> 2978 <name>PCLKDIS1</name> 2979 <description>Peripheral Clock Disable.</description> 2980 <addressOffset>0x48</addressOffset> 2981 <fields> 2982 <field> 2983 <name>TRNG</name> 2984 <description>TRNG Disable.</description> 2985 <bitOffset>2</bitOffset> 2986 <bitWidth>1</bitWidth> 2987 </field> 2988 <field derivedFrom="TRNG"> 2989 <name>WDT0</name> 2990 <description>WDT0 Clock Disable</description> 2991 <bitOffset>27</bitOffset> 2992 <bitWidth>1</bitWidth> 2993 </field> 2994 <field derivedFrom="TRNG"> 2995 <name>WDT1</name> 2996 <description>WDT1 Clock Disable</description> 2997 <bitOffset>28</bitOffset> 2998 <bitWidth>1</bitWidth> 2999 </field> 3000 <field derivedFrom="TRNG"> 3001 <name>SFES</name> 3002 <description>Serial Flash emulation slave Clock Disable</description> 3003 <bitOffset>30</bitOffset> 3004 <bitWidth>1</bitWidth> 3005 </field> 3006 </fields> 3007 </register> 3008 <register> 3009 <name>EVENTEN</name> 3010 <description>Event Enable Register.</description> 3011 <addressOffset>0x4C</addressOffset> 3012 <fields> 3013 <field> 3014 <name>DMA</name> 3015 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 3016 <bitOffset>0</bitOffset> 3017 <bitWidth>1</bitWidth> 3018 </field> 3019 <field> 3020 <name>RX</name> 3021 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 3022 <bitOffset>1</bitOffset> 3023 <bitWidth>1</bitWidth> 3024 </field> 3025 <field> 3026 <name>TX</name> 3027 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].</description> 3028 <bitOffset>2</bitOffset> 3029 <bitWidth>1</bitWidth> 3030 </field> 3031 </fields> 3032 </register> 3033 <register> 3034 <name>REVISION</name> 3035 <description>Revision Register.</description> 3036 <addressOffset>0x50</addressOffset> 3037 <access>read-only</access> 3038 <fields> 3039 <field> 3040 <name>REVISION</name> 3041 <description>Manufacturer Chip Revision. </description> 3042 <bitOffset>0</bitOffset> 3043 <bitWidth>16</bitWidth> 3044 </field> 3045 </fields> 3046 </register> 3047 <register> 3048 <name>SYSIE</name> 3049 <description>System Status Interrupt Enable Register.</description> 3050 <addressOffset>0x54</addressOffset> 3051 <fields> 3052 <field> 3053 <name>ICEUNLOCK</name> 3054 <description>ARM ICE Unlock Interrupt Enable.</description> 3055 <bitOffset>0</bitOffset> 3056 <bitWidth>1</bitWidth> 3057 <enumeratedValues> 3058 <enumeratedValue> 3059 <name>dis</name> 3060 <description>disabled.</description> 3061 <value>0</value> 3062 </enumeratedValue> 3063 <enumeratedValue> 3064 <name>en</name> 3065 <description>enabled.</description> 3066 <value>1</value> 3067 </enumeratedValue> 3068 </enumeratedValues> 3069 </field> 3070 </fields> 3071 </register> 3072 <register> 3073 <name>ECCERR</name> 3074 <description>ECC Error Register</description> 3075 <addressOffset>0x64</addressOffset> 3076 <fields> 3077 <field> 3078 <name>RAM0</name> 3079 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 3080 <bitOffset>0</bitOffset> 3081 <bitWidth>1</bitWidth> 3082 </field> 3083 <field> 3084 <name>RAM1</name> 3085 <description>ECC System RAM1 Error Flag. Write 1 to clear.</description> 3086 <bitOffset>1</bitOffset> 3087 <bitWidth>1</bitWidth> 3088 </field> 3089 <field> 3090 <name>RAM2</name> 3091 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 3092 <bitOffset>2</bitOffset> 3093 <bitWidth>1</bitWidth> 3094 </field> 3095 <field> 3096 <name>RAM3</name> 3097 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 3098 <bitOffset>3</bitOffset> 3099 <bitWidth>1</bitWidth> 3100 </field> 3101 <field> 3102 <name>RAM4</name> 3103 <description>ECC System RAM4 Error Flag. Write 1 to clear.</description> 3104 <bitOffset>4</bitOffset> 3105 <bitWidth>1</bitWidth> 3106 </field> 3107 </fields> 3108 </register> 3109 <register> 3110 <name>ECCCED</name> 3111 <description>ECC Not Double Error Detect Register</description> 3112 <addressOffset>0x68</addressOffset> 3113 <fields> 3114 <field> 3115 <name>RAM0</name> 3116 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 3117 <bitOffset>0</bitOffset> 3118 <bitWidth>1</bitWidth> 3119 </field> 3120 <field> 3121 <name>RAM1</name> 3122 <description>ECC System RAM1 Not Double Error Detect. Write 1 to clear.</description> 3123 <bitOffset>1</bitOffset> 3124 <bitWidth>1</bitWidth> 3125 </field> 3126 <field> 3127 <name>RAM2</name> 3128 <description>ECC System RAM2 Not Double Error Detect. Write 1 to clear.</description> 3129 <bitOffset>2</bitOffset> 3130 <bitWidth>1</bitWidth> 3131 </field> 3132 <field> 3133 <name>RAM3</name> 3134 <description>ECC System RAM3 Not Double Error Detect. Write 1 to clear.</description> 3135 <bitOffset>3</bitOffset> 3136 <bitWidth>1</bitWidth> 3137 </field> 3138 <field> 3139 <name>RAM4</name> 3140 <description>ECC System RAM4 Not Double Error Detect. Write 1 to clear.</description> 3141 <bitOffset>4</bitOffset> 3142 <bitWidth>1</bitWidth> 3143 </field> 3144 </fields> 3145 </register> 3146 <register> 3147 <name>ECCIE</name> 3148 <description>ECC IRQ Enable Register</description> 3149 <addressOffset>0x6C</addressOffset> 3150 <fields> 3151 <field> 3152 <name>RAM0</name> 3153 <description>ECC System RAM0 Interrupt Enable.</description> 3154 <bitOffset>0</bitOffset> 3155 <bitWidth>1</bitWidth> 3156 </field> 3157 <field> 3158 <name>RAM1</name> 3159 <description>ECC System RAM1 Interrupt Enable.</description> 3160 <bitOffset>1</bitOffset> 3161 <bitWidth>1</bitWidth> 3162 </field> 3163 <field> 3164 <name>RAM2</name> 3165 <description>ECC System RAM2 Interrupt Enable.</description> 3166 <bitOffset>2</bitOffset> 3167 <bitWidth>1</bitWidth> 3168 </field> 3169 <field> 3170 <name>RAM3</name> 3171 <description>ECC System RAM3 Interrupt Enable.</description> 3172 <bitOffset>3</bitOffset> 3173 <bitWidth>1</bitWidth> 3174 </field> 3175 <field> 3176 <name>RAM4</name> 3177 <description>ECC System RAM4 Interrupt Enable.</description> 3178 <bitOffset>4</bitOffset> 3179 <bitWidth>1</bitWidth> 3180 </field> 3181 </fields> 3182 </register> 3183 <register> 3184 <name>ECCADDR</name> 3185 <description>ECC Error Address Register</description> 3186 <addressOffset>0x70</addressOffset> 3187 <fields> 3188 <field> 3189 <name>DATARAMADDR</name> 3190 <description>ECC Error Address/DATA RAM Error Address</description> 3191 <bitOffset>0</bitOffset> 3192 <bitWidth>14</bitWidth> 3193 </field> 3194 <field> 3195 <name>DATARAMBANK</name> 3196 <description>ECC Error Address/DATA RAM Error Bank</description> 3197 <bitOffset>14</bitOffset> 3198 <bitWidth>1</bitWidth> 3199 </field> 3200 <field> 3201 <name>DATARAMERR</name> 3202 <description>DATA RAM ERROR</description> 3203 <bitOffset>15</bitOffset> 3204 <bitWidth>1</bitWidth> 3205 </field> 3206 <field> 3207 <name>TAGRAMADDR</name> 3208 <description>ECC Error Address/TAG RAM Error Address</description> 3209 <bitOffset>16</bitOffset> 3210 <bitWidth>14</bitWidth> 3211 </field> 3212 <field> 3213 <name>TAGRAMBANK</name> 3214 <description>ECC Error Address/TAG RAM Error Bank</description> 3215 <bitOffset>30</bitOffset> 3216 <bitWidth>1</bitWidth> 3217 </field> 3218 <field> 3219 <name>TAGRAMERR</name> 3220 <description>TAG RAM ERROR</description> 3221 <bitOffset>31</bitOffset> 3222 <bitWidth>1</bitWidth> 3223 </field> 3224 </fields> 3225 </register> 3226 </registers> 3227 </peripheral> 3228<!--GCR Global Control Registers.--> 3229 <peripheral> 3230 <name>GPIO0</name> 3231 <description>Individual I/O for each GPIO</description> 3232 <groupName>GPIO</groupName> 3233 <baseAddress>0x40008000</baseAddress> 3234 <addressBlock> 3235 <offset>0x00</offset> 3236 <size>0x1000</size> 3237 <usage>registers</usage> 3238 </addressBlock> 3239 <interrupt> 3240 <name>GPIO0</name> 3241 <description>GPIO0 interrupt.</description> 3242 <value>24</value> 3243 </interrupt> 3244 <registers> 3245 <register> 3246 <name>EN0</name> 3247 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 3248 <addressOffset>0x00</addressOffset> 3249 <fields> 3250 <field> 3251 <name>GPIO_EN0</name> 3252 <description>Mask of all of the pins on the port.</description> 3253 <bitOffset>0</bitOffset> 3254 <bitWidth>32</bitWidth> 3255 <enumeratedValues> 3256 <enumeratedValue> 3257 <name>ALTERNATE</name> 3258 <description>Alternate function enabled.</description> 3259 <value>0</value> 3260 </enumeratedValue> 3261 <enumeratedValue> 3262 <name>GPIO</name> 3263 <description>GPIO function is enabled.</description> 3264 <value>1</value> 3265 </enumeratedValue> 3266 </enumeratedValues> 3267 </field> 3268 </fields> 3269 </register> 3270 <register> 3271 <name>EN0_SET</name> 3272 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 3273 <addressOffset>0x04</addressOffset> 3274 <fields> 3275 <field> 3276 <name>GPIO_EN0_SET</name> 3277 <description>Mask of all of the pins on the port.</description> 3278 <bitOffset>0</bitOffset> 3279 <bitWidth>32</bitWidth> 3280 </field> 3281 </fields> 3282 </register> 3283 <register> 3284 <name>EN0_CLR</name> 3285 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 3286 <addressOffset>0x08</addressOffset> 3287 <fields> 3288 <field> 3289 <name>GPIO_EN0_CLR</name> 3290 <description>Mask of all of the pins on the port.</description> 3291 <bitOffset>0</bitOffset> 3292 <bitWidth>32</bitWidth> 3293 </field> 3294 </fields> 3295 </register> 3296 <register> 3297 <name>OUT_EN</name> 3298 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 3299 <addressOffset>0x0C</addressOffset> 3300 <fields> 3301 <field> 3302 <name>GPIO_OUT_EN</name> 3303 <description>Mask of all of the pins on the port.</description> 3304 <bitOffset>0</bitOffset> 3305 <bitWidth>32</bitWidth> 3306 <enumeratedValues> 3307 <enumeratedValue> 3308 <name>dis</name> 3309 <description>GPIO Output Disable</description> 3310 <value>0</value> 3311 </enumeratedValue> 3312 <enumeratedValue> 3313 <name>en</name> 3314 <description>GPIO Output Enable</description> 3315 <value>1</value> 3316 </enumeratedValue> 3317 </enumeratedValues> 3318 </field> 3319 </fields> 3320 </register> 3321 <register> 3322 <name>OUT_EN_SET</name> 3323 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 3324 <addressOffset>0x10</addressOffset> 3325 <fields> 3326 <field> 3327 <name>GPIO_OUT_EN_SET</name> 3328 <description>Mask of all of the pins on the port.</description> 3329 <bitOffset>0</bitOffset> 3330 <bitWidth>32</bitWidth> 3331 </field> 3332 </fields> 3333 </register> 3334 <register> 3335 <name>OUT_EN_CLR</name> 3336 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 3337 <addressOffset>0x14</addressOffset> 3338 <fields> 3339 <field> 3340 <name>GPIO_OUT_EN_CLR</name> 3341 <description>Mask of all of the pins on the port.</description> 3342 <bitOffset>0</bitOffset> 3343 <bitWidth>32</bitWidth> 3344 </field> 3345 </fields> 3346 </register> 3347 <register> 3348 <name>OUT</name> 3349 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 3350 <addressOffset>0x18</addressOffset> 3351 <fields> 3352 <field> 3353 <name>GPIO_OUT</name> 3354 <description>Mask of all of the pins on the port.</description> 3355 <bitOffset>0</bitOffset> 3356 <bitWidth>32</bitWidth> 3357 <enumeratedValues> 3358 <enumeratedValue> 3359 <name>low</name> 3360 <description>Drive Logic 0 (low) on GPIO output.</description> 3361 <value>0</value> 3362 </enumeratedValue> 3363 <enumeratedValue> 3364 <name>high</name> 3365 <description>Drive logic 1 (high) on GPIO output.</description> 3366 <value>1</value> 3367 </enumeratedValue> 3368 </enumeratedValues> 3369 </field> 3370 </fields> 3371 </register> 3372 <register> 3373 <name>OUT_SET</name> 3374 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 3375 <addressOffset>0x1C</addressOffset> 3376 <access>write-only</access> 3377 <fields> 3378 <field> 3379 <name>GPIO_OUT_SET</name> 3380 <description>Mask of all of the pins on the port.</description> 3381 <bitOffset>0</bitOffset> 3382 <bitWidth>32</bitWidth> 3383 <enumeratedValues> 3384 <enumeratedValue> 3385 <name>no</name> 3386 <description>No Effect.</description> 3387 <value>0</value> 3388 </enumeratedValue> 3389 <enumeratedValue> 3390 <name>set</name> 3391 <description>Set GPIO_OUT bit in this position to '1'</description> 3392 <value>1</value> 3393 </enumeratedValue> 3394 </enumeratedValues> 3395 </field> 3396 </fields> 3397 </register> 3398 <register> 3399 <name>OUT_CLR</name> 3400 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 3401 <addressOffset>0x20</addressOffset> 3402 <access>write-only</access> 3403 <fields> 3404 <field> 3405 <name>GPIO_OUT_CLR</name> 3406 <description>Mask of all of the pins on the port.</description> 3407 <bitOffset>0</bitOffset> 3408 <bitWidth>32</bitWidth> 3409 </field> 3410 </fields> 3411 </register> 3412 <register> 3413 <name>IN</name> 3414 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 3415 <addressOffset>0x24</addressOffset> 3416 <access>read-only</access> 3417 <fields> 3418 <field> 3419 <name>GPIO_IN</name> 3420 <description>Mask of all of the pins on the port.</description> 3421 <bitOffset>0</bitOffset> 3422 <bitWidth>32</bitWidth> 3423 </field> 3424 </fields> 3425 </register> 3426 <register> 3427 <name>INT_MOD</name> 3428 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 3429 <addressOffset>0x28</addressOffset> 3430 <fields> 3431 <field> 3432 <name>GPIO_INT_MOD</name> 3433 <description>Mask of all of the pins on the port.</description> 3434 <bitOffset>0</bitOffset> 3435 <bitWidth>32</bitWidth> 3436 <enumeratedValues> 3437 <enumeratedValue> 3438 <name>level</name> 3439 <description>Interrupts for this pin are level triggered.</description> 3440 <value>0</value> 3441 </enumeratedValue> 3442 <enumeratedValue> 3443 <name>edge</name> 3444 <description>Interrupts for this pin are edge triggered.</description> 3445 <value>1</value> 3446 </enumeratedValue> 3447 </enumeratedValues> 3448 </field> 3449 </fields> 3450 </register> 3451 <register> 3452 <name>INT_POL</name> 3453 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 3454 <addressOffset>0x2C</addressOffset> 3455 <fields> 3456 <field> 3457 <name>GPIO_INT_POL</name> 3458 <description>Mask of all of the pins on the port.</description> 3459 <bitOffset>0</bitOffset> 3460 <bitWidth>32</bitWidth> 3461 <enumeratedValues> 3462 <enumeratedValue> 3463 <name>falling</name> 3464 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 3465 <value>0</value> 3466 </enumeratedValue> 3467 <enumeratedValue> 3468 <name>rising</name> 3469 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 3470 <value>1</value> 3471 </enumeratedValue> 3472 </enumeratedValues> 3473 </field> 3474 </fields> 3475 </register> 3476 <register> 3477 <name>IN_EN</name> 3478 <description>GPIO Input Enable</description> 3479 <addressOffset>0x30</addressOffset> 3480 <fields> 3481 <field> 3482 <name>GPIO_IN_EN</name> 3483 <description>Connects corresponding input pad to specified input pin for reading the pin state using GPIOn_IN register.</description> 3484 <bitOffset>0</bitOffset> 3485 <bitWidth>32</bitWidth> 3486 <enumeratedValues> 3487 <enumeratedValue> 3488 <name>not_connected</name> 3489 <description>Input not connected.</description> 3490 <value>0</value> 3491 </enumeratedValue> 3492 <enumeratedValue> 3493 <name>connected</name> 3494 <description>Input pin connected to the pad.</description> 3495 <value>1</value> 3496 </enumeratedValue> 3497 </enumeratedValues> 3498 </field> 3499 </fields> 3500 </register> 3501 <register> 3502 <name>INT_EN</name> 3503 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 3504 <addressOffset>0x34</addressOffset> 3505 <fields> 3506 <field> 3507 <name>GPIO_INT_EN</name> 3508 <description>Mask of all of the pins on the port.</description> 3509 <bitOffset>0</bitOffset> 3510 <bitWidth>32</bitWidth> 3511 <enumeratedValues> 3512 <enumeratedValue> 3513 <name>dis</name> 3514 <description>Interrupts are disabled for this GPIO pin.</description> 3515 <value>0</value> 3516 </enumeratedValue> 3517 <enumeratedValue> 3518 <name>en</name> 3519 <description>Interrupts are enabled for this GPIO pin.</description> 3520 <value>1</value> 3521 </enumeratedValue> 3522 </enumeratedValues> 3523 </field> 3524 </fields> 3525 </register> 3526 <register> 3527 <name>INT_EN_SET</name> 3528 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 3529 <addressOffset>0x38</addressOffset> 3530 <fields> 3531 <field> 3532 <name>GPIO_INT_EN_SET</name> 3533 <description>Mask of all of the pins on the port.</description> 3534 <bitOffset>0</bitOffset> 3535 <bitWidth>32</bitWidth> 3536 <enumeratedValues> 3537 <enumeratedValue> 3538 <name>no</name> 3539 <description>No effect.</description> 3540 <value>0</value> 3541 </enumeratedValue> 3542 <enumeratedValue> 3543 <name>set</name> 3544 <description>Set GPIO_INT_EN bit in this position to '1'</description> 3545 <value>1</value> 3546 </enumeratedValue> 3547 </enumeratedValues> 3548 </field> 3549 </fields> 3550 </register> 3551 <register> 3552 <name>INT_EN_CLR</name> 3553 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 3554 <addressOffset>0x3C</addressOffset> 3555 <fields> 3556 <field> 3557 <name>GPIO_INT_EN_CLR</name> 3558 <description>Mask of all of the pins on the port.</description> 3559 <bitOffset>0</bitOffset> 3560 <bitWidth>32</bitWidth> 3561 <enumeratedValues> 3562 <enumeratedValue> 3563 <name>no</name> 3564 <description>No Effect.</description> 3565 <value>0</value> 3566 </enumeratedValue> 3567 <enumeratedValue> 3568 <name>clear</name> 3569 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 3570 <value>1</value> 3571 </enumeratedValue> 3572 </enumeratedValues> 3573 </field> 3574 </fields> 3575 </register> 3576 <register> 3577 <name>INT_STAT</name> 3578 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 3579 <addressOffset>0x40</addressOffset> 3580 <access>read-only</access> 3581 <fields> 3582 <field> 3583 <name>GPIO_INT_STAT</name> 3584 <description>Mask of all of the pins on the port.</description> 3585 <bitOffset>0</bitOffset> 3586 <bitWidth>32</bitWidth> 3587 <enumeratedValues> 3588 <enumeratedValue> 3589 <name>no</name> 3590 <description>No Interrupt is pending on this GPIO pin.</description> 3591 <value>0</value> 3592 </enumeratedValue> 3593 <enumeratedValue> 3594 <name>pending</name> 3595 <description>An Interrupt is pending on this GPIO pin.</description> 3596 <value>1</value> 3597 </enumeratedValue> 3598 </enumeratedValues> 3599 </field> 3600 </fields> 3601 </register> 3602 <register> 3603 <name>INT_CLR</name> 3604 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 3605 <addressOffset>0x48</addressOffset> 3606 <fields> 3607 <field> 3608 <name>GPIO_INT_CLR</name> 3609 <description>Mask of all of the pins on the port.</description> 3610 <bitOffset>0</bitOffset> 3611 <bitWidth>32</bitWidth> 3612 </field> 3613 </fields> 3614 </register> 3615 <register> 3616 <name>WAKE_EN</name> 3617 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 3618 <addressOffset>0x4C</addressOffset> 3619 <fields> 3620 <field> 3621 <name>GPIO_WAKE_EN</name> 3622 <description>Mask of all of the pins on the port.</description> 3623 <bitOffset>0</bitOffset> 3624 <bitWidth>32</bitWidth> 3625 <enumeratedValues> 3626 <enumeratedValue> 3627 <name>dis</name> 3628 <description>PMU wakeup for this GPIO is disabled.</description> 3629 <value>0</value> 3630 </enumeratedValue> 3631 <enumeratedValue> 3632 <name>en</name> 3633 <description>PMU wakeup for this GPIO is enabled.</description> 3634 <value>1</value> 3635 </enumeratedValue> 3636 </enumeratedValues> 3637 </field> 3638 </fields> 3639 </register> 3640 <register> 3641 <name>WAKE_EN_SET</name> 3642 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 3643 <addressOffset>0x50</addressOffset> 3644 <fields> 3645 <field> 3646 <name>GPIO_WAKE_EN_SET</name> 3647 <description>Mask of all of the pins on the port.</description> 3648 <bitOffset>0</bitOffset> 3649 <bitWidth>32</bitWidth> 3650 </field> 3651 </fields> 3652 </register> 3653 <register> 3654 <name>WAKE_EN_CLR</name> 3655 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 3656 <addressOffset>0x54</addressOffset> 3657 <fields> 3658 <field> 3659 <name>GPIO_WAKE_EN_CLR</name> 3660 <description>Mask of all of the pins on the port.</description> 3661 <bitOffset>0</bitOffset> 3662 <bitWidth>32</bitWidth> 3663 </field> 3664 </fields> 3665 </register> 3666 <register> 3667 <name>INT_DUAL_EDGE</name> 3668 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 3669 <addressOffset>0x5C</addressOffset> 3670 <fields> 3671 <field> 3672 <name>GPIO_INT_DUAL_EDGE</name> 3673 <description>Mask of all of the pins on the port.</description> 3674 <bitOffset>0</bitOffset> 3675 <bitWidth>32</bitWidth> 3676 <enumeratedValues> 3677 <enumeratedValue> 3678 <name>no</name> 3679 <description>No Effect.</description> 3680 <value>0</value> 3681 </enumeratedValue> 3682 <enumeratedValue> 3683 <name>en</name> 3684 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 3685 <value>1</value> 3686 </enumeratedValue> 3687 </enumeratedValues> 3688 </field> 3689 </fields> 3690 </register> 3691 <register> 3692 <name>PDPU_SEL0</name> 3693 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 3694 <addressOffset>0x60</addressOffset> 3695 <fields> 3696 <field> 3697 <name>GPIO_PDPU_SEL0</name> 3698 <description>The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 3699 <bitOffset>0</bitOffset> 3700 <bitWidth>32</bitWidth> 3701 <enumeratedValues> 3702 <enumeratedValue> 3703 <name>impedance</name> 3704 <description>High Impedance.</description> 3705 <value>0</value> 3706 </enumeratedValue> 3707 <enumeratedValue> 3708 <name>pu</name> 3709 <description>Weak pull-up mode.</description> 3710 <value>1</value> 3711 </enumeratedValue> 3712 <enumeratedValue> 3713 <name>pd</name> 3714 <description>weak pull-down mode.</description> 3715 <value>2</value> 3716 </enumeratedValue> 3717 </enumeratedValues> 3718 </field> 3719 </fields> 3720 </register> 3721 <register> 3722 <name>PDPU_SEL1</name> 3723 <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 3724 <addressOffset>0x64</addressOffset> 3725 <fields> 3726 <field> 3727 <name>GPIO_PDPU_SEL1</name> 3728 <description>The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 3729 <bitOffset>0</bitOffset> 3730 <bitWidth>32</bitWidth> 3731 <enumeratedValues> 3732 <enumeratedValue> 3733 <name>impedance</name> 3734 <description>High Impedance.</description> 3735 <value>0</value> 3736 </enumeratedValue> 3737 <enumeratedValue> 3738 <name>pu</name> 3739 <description>Weak pull-up mode.</description> 3740 <value>1</value> 3741 </enumeratedValue> 3742 <enumeratedValue> 3743 <name>pd</name> 3744 <description>weak pull-down mode.</description> 3745 <value>2</value> 3746 </enumeratedValue> 3747 </enumeratedValues> 3748 </field> 3749 </fields> 3750 </register> 3751 <register> 3752 <name>EN1</name> 3753 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 3754 <addressOffset>0x68</addressOffset> 3755 <fields> 3756 <field> 3757 <name>GPIO_EN1</name> 3758 <description>Mask of all of the pins on the port.</description> 3759 <bitOffset>0</bitOffset> 3760 <bitWidth>32</bitWidth> 3761 <enumeratedValues> 3762 <enumeratedValue> 3763 <name>primary</name> 3764 <description>Primary function selected.</description> 3765 <value>0</value> 3766 </enumeratedValue> 3767 <enumeratedValue> 3768 <name>secondary</name> 3769 <description>Secondary function selected.</description> 3770 <value>1</value> 3771 </enumeratedValue> 3772 </enumeratedValues> 3773 </field> 3774 </fields> 3775 </register> 3776 <register> 3777 <name>EN1_SET</name> 3778 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 3779 <addressOffset>0x6C</addressOffset> 3780 <fields> 3781 <field> 3782 <name>GPIO_EN1_SET</name> 3783 <description>Mask of all of the pins on the port.</description> 3784 <bitOffset>0</bitOffset> 3785 <bitWidth>32</bitWidth> 3786 </field> 3787 </fields> 3788 </register> 3789 <register> 3790 <name>EN1_CLR</name> 3791 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 3792 <addressOffset>0x70</addressOffset> 3793 <fields> 3794 <field> 3795 <name>GPIO_EN1_CLR</name> 3796 <description>Mask of all of the pins on the port.</description> 3797 <bitOffset>0</bitOffset> 3798 <bitWidth>32</bitWidth> 3799 </field> 3800 </fields> 3801 </register> 3802 <register> 3803 <name>DS_SEL0</name> 3804 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 3805 <addressOffset>0xB0</addressOffset> 3806 <fields> 3807 <field> 3808 <name>DS_SEL0</name> 3809 <description>Mask of all of the pins on the port.</description> 3810 <bitOffset>0</bitOffset> 3811 <bitWidth>32</bitWidth> 3812 <enumeratedValues> 3813 <enumeratedValue> 3814 <name>ld</name> 3815 <description>GPIO port pin is in low-drive mode.</description> 3816 <value>0</value> 3817 </enumeratedValue> 3818 <enumeratedValue> 3819 <name>hd</name> 3820 <description>GPIO port pin is in high-drive mode.</description> 3821 <value>1</value> 3822 </enumeratedValue> 3823 </enumeratedValues> 3824 </field> 3825 </fields> 3826 </register> 3827 <register> 3828 <name>DS_SEL1</name> 3829 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 3830 <addressOffset>0xB4</addressOffset> 3831 <fields> 3832 <field> 3833 <name>DS_SEL1</name> 3834 <description>Mask of all of the pins on the port.</description> 3835 <bitOffset>0</bitOffset> 3836 <bitWidth>32</bitWidth> 3837 </field> 3838 </fields> 3839 </register> 3840 <register> 3841 <name>PSSEL</name> 3842 <description>GPIO Pull Select Mode.</description> 3843 <addressOffset>0xB8</addressOffset> 3844 <fields> 3845 <field> 3846 <name>PSSEL</name> 3847 <description>Mask of all of the pins on the port.</description> 3848 <bitOffset>0</bitOffset> 3849 <bitWidth>32</bitWidth> 3850 </field> 3851 </fields> 3852 </register> 3853 </registers> 3854 </peripheral> 3855<!--GPIO0 Individual I/O for each GPIO--> 3856 <peripheral derivedFrom="GPIO0"> 3857 <name>GPIO1</name> 3858 <description>Individual I/O for each GPIO 1</description> 3859 <baseAddress>0x40009000</baseAddress> 3860 <interrupt> 3861 <name>GPIO1</name> 3862 <description>GPIO1 IRQ</description> 3863 <value>25</value> 3864 </interrupt> 3865 </peripheral> 3866<!--GPIO1 Individual I/O for each GPIO 1--> 3867 <peripheral> 3868 <name>I2C0</name> 3869 <description>Inter-Integrated Circuit.</description> 3870 <groupName>I2C</groupName> 3871 <baseAddress>0x4001D000</baseAddress> 3872 <size>32</size> 3873 <addressBlock> 3874 <offset>0x00</offset> 3875 <size>0x1000</size> 3876 <usage>registers</usage> 3877 </addressBlock> 3878 <interrupt> 3879 <name>I2C0</name> 3880 <description>I2C0 IRQ</description> 3881 <value>13</value> 3882 </interrupt> 3883 <registers> 3884 <register> 3885 <name>CN</name> 3886 <description>Control Register0.</description> 3887 <addressOffset>0x00</addressOffset> 3888 <fields> 3889 <field> 3890 <name>I2CEN</name> 3891 <description>I2C Enable.</description> 3892 <bitRange>[0:0]</bitRange> 3893 <access>read-write</access> 3894 <enumeratedValues> 3895 <enumeratedValue> 3896 <name>dis</name> 3897 <description>Disable I2C.</description> 3898 <value>0</value> 3899 </enumeratedValue> 3900 <enumeratedValue> 3901 <name>en</name> 3902 <description>Enable I2C.</description> 3903 <value>1</value> 3904 </enumeratedValue> 3905 </enumeratedValues> 3906 </field> 3907 <field> 3908 <name>MST</name> 3909 <description>Master Mode Enable.</description> 3910 <bitRange>[1:1]</bitRange> 3911 <access>read-write</access> 3912 <enumeratedValues> 3913 <enumeratedValue> 3914 <name>slave_mode</name> 3915 <description>Slave Mode.</description> 3916 <value>0</value> 3917 </enumeratedValue> 3918 <enumeratedValue> 3919 <name>master_mode</name> 3920 <description>Master Mode.</description> 3921 <value>1</value> 3922 </enumeratedValue> 3923 </enumeratedValues> 3924 </field> 3925 <field> 3926 <name>GCEN</name> 3927 <description>General Call Address Enable.</description> 3928 <bitRange>[2:2]</bitRange> 3929 <access>read-write</access> 3930 <enumeratedValues> 3931 <enumeratedValue> 3932 <name>dis</name> 3933 <description>Ignore Gneral Call Address.</description> 3934 <value>0</value> 3935 </enumeratedValue> 3936 <enumeratedValue> 3937 <name>en</name> 3938 <description>Acknowledge general call address.</description> 3939 <value>1</value> 3940 </enumeratedValue> 3941 </enumeratedValues> 3942 </field> 3943 <field> 3944 <name>IRXM</name> 3945 <description>Interactive Receive Mode.</description> 3946 <bitRange>[3:3]</bitRange> 3947 <access>read-write</access> 3948 <enumeratedValues> 3949 <enumeratedValue> 3950 <name>dis</name> 3951 <description>Disable Interactive Receive Mode.</description> 3952 <value>0</value> 3953 </enumeratedValue> 3954 <enumeratedValue> 3955 <name>en</name> 3956 <description>Enable Interactive Receive Mode.</description> 3957 <value>1</value> 3958 </enumeratedValue> 3959 </enumeratedValues> 3960 </field> 3961 <field> 3962 <name>ACK</name> 3963 <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description> 3964 <bitRange>[4:4]</bitRange> 3965 <access>read-write</access> 3966 <enumeratedValues> 3967 <enumeratedValue> 3968 <name>ack</name> 3969 <description>return ACK (pulling SDA LOW).</description> 3970 <value>0</value> 3971 </enumeratedValue> 3972 <enumeratedValue> 3973 <name>nack</name> 3974 <description>return NACK (leaving SDA HIGH).</description> 3975 <value>1</value> 3976 </enumeratedValue> 3977 </enumeratedValues> 3978 </field> 3979 <field> 3980 <name>SCLO</name> 3981 <description>SCL Output. This bits control SCL output when SWOE =1.</description> 3982 <bitRange>[6:6]</bitRange> 3983 <access>read-write</access> 3984 <enumeratedValues> 3985 <enumeratedValue> 3986 <name>drive_scl_low</name> 3987 <description>Drive SCL low. </description> 3988 <value>0</value> 3989 </enumeratedValue> 3990 <enumeratedValue> 3991 <name>release_scl</name> 3992 <description>Release SCL.</description> 3993 <value>1</value> 3994 </enumeratedValue> 3995 </enumeratedValues> 3996 </field> 3997 <field> 3998 <name>SDAO</name> 3999 <description>SDA Output. This bits control SDA output when SWOE = 1. </description> 4000 <bitRange>[7:7]</bitRange> 4001 <access>read-write</access> 4002 <enumeratedValues> 4003 <enumeratedValue> 4004 <name>drive_sda_low</name> 4005 <description>Drive SDA low. </description> 4006 <value>0</value> 4007 </enumeratedValue> 4008 <enumeratedValue> 4009 <name>release_sda</name> 4010 <description>Release SDA.</description> 4011 <value>1</value> 4012 </enumeratedValue> 4013 </enumeratedValues> 4014 </field> 4015 <field> 4016 <name>SCL</name> 4017 <description>SCL status. This bit reflects the logic gate of SCL signal. </description> 4018 <bitRange>[8:8]</bitRange> 4019 <access>read-only</access> 4020 </field> 4021 <field> 4022 <name>SDA</name> 4023 <description>SDA status. THis bit reflects the logic gate of SDA signal.</description> 4024 <bitRange>[9:9]</bitRange> 4025 <access>read-only</access> 4026 </field> 4027 <field> 4028 <name>SWOE</name> 4029 <description>Software Output Enable.</description> 4030 <bitRange>[10:10]</bitRange> 4031 <access>read-write</access> 4032 <enumeratedValues> 4033 <enumeratedValue> 4034 <name>outputs_disable</name> 4035 <description>I2C Outputs SCLO and SDAO disabled. </description> 4036 <value>0</value> 4037 </enumeratedValue> 4038 <enumeratedValue> 4039 <name>outputs_enable</name> 4040 <description>I2C Outputs SCLO and SDAO enabled.</description> 4041 <value>1</value> 4042 </enumeratedValue> 4043 </enumeratedValues> 4044 </field> 4045 <field> 4046 <name>READ</name> 4047 <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description> 4048 <bitRange>[11:11]</bitRange> 4049 <access>read-only</access> 4050 <enumeratedValues> 4051 <enumeratedValue> 4052 <name>write</name> 4053 <description>Write.</description> 4054 <value>0</value> 4055 </enumeratedValue> 4056 <enumeratedValue> 4057 <name>read</name> 4058 <description>Read.</description> 4059 <value>1</value> 4060 </enumeratedValue> 4061 </enumeratedValues> 4062 </field> 4063 <field> 4064 <name>SCLSTRD</name> 4065 <description>This bit will disable slave clock stretching when set.</description> 4066 <bitRange>[12:12]</bitRange> 4067 <access>read-write</access> 4068 <enumeratedValues> 4069 <enumeratedValue> 4070 <name>en</name> 4071 <description>Slave clock stretching enabled.</description> 4072 <value>0</value> 4073 </enumeratedValue> 4074 <enumeratedValue> 4075 <name>dis</name> 4076 <description>Slave clock stretching disabled.</description> 4077 <value>1</value> 4078 </enumeratedValue> 4079 </enumeratedValues> 4080 </field> 4081 <field> 4082 <name>SCLPPM</name> 4083 <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description> 4084 <bitRange>[13:13]</bitRange> 4085 <access>read-write</access> 4086 <enumeratedValues> 4087 <enumeratedValue> 4088 <name>dis</name> 4089 <description>Standard open-drain operation: 4090 drive low for 0, Hi-Z for 1</description> 4091 <value>0</value> 4092 </enumeratedValue> 4093 <enumeratedValue> 4094 <name>en</name> 4095 <description>Non-standard push-pull operation: 4096 drive low for 0, drive high for 1</description> 4097 <value>1</value> 4098 </enumeratedValue> 4099 </enumeratedValues> 4100 </field> 4101 </fields> 4102 </register> 4103 <register> 4104 <name>ST</name> 4105 <description>Status Register.</description> 4106 <addressOffset>0x04</addressOffset> 4107 <fields> 4108 <field> 4109 <name>BUS</name> 4110 <description>Bus Status.</description> 4111 <bitRange>[0:0]</bitRange> 4112 <access>read-only</access> 4113 <enumeratedValues> 4114 <enumeratedValue> 4115 <name>idle</name> 4116 <description>I2C Bus Idle.</description> 4117 <value>0</value> 4118 </enumeratedValue> 4119 <enumeratedValue> 4120 <name>busy</name> 4121 <description>I2C Bus Busy.</description> 4122 <value>1</value> 4123 </enumeratedValue> 4124 </enumeratedValues> 4125 </field> 4126 <field> 4127 <name>RXE</name> 4128 <description>RX empty.</description> 4129 <bitRange>[1:1]</bitRange> 4130 <access>read-only</access> 4131 <enumeratedValues> 4132 <enumeratedValue> 4133 <name>not_empty</name> 4134 <description>Not Empty.</description> 4135 <value>0</value> 4136 </enumeratedValue> 4137 <enumeratedValue> 4138 <name>empty</name> 4139 <description>Empty.</description> 4140 <value>1</value> 4141 </enumeratedValue> 4142 </enumeratedValues> 4143 </field> 4144 <field> 4145 <name>RXF</name> 4146 <description>RX Full.</description> 4147 <bitRange>[2:2]</bitRange> 4148 <access>read-only</access> 4149 <enumeratedValues> 4150 <enumeratedValue> 4151 <name>not_full</name> 4152 <description>Not Full.</description> 4153 <value>0</value> 4154 </enumeratedValue> 4155 <enumeratedValue> 4156 <name>full</name> 4157 <description>Full.</description> 4158 <value>1</value> 4159 </enumeratedValue> 4160 </enumeratedValues> 4161 </field> 4162 <field> 4163 <name>TXE</name> 4164 <description>TX Empty.</description> 4165 <bitRange>[3:3]</bitRange> 4166 <enumeratedValues> 4167 <enumeratedValue> 4168 <name>not_empty</name> 4169 <description>Not Empty.</description> 4170 <value>0</value> 4171 </enumeratedValue> 4172 <enumeratedValue> 4173 <name>empty</name> 4174 <description>Empty.</description> 4175 <value>1</value> 4176 </enumeratedValue> 4177 </enumeratedValues> 4178 </field> 4179 <field> 4180 <name>TXF</name> 4181 <description>TX Full.</description> 4182 <bitRange>[4:4]</bitRange> 4183 <enumeratedValues> 4184 <enumeratedValue> 4185 <name>not_empty</name> 4186 <description>Not Empty.</description> 4187 <value>0</value> 4188 </enumeratedValue> 4189 <enumeratedValue> 4190 <name>empty</name> 4191 <description>Empty.</description> 4192 <value>1</value> 4193 </enumeratedValue> 4194 </enumeratedValues> 4195 </field> 4196 <field> 4197 <name>CKMD</name> 4198 <description>Clock Mode.</description> 4199 <bitRange>[5:5]</bitRange> 4200 <access>read-only</access> 4201 <enumeratedValues> 4202 <enumeratedValue> 4203 <name>not_actively_driving_scl_clock</name> 4204 <description>Device not actively driving SCL clock cycles.</description> 4205 <value>0</value> 4206 </enumeratedValue> 4207 <enumeratedValue> 4208 <name>actively_driving_scl_clock</name> 4209 <description>Device operating as master and actively driving SCL clock cycles.</description> 4210 <value>1</value> 4211 </enumeratedValue> 4212 </enumeratedValues> 4213 </field> 4214 <field> 4215 <name>ST</name> 4216 <description>Status Controller.</description> 4217 <bitRange>[11:8]</bitRange> 4218 <access>read-only</access> 4219 </field> 4220 </fields> 4221 </register> 4222 <register> 4223 <name>INT0</name> 4224 <description>Interrupt Status Register.</description> 4225 <addressOffset>0x08</addressOffset> 4226 <fields> 4227 <field> 4228 <name>DONEI</name> 4229 <description>Transfer Done Interrupt.</description> 4230 <bitRange>[0:0]</bitRange> 4231 <enumeratedValues> 4232 <enumeratedValue> 4233 <name>inactive</name> 4234 <description>No Interrupt is Pending.</description> 4235 <value>0</value> 4236 </enumeratedValue> 4237 <enumeratedValue> 4238 <name>pending</name> 4239 <description>An interrupt is pending.</description> 4240 <value>1</value> 4241 </enumeratedValue> 4242 </enumeratedValues> 4243 </field> 4244 <field> 4245 <name>IRXMI</name> 4246 <description>Interactive Receive Interrupt.</description> 4247 <bitRange>[1:1]</bitRange> 4248 <enumeratedValues> 4249 <enumeratedValue> 4250 <name>inactive</name> 4251 <description>No Interrupt is Pending.</description> 4252 <value>0</value> 4253 </enumeratedValue> 4254 <enumeratedValue> 4255 <name>pending</name> 4256 <description>An interrupt is pending.</description> 4257 <value>1</value> 4258 </enumeratedValue> 4259 </enumeratedValues> 4260 </field> 4261 <field> 4262 <name>GCI</name> 4263 <description>Slave General Call Address Match Interrupt.</description> 4264 <bitRange>[2:2]</bitRange> 4265 <enumeratedValues> 4266 <enumeratedValue> 4267 <name>inactive</name> 4268 <description>No Interrupt is Pending.</description> 4269 <value>0</value> 4270 </enumeratedValue> 4271 <enumeratedValue> 4272 <name>pending</name> 4273 <description>An interrupt is pending.</description> 4274 <value>1</value> 4275 </enumeratedValue> 4276 </enumeratedValues> 4277 </field> 4278 <field> 4279 <name>AMI</name> 4280 <description>Slave Address Match Interrupt.</description> 4281 <bitRange>[3:3]</bitRange> 4282 <enumeratedValues> 4283 <enumeratedValue> 4284 <name>inactive</name> 4285 <description>No Interrupt is Pending.</description> 4286 <value>0</value> 4287 </enumeratedValue> 4288 <enumeratedValue> 4289 <name>pending</name> 4290 <description>An interrupt is pending.</description> 4291 <value>1</value> 4292 </enumeratedValue> 4293 </enumeratedValues> 4294 </field> 4295 <field> 4296 <name>RXTHI</name> 4297 <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description> 4298 <bitRange>[4:4]</bitRange> 4299 <enumeratedValues> 4300 <enumeratedValue> 4301 <name>inactive</name> 4302 <description>No interrupt is pending.</description> 4303 <value>0</value> 4304 </enumeratedValue> 4305 <enumeratedValue> 4306 <name>pending</name> 4307 <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description> 4308 <value>1</value> 4309 </enumeratedValue> 4310 </enumeratedValues> 4311 </field> 4312 <field> 4313 <name>TXTHI</name> 4314 <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description> 4315 <bitRange>[5:5]</bitRange> 4316 <enumeratedValues> 4317 <enumeratedValue> 4318 <name>inactive</name> 4319 <description>No interrupt is pending.</description> 4320 <value>0</value> 4321 </enumeratedValue> 4322 <enumeratedValue> 4323 <name>pending</name> 4324 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 4325 <value>1</value> 4326 </enumeratedValue> 4327 </enumeratedValues> 4328 </field> 4329 <field> 4330 <name>STOPI</name> 4331 <description>STOP Interrupt.</description> 4332 <bitRange>[6:6]</bitRange> 4333 <enumeratedValues> 4334 <enumeratedValue> 4335 <name>inactive</name> 4336 <description>No interrupt is pending.</description> 4337 <value>0</value> 4338 </enumeratedValue> 4339 <enumeratedValue> 4340 <name>pending</name> 4341 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 4342 <value>1</value> 4343 </enumeratedValue> 4344 </enumeratedValues> 4345 </field> 4346 <field> 4347 <name>ADRACKI</name> 4348 <description>Address Acknowledge Interrupt.</description> 4349 <bitRange>[7:7]</bitRange> 4350 <enumeratedValues> 4351 <enumeratedValue> 4352 <name>inactive</name> 4353 <description>No Interrupt is Pending.</description> 4354 <value>0</value> 4355 </enumeratedValue> 4356 <enumeratedValue> 4357 <name>pending</name> 4358 <description>An interrupt is pending.</description> 4359 <value>1</value> 4360 </enumeratedValue> 4361 </enumeratedValues> 4362 </field> 4363 <field> 4364 <name>ARBERI</name> 4365 <description>Arbritation error Interrupt.</description> 4366 <bitRange>[8:8]</bitRange> 4367 <enumeratedValues> 4368 <enumeratedValue> 4369 <name>inactive</name> 4370 <description>No Interrupt is Pending.</description> 4371 <value>0</value> 4372 </enumeratedValue> 4373 <enumeratedValue> 4374 <name>pending</name> 4375 <description>An interrupt is pending.</description> 4376 <value>1</value> 4377 </enumeratedValue> 4378 </enumeratedValues> 4379 </field> 4380 <field> 4381 <name>TOERI</name> 4382 <description>timeout Error Interrupt.</description> 4383 <bitRange>[9:9]</bitRange> 4384 <enumeratedValues> 4385 <enumeratedValue> 4386 <name>inactive</name> 4387 <description>No Interrupt is Pending.</description> 4388 <value>0</value> 4389 </enumeratedValue> 4390 <enumeratedValue> 4391 <name>pending</name> 4392 <description>An interrupt is pending.</description> 4393 <value>1</value> 4394 </enumeratedValue> 4395 </enumeratedValues> 4396 </field> 4397 <field> 4398 <name>ADRERI</name> 4399 <description>Address NACK Error Interrupt.</description> 4400 <bitRange>[10:10]</bitRange> 4401 <enumeratedValues> 4402 <enumeratedValue> 4403 <name>inactive</name> 4404 <description>No Interrupt is Pending.</description> 4405 <value>0</value> 4406 </enumeratedValue> 4407 <enumeratedValue> 4408 <name>pending</name> 4409 <description>An interrupt is pending.</description> 4410 <value>1</value> 4411 </enumeratedValue> 4412 </enumeratedValues> 4413 </field> 4414 <field> 4415 <name>DATERI</name> 4416 <description>Data NACK Error Interrupt.</description> 4417 <bitRange>[11:11]</bitRange> 4418 <enumeratedValues> 4419 <enumeratedValue> 4420 <name>inactive</name> 4421 <description>No Interrupt is Pending.</description> 4422 <value>0</value> 4423 </enumeratedValue> 4424 <enumeratedValue> 4425 <name>pending</name> 4426 <description>An interrupt is pending.</description> 4427 <value>1</value> 4428 </enumeratedValue> 4429 </enumeratedValues> 4430 </field> 4431 <field> 4432 <name>DNRERI</name> 4433 <description>Do Not Respond Error Interrupt.</description> 4434 <bitRange>[12:12]</bitRange> 4435 <enumeratedValues> 4436 <enumeratedValue> 4437 <name>inactive</name> 4438 <description>No Interrupt is Pending.</description> 4439 <value>0</value> 4440 </enumeratedValue> 4441 <enumeratedValue> 4442 <name>pending</name> 4443 <description>An interrupt is pending.</description> 4444 <value>1</value> 4445 </enumeratedValue> 4446 </enumeratedValues> 4447 </field> 4448 <field> 4449 <name>STRTERI</name> 4450 <description>Start Error Interrupt.</description> 4451 <bitRange>[13:13]</bitRange> 4452 <enumeratedValues> 4453 <enumeratedValue> 4454 <name>inactive</name> 4455 <description>No Interrupt is Pending.</description> 4456 <value>0</value> 4457 </enumeratedValue> 4458 <enumeratedValue> 4459 <name>pending</name> 4460 <description>An interrupt is pending.</description> 4461 <value>1</value> 4462 </enumeratedValue> 4463 </enumeratedValues> 4464 </field> 4465 <field> 4466 <name>STOPERI</name> 4467 <description>Stop Error Interrupt.</description> 4468 <bitRange>[14:14]</bitRange> 4469 <enumeratedValues> 4470 <enumeratedValue> 4471 <name>inactive</name> 4472 <description>No Interrupt is Pending.</description> 4473 <value>0</value> 4474 </enumeratedValue> 4475 <enumeratedValue> 4476 <name>pending</name> 4477 <description>An interrupt is pending.</description> 4478 <value>1</value> 4479 </enumeratedValue> 4480 </enumeratedValues> 4481 </field> 4482 <field> 4483 <name>TXLOI</name> 4484 <description>Transmit Lock Out Interrupt.</description> 4485 <bitRange>[15:15]</bitRange> 4486 </field> 4487 <field> 4488 <name>RDAMI</name> 4489 <description>Slave Read Address Match Interrupt.</description> 4490 <bitRange>[22:22]</bitRange> 4491 </field> 4492 <field> 4493 <name>WRAMI</name> 4494 <description>Slave Write Address Match Interrupt.</description> 4495 <bitRange>[23:23]</bitRange> 4496 </field> 4497 </fields> 4498 </register> 4499 <register> 4500 <name>INTEN0</name> 4501 <description>Interrupt Enable Register.</description> 4502 <addressOffset>0x0C</addressOffset> 4503 <access>read-write</access> 4504 <fields> 4505 <field> 4506 <name>DONEIE</name> 4507 <description>Transfer Done Interrupt Enable.</description> 4508 <bitRange>[0:0]</bitRange> 4509 <access>read-write</access> 4510 <enumeratedValues> 4511 <enumeratedValue> 4512 <name>dis</name> 4513 <description>Interrupt disabled.</description> 4514 <value>0</value> 4515 </enumeratedValue> 4516 <enumeratedValue> 4517 <name>en</name> 4518 <description>Interrupt enabled when DONE = 1.</description> 4519 <value>1</value> 4520 </enumeratedValue> 4521 </enumeratedValues> 4522 </field> 4523 <field> 4524 <name>IRXMIE</name> 4525 <description>Description not available.</description> 4526 <bitRange>[1:1]</bitRange> 4527 <access>read-write</access> 4528 <enumeratedValues> 4529 <enumeratedValue> 4530 <name>dis</name> 4531 <description>Interrupt disabled.</description> 4532 <value>0</value> 4533 </enumeratedValue> 4534 <enumeratedValue> 4535 <name>en</name> 4536 <description>Interrupt enabled when RX_MODE = 1.</description> 4537 <value>1</value> 4538 </enumeratedValue> 4539 </enumeratedValues> 4540 </field> 4541 <field> 4542 <name>GCIE</name> 4543 <description>Slave mode general call address match received input enable.</description> 4544 <bitRange>[2:2]</bitRange> 4545 <access>read-write</access> 4546 <enumeratedValues> 4547 <enumeratedValue> 4548 <name>dis</name> 4549 <description>Interrupt disabled.</description> 4550 <value>0</value> 4551 </enumeratedValue> 4552 <enumeratedValue> 4553 <name>en</name> 4554 <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description> 4555 <value>1</value> 4556 </enumeratedValue> 4557 </enumeratedValues> 4558 </field> 4559 <field> 4560 <name>AMIE</name> 4561 <description>Slave mode incoming address match interrupt.</description> 4562 <bitRange>[3:3]</bitRange> 4563 <access>read-write</access> 4564 <enumeratedValues> 4565 <enumeratedValue> 4566 <name>dis</name> 4567 <description>Interrupt disabled.</description> 4568 <value>0</value> 4569 </enumeratedValue> 4570 <enumeratedValue> 4571 <name>en</name> 4572 <description>Interrupt enabled when ADDR_MATCH = 1.</description> 4573 <value>1</value> 4574 </enumeratedValue> 4575 </enumeratedValues> 4576 </field> 4577 <field> 4578 <name>RXTHIE</name> 4579 <description>RX FIFO Above Treshold Level Interrupt Enable.</description> 4580 <bitRange>[4:4]</bitRange> 4581 <access>read-write</access> 4582 <enumeratedValues> 4583 <enumeratedValue> 4584 <name>dis</name> 4585 <description>Interrupt disabled.</description> 4586 <value>0</value> 4587 </enumeratedValue> 4588 <enumeratedValue> 4589 <name>en</name> 4590 <description>Interrupt enabled.</description> 4591 <value>1</value> 4592 </enumeratedValue> 4593 </enumeratedValues> 4594 </field> 4595 <field> 4596 <name>TXTHIE</name> 4597 <description>TX FIFO Below Treshold Level Interrupt Enable.</description> 4598 <bitRange>[5:5]</bitRange> 4599 <enumeratedValues> 4600 <enumeratedValue> 4601 <name>dis</name> 4602 <description>Interrupt disabled.</description> 4603 <value>0</value> 4604 </enumeratedValue> 4605 <enumeratedValue> 4606 <name>en</name> 4607 <description>Interrupt enabled.</description> 4608 <value>1</value> 4609 </enumeratedValue> 4610 </enumeratedValues> 4611 </field> 4612 <field> 4613 <name>STOPIE</name> 4614 <description>Stop Interrupt Enable</description> 4615 <bitRange>[6:6]</bitRange> 4616 <access>read-write</access> 4617 <enumeratedValues> 4618 <enumeratedValue> 4619 <name>dis</name> 4620 <description>Interrupt disabled.</description> 4621 <value>0</value> 4622 </enumeratedValue> 4623 <enumeratedValue> 4624 <name>en</name> 4625 <description>Interrupt enabled when STOP = 1.</description> 4626 <value>1</value> 4627 </enumeratedValue> 4628 </enumeratedValues> 4629 </field> 4630 <field> 4631 <name>ADRACKIE</name> 4632 <description>Received Address ACK from Slave Interrupt.</description> 4633 <bitRange>[7:7]</bitRange> 4634 <enumeratedValues> 4635 <enumeratedValue> 4636 <name>dis</name> 4637 <description>Interrupt disabled.</description> 4638 <value>0</value> 4639 </enumeratedValue> 4640 <enumeratedValue> 4641 <name>en</name> 4642 <description>Interrupt enabled.</description> 4643 <value>1</value> 4644 </enumeratedValue> 4645 </enumeratedValues> 4646 </field> 4647 <field> 4648 <name>ARBERIE</name> 4649 <description>Master Mode Arbitration Lost Interrupt.</description> 4650 <bitRange>[8:8]</bitRange> 4651 <enumeratedValues> 4652 <enumeratedValue> 4653 <name>dis</name> 4654 <description>Interrupt disabled.</description> 4655 <value>0</value> 4656 </enumeratedValue> 4657 <enumeratedValue> 4658 <name>en</name> 4659 <description>Interrupt enabled.</description> 4660 <value>1</value> 4661 </enumeratedValue> 4662 </enumeratedValues> 4663 </field> 4664 <field> 4665 <name>TOERIE</name> 4666 <description>Timeout Error Interrupt Enable.</description> 4667 <bitRange>[9:9]</bitRange> 4668 <enumeratedValues> 4669 <enumeratedValue> 4670 <name>dis</name> 4671 <description>Interrupt disabled.</description> 4672 <value>0</value> 4673 </enumeratedValue> 4674 <enumeratedValue> 4675 <name>en</name> 4676 <description>Interrupt enabled.</description> 4677 <value>1</value> 4678 </enumeratedValue> 4679 </enumeratedValues> 4680 </field> 4681 <field> 4682 <name>ADRERIE</name> 4683 <description>Master Mode Address NACK Received Interrupt.</description> 4684 <bitRange>[10:10]</bitRange> 4685 <enumeratedValues> 4686 <enumeratedValue> 4687 <name>dis</name> 4688 <description>Interrupt disabled.</description> 4689 <value>0</value> 4690 </enumeratedValue> 4691 <enumeratedValue> 4692 <name>en</name> 4693 <description>Interrupt enabled.</description> 4694 <value>1</value> 4695 </enumeratedValue> 4696 </enumeratedValues> 4697 </field> 4698 <field> 4699 <name>DATERIE</name> 4700 <description>Master Mode Data NACK Received Interrupt.</description> 4701 <bitRange>[11:11]</bitRange> 4702 <enumeratedValues> 4703 <enumeratedValue> 4704 <name>dis</name> 4705 <description>Interrupt disabled.</description> 4706 <value>0</value> 4707 </enumeratedValue> 4708 <enumeratedValue> 4709 <name>en</name> 4710 <description>Interrupt enabled.</description> 4711 <value>1</value> 4712 </enumeratedValue> 4713 </enumeratedValues> 4714 </field> 4715 <field> 4716 <name>DNRERIE</name> 4717 <description>Slave Mode Do Not Respond Interrupt.</description> 4718 <bitRange>[12:12]</bitRange> 4719 <enumeratedValues> 4720 <enumeratedValue> 4721 <name>dis</name> 4722 <description>Interrupt disabled.</description> 4723 <value>0</value> 4724 </enumeratedValue> 4725 <enumeratedValue> 4726 <name>en</name> 4727 <description>Interrupt enabled.</description> 4728 <value>1</value> 4729 </enumeratedValue> 4730 </enumeratedValues> 4731 </field> 4732 <field> 4733 <name>STRTERIE</name> 4734 <description>Out of Sequence START condition detected interrupt.</description> 4735 <bitRange>[13:13]</bitRange> 4736 <enumeratedValues> 4737 <enumeratedValue> 4738 <name>dis</name> 4739 <description>Interrupt disabled.</description> 4740 <value>0</value> 4741 </enumeratedValue> 4742 <enumeratedValue> 4743 <name>en</name> 4744 <description>Interrupt enabled.</description> 4745 <value>1</value> 4746 </enumeratedValue> 4747 </enumeratedValues> 4748 </field> 4749 <field> 4750 <name>STOPERIE</name> 4751 <description>Out of Sequence STOP condition detected interrupt.</description> 4752 <bitRange>[14:14]</bitRange> 4753 <enumeratedValues> 4754 <enumeratedValue> 4755 <name>dis</name> 4756 <description>Interrupt disabled.</description> 4757 <value>0</value> 4758 </enumeratedValue> 4759 <enumeratedValue> 4760 <name>en</name> 4761 <description>Interrupt enabled.</description> 4762 <value>1</value> 4763 </enumeratedValue> 4764 </enumeratedValues> 4765 </field> 4766 <field> 4767 <name>TXLOIE</name> 4768 <description>TX FIFO Locked Out Interrupt.</description> 4769 <bitRange>[15:15]</bitRange> 4770 <enumeratedValues> 4771 <enumeratedValue> 4772 <name>dis</name> 4773 <description>Interrupt disabled.</description> 4774 <value>0</value> 4775 </enumeratedValue> 4776 <enumeratedValue> 4777 <name>en</name> 4778 <description>Interrupt enabled.</description> 4779 <value>1</value> 4780 </enumeratedValue> 4781 </enumeratedValues> 4782 </field> 4783 </fields> 4784 </register> 4785 <register> 4786 <name>INT1</name> 4787 <description>Interrupt Status Register 1.</description> 4788 <addressOffset>0x10</addressOffset> 4789 <fields> 4790 <field> 4791 <name>RXOFI</name> 4792 <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description> 4793 <bitRange>[0:0]</bitRange> 4794 <enumeratedValues> 4795 <enumeratedValue> 4796 <name>inactive</name> 4797 <description>No Interrupt is Pending.</description> 4798 <value>0</value> 4799 </enumeratedValue> 4800 <enumeratedValue> 4801 <name>pending</name> 4802 <description>An interrupt is pending.</description> 4803 <value>1</value> 4804 </enumeratedValue> 4805 </enumeratedValues> 4806 </field> 4807 <field> 4808 <name>TXUFI</name> 4809 <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description> 4810 <bitRange>[1:1]</bitRange> 4811 <enumeratedValues> 4812 <enumeratedValue> 4813 <name>inactive</name> 4814 <description>No Interrupt is Pending.</description> 4815 <value>0</value> 4816 </enumeratedValue> 4817 <enumeratedValue> 4818 <name>pending</name> 4819 <description>An interrupt is pending.</description> 4820 <value>1</value> 4821 </enumeratedValue> 4822 </enumeratedValues> 4823 </field> 4824 </fields> 4825 </register> 4826 <register> 4827 <name>INTEN1</name> 4828 <description>Interrupt Staus Register 1.</description> 4829 <addressOffset>0x14</addressOffset> 4830 <access>read-write</access> 4831 <fields> 4832 <field> 4833 <name>RXOFIE</name> 4834 <description>Receiver Overflow Interrupt Enable.</description> 4835 <bitRange>[0:0]</bitRange> 4836 <enumeratedValues> 4837 <enumeratedValue> 4838 <name>dis</name> 4839 <description>No Interrupt is Pending.</description> 4840 <value>0</value> 4841 </enumeratedValue> 4842 <enumeratedValue> 4843 <name>en</name> 4844 <description>An interrupt is pending.</description> 4845 <value>1</value> 4846 </enumeratedValue> 4847 </enumeratedValues> 4848 </field> 4849 <field> 4850 <name>TXUFIE</name> 4851 <description>Transmit Underflow Interrupt Enable.</description> 4852 <bitRange>[1:1]</bitRange> 4853 <enumeratedValues> 4854 <enumeratedValue> 4855 <name>dis</name> 4856 <description>No Interrupt is Pending.</description> 4857 <value>0</value> 4858 </enumeratedValue> 4859 <enumeratedValue> 4860 <name>en</name> 4861 <description>An interrupt is pending.</description> 4862 <value>1</value> 4863 </enumeratedValue> 4864 </enumeratedValues> 4865 </field> 4866 </fields> 4867 </register> 4868 <register> 4869 <name>FIFO</name> 4870 <description>FIFO Configuration Register.</description> 4871 <addressOffset>0x18</addressOffset> 4872 <fields> 4873 <field> 4874 <name>RXLEN</name> 4875 <description>Receive FIFO Length.</description> 4876 <bitRange>[7:0]</bitRange> 4877 <access>read-only</access> 4878 </field> 4879 <field> 4880 <name>TXLEN</name> 4881 <description>Transmit FIFO Length.</description> 4882 <bitRange>[15:8]</bitRange> 4883 <access>read-only</access> 4884 </field> 4885 </fields> 4886 </register> 4887 <register> 4888 <name>RXCFG</name> 4889 <description>Receive Control Register 0.</description> 4890 <addressOffset>0x1C</addressOffset> 4891 <fields> 4892 <field> 4893 <name>DNR</name> 4894 <description>Do Not Respond.</description> 4895 <bitRange>[0:0]</bitRange> 4896 <enumeratedValues> 4897 <enumeratedValue> 4898 <name>respond</name> 4899 <description>Always respond to address match.</description> 4900 <value>0</value> 4901 </enumeratedValue> 4902 <enumeratedValue> 4903 <name>not_respond_rx_fifo_empty</name> 4904 <description>Do not respond to address match when RX_FIFO is not empty.</description> 4905 <value>1</value> 4906 </enumeratedValue> 4907 </enumeratedValues> 4908 </field> 4909 <field> 4910 <name>RXFSH</name> 4911 <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description> 4912 <bitRange>[7:7]</bitRange> 4913 <enumeratedValues> 4914 <enumeratedValue> 4915 <name>not_flushed</name> 4916 <description>FIFO not flushed.</description> 4917 <value>0</value> 4918 </enumeratedValue> 4919 <enumeratedValue> 4920 <name>flush</name> 4921 <description>Flush RX_FIFO.</description> 4922 <value>1</value> 4923 </enumeratedValue> 4924 </enumeratedValues> 4925 </field> 4926 <field> 4927 <name>RXTH</name> 4928 <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description> 4929 <bitRange>[11:8]</bitRange> 4930 </field> 4931 </fields> 4932 </register> 4933 <register> 4934 <name>RX</name> 4935 <description>Receive Control Register 1.</description> 4936 <addressOffset>0x20</addressOffset> 4937 <fields> 4938 <field> 4939 <name>RXCNT</name> 4940 <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description> 4941 <bitRange>[7:0]</bitRange> 4942 </field> 4943 <field> 4944 <name>RXFIFO</name> 4945 <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description> 4946 <bitRange>[11:8]</bitRange> 4947 <access>read-only</access> 4948 </field> 4949 </fields> 4950 </register> 4951 <register> 4952 <name>TXCFG</name> 4953 <description>Transmit Control Register 0.</description> 4954 <addressOffset>0x24</addressOffset> 4955 <fields> 4956 <field> 4957 <name>TXPRELD</name> 4958 <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description> 4959 <bitRange>[0:0]</bitRange> 4960 </field> 4961 <field> 4962 <name>TXRDYMMODE</name> 4963 <description>Transmit FIFO Ready Manual Mode.</description> 4964 <bitRange>[1:1]</bitRange> 4965 <enumeratedValues> 4966 <enumeratedValue> 4967 <name>en</name> 4968 <description>HW control of I2CTXRDY enabled.</description> 4969 <value>0</value> 4970 </enumeratedValue> 4971 <enumeratedValue> 4972 <name>dis</name> 4973 <description>HW control of I2CTXRDY disabled.</description> 4974 <value>1</value> 4975 </enumeratedValue> 4976 </enumeratedValues> 4977 </field> 4978 <field> 4979 <name>TXFSH</name> 4980 <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description> 4981 <bitRange>[7:7]</bitRange> 4982 <enumeratedValues> 4983 <enumeratedValue> 4984 <name>not_flushed</name> 4985 <description>FIFO not flushed.</description> 4986 <value>0</value> 4987 </enumeratedValue> 4988 <enumeratedValue> 4989 <name>flush</name> 4990 <description>Flush TX_FIFO.</description> 4991 <value>1</value> 4992 </enumeratedValue> 4993 </enumeratedValues> 4994 </field> 4995 <field> 4996 <name>TXTH</name> 4997 <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description> 4998 <bitRange>[11:8]</bitRange> 4999 </field> 5000 </fields> 5001 </register> 5002 <register> 5003 <name>TX</name> 5004 <description>Transmit Control Register 1.</description> 5005 <addressOffset>0x28</addressOffset> 5006 <fields> 5007 <field> 5008 <name>TXRDY</name> 5009 <description>Transmit FIFO Preload Ready.</description> 5010 <bitRange>[0:0]</bitRange> 5011 </field> 5012 <field> 5013 <name>TXLAST</name> 5014 <description>Transmit Lasr. Used in slave mode only. (Cleared by hardware)</description> 5015 <bitRange>[1:1]</bitRange> 5016 </field> 5017 <field> 5018 <name>TXFIFO</name> 5019 <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description> 5020 <bitRange>[11:8]</bitRange> 5021 <access>read-only</access> 5022 </field> 5023 </fields> 5024 </register> 5025 <register> 5026 <name>DATA</name> 5027 <description>Data Register.</description> 5028 <addressOffset>0x2C</addressOffset> 5029 <fields> 5030 <field> 5031 <name>DATA</name> 5032 <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description> 5033 <bitOffset>0</bitOffset> 5034 <bitWidth>8</bitWidth> 5035 </field> 5036 </fields> 5037 </register> 5038 <register> 5039 <name>MCN</name> 5040 <description>Master Control Register.</description> 5041 <addressOffset>0x30</addressOffset> 5042 <fields> 5043 <field> 5044 <name>START</name> 5045 <description>Setting this bit to 1 will start a master transfer.</description> 5046 <bitRange>[0:0]</bitRange> 5047 </field> 5048 <field> 5049 <name>RESTART</name> 5050 <description>Setting this bit to 1 will generate a repeated START.</description> 5051 <bitRange>[1:1]</bitRange> 5052 </field> 5053 <field> 5054 <name>STOP</name> 5055 <description>Setting this bit to 1 will generate a STOP condition.</description> 5056 <bitRange>[2:2]</bitRange> 5057 </field> 5058 <field> 5059 <name>SEA</name> 5060 <description>Slave Extend Address Select.</description> 5061 <bitRange>[7:7]</bitRange> 5062 <enumeratedValues> 5063 <enumeratedValue> 5064 <name>7_bits_address</name> 5065 <description>7-bit address.</description> 5066 <value>0</value> 5067 </enumeratedValue> 5068 <enumeratedValue> 5069 <name>10_bits_address</name> 5070 <description>10-bit address.</description> 5071 <value>1</value> 5072 </enumeratedValue> 5073 </enumeratedValues> 5074 </field> 5075 </fields> 5076 </register> 5077 <register> 5078 <name>CKL</name> 5079 <description>Clock Low Register.</description> 5080 <addressOffset>0x34</addressOffset> 5081 <fields> 5082 <field> 5083 <name>CKL</name> 5084 <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description> 5085 <bitRange>[8:0]</bitRange> 5086 </field> 5087 </fields> 5088 </register> 5089 <register> 5090 <name>CKH</name> 5091 <description>Clock high Register.</description> 5092 <addressOffset>0x38</addressOffset> 5093 <fields> 5094 <field> 5095 <name>CKH</name> 5096 <description>Clock High. In master mode, these bits define the SCL high period.</description> 5097 <bitRange>[8:0]</bitRange> 5098 </field> 5099 </fields> 5100 </register> 5101 <register> 5102 <name>TO</name> 5103 <description>Timeout Register</description> 5104 <addressOffset>0x40</addressOffset> 5105 <fields> 5106 <field> 5107 <name>TO</name> 5108 <description>Timeout</description> 5109 <bitRange>[15:0]</bitRange> 5110 </field> 5111 </fields> 5112 </register> 5113 <register> 5114 <name>DMA</name> 5115 <description>DMA Register.</description> 5116 <addressOffset>0x48</addressOffset> 5117 <fields> 5118 <field> 5119 <name>TXEN</name> 5120 <description>TX channel enable.</description> 5121 <bitRange>[0:0]</bitRange> 5122 <enumeratedValues> 5123 <enumeratedValue> 5124 <name>dis</name> 5125 <description>Disable.</description> 5126 <value>0</value> 5127 </enumeratedValue> 5128 <enumeratedValue> 5129 <name>en</name> 5130 <description>Enable.</description> 5131 <value>1</value> 5132 </enumeratedValue> 5133 </enumeratedValues> 5134 </field> 5135 <field> 5136 <name>RXEN</name> 5137 <description>RX channel enable.</description> 5138 <bitRange>[1:1]</bitRange> 5139 <enumeratedValues> 5140 <enumeratedValue> 5141 <name>dis</name> 5142 <description>Disable.</description> 5143 <value>0</value> 5144 </enumeratedValue> 5145 <enumeratedValue> 5146 <name>en</name> 5147 <description>Enable.</description> 5148 <value>1</value> 5149 </enumeratedValue> 5150 </enumeratedValues> 5151 </field> 5152 </fields> 5153 </register> 5154 <register> 5155 <name>SLA</name> 5156 <description>Slave Address Register.</description> 5157 <addressOffset>0x4C</addressOffset> 5158 <fields> 5159 <field> 5160 <name>SLA</name> 5161 <description>Slave Address.</description> 5162 <bitRange>[9:0]</bitRange> 5163 <enumeratedValues> 5164 <enumeratedValue> 5165 <name>dis</name> 5166 <description>Disable.</description> 5167 <value>0</value> 5168 </enumeratedValue> 5169 <enumeratedValue> 5170 <name>en</name> 5171 <description>Enable.</description> 5172 <value>1</value> 5173 </enumeratedValue> 5174 </enumeratedValues> 5175 </field> 5176 <field> 5177 <name>EA</name> 5178 <description>Extended Address Select. This bit selects whether the SLA contains a 7-bit or 10-bit address.</description> 5179 <bitRange>[15:15]</bitRange> 5180 <enumeratedValues> 5181 <enumeratedValue> 5182 <name>7_bit_address</name> 5183 <description>7-bit address select.</description> 5184 <value>0</value> 5185 </enumeratedValue> 5186 <enumeratedValue> 5187 <name>10_bit_address</name> 5188 <description>10-bit address select.</description> 5189 <value>1</value> 5190 </enumeratedValue> 5191 </enumeratedValues> 5192 </field> 5193 </fields> 5194 </register> 5195 </registers> 5196 </peripheral> 5197<!--I2C0 Inter-Integrated Circuit.--> 5198 <peripheral> 5199 <name>ICC0</name> 5200 <description>Instruction Cache Controller Registers</description> 5201 <baseAddress>0x4002A000</baseAddress> 5202 <addressBlock> 5203 <offset>0x00</offset> 5204 <size>0x1000</size> 5205 <usage>registers</usage> 5206 </addressBlock> 5207 <registers> 5208 <register> 5209 <name>CACHE_ID</name> 5210 <description>Cache ID Register.</description> 5211 <addressOffset>0x0000</addressOffset> 5212 <access>read-only</access> 5213 <fields> 5214 <field> 5215 <name>RELNUM</name> 5216 <description>Release Number. Identifies the RTL release version.</description> 5217 <bitOffset>0</bitOffset> 5218 <bitWidth>6</bitWidth> 5219 </field> 5220 <field> 5221 <name>PARTNUM</name> 5222 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 5223 <bitOffset>6</bitOffset> 5224 <bitWidth>4</bitWidth> 5225 </field> 5226 <field> 5227 <name>CCHID</name> 5228 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 5229 <bitOffset>10</bitOffset> 5230 <bitWidth>6</bitWidth> 5231 </field> 5232 </fields> 5233 </register> 5234 <register> 5235 <name>MEMCFG</name> 5236 <description>Memory Configuration Register.</description> 5237 <addressOffset>0x0004</addressOffset> 5238 <access>read-only</access> 5239 <resetValue>0x00080008</resetValue> 5240 <fields> 5241 <field> 5242 <name>CCHSZ</name> 5243 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 5244 <bitOffset>0</bitOffset> 5245 <bitWidth>16</bitWidth> 5246 </field> 5247 <field> 5248 <name>MEMSZ</name> 5249 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 5250 <bitOffset>16</bitOffset> 5251 <bitWidth>16</bitWidth> 5252 </field> 5253 </fields> 5254 </register> 5255 <register> 5256 <name>CACHE_CTRL</name> 5257 <description>Cache Control and Status Register.</description> 5258 <addressOffset>0x0100</addressOffset> 5259 <fields> 5260 <field> 5261 <name>CACHE_EN</name> 5262 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 5263 <bitOffset>0</bitOffset> 5264 <bitWidth>1</bitWidth> 5265 <enumeratedValues> 5266 <enumeratedValue> 5267 <name>dis</name> 5268 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 5269 <value>0</value> 5270 </enumeratedValue> 5271 <enumeratedValue> 5272 <name>en</name> 5273 <description>Cache Enabled.</description> 5274 <value>1</value> 5275 </enumeratedValue> 5276 </enumeratedValues> 5277 </field> 5278 <field> 5279 <name>CACHE_RDY</name> 5280 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 5281 <bitOffset>16</bitOffset> 5282 <bitWidth>1</bitWidth> 5283 <access>read-only</access> 5284 <enumeratedValues> 5285 <enumeratedValue> 5286 <name>notReady</name> 5287 <description>Not Ready.</description> 5288 <value>0</value> 5289 </enumeratedValue> 5290 <enumeratedValue> 5291 <name>ready</name> 5292 <description>Ready.</description> 5293 <value>1</value> 5294 </enumeratedValue> 5295 </enumeratedValues> 5296 </field> 5297 </fields> 5298 </register> 5299 <register> 5300 <name>INVALIDATE</name> 5301 <description>Invalidate All Registers.</description> 5302 <addressOffset>0x0700</addressOffset> 5303 <access>read-write</access> 5304 <fields> 5305 <field> 5306 <name>IA</name> 5307 <description>Invalidate.</description> 5308 <bitOffset>0</bitOffset> 5309 <bitWidth>32</bitWidth> 5310 </field> 5311 </fields> 5312 </register> 5313 </registers> 5314 </peripheral> 5315<!--ICC0 Instruction Cache Controller Registers--> 5316 <peripheral> 5317 <name>MCR</name> 5318 <description>Misc Control.</description> 5319 <baseAddress>0x40006C00</baseAddress> 5320 <addressBlock> 5321 <offset>0x00</offset> 5322 <size>0x400</size> 5323 <usage>registers</usage> 5324 </addressBlock> 5325 <registers> 5326 <register> 5327 <name>ECCEN</name> 5328 <description>ECC Enable Register</description> 5329 <addressOffset>0x00</addressOffset> 5330 <fields> 5331 <field> 5332 <name>SYSRAM0ECCEN</name> 5333 <description>ECC System RAM Enable.</description> 5334 <bitOffset>0</bitOffset> 5335 <bitWidth>1</bitWidth> 5336 <enumeratedValues> 5337 <enumeratedValue> 5338 <name>dis</name> 5339 <description>disabled.</description> 5340 <value>0</value> 5341 </enumeratedValue> 5342 <enumeratedValue> 5343 <name>en</name> 5344 <description>enabled.</description> 5345 <value>1</value> 5346 </enumeratedValue> 5347 </enumeratedValues> 5348 </field> 5349 <field> 5350 <name>SYSRAM1ECCEN</name> 5351 <description>ECC System RAM Enable.</description> 5352 <bitOffset>1</bitOffset> 5353 <bitWidth>1</bitWidth> 5354 <enumeratedValues> 5355 <enumeratedValue> 5356 <name>dis</name> 5357 <description>disabled.</description> 5358 <value>0</value> 5359 </enumeratedValue> 5360 <enumeratedValue> 5361 <name>en</name> 5362 <description>enabled.</description> 5363 <value>1</value> 5364 </enumeratedValue> 5365 </enumeratedValues> 5366 </field> 5367 <field> 5368 <name>SYSRAM2ECCEN</name> 5369 <description>ECC System RAM Enable.</description> 5370 <bitOffset>2</bitOffset> 5371 <bitWidth>1</bitWidth> 5372 <enumeratedValues> 5373 <enumeratedValue> 5374 <name>dis</name> 5375 <description>disabled.</description> 5376 <value>0</value> 5377 </enumeratedValue> 5378 <enumeratedValue> 5379 <name>en</name> 5380 <description>enabled.</description> 5381 <value>1</value> 5382 </enumeratedValue> 5383 </enumeratedValues> 5384 </field> 5385 <field> 5386 <name>SYSRAM3ECCEN</name> 5387 <description>ECC System RAM Enable.</description> 5388 <bitOffset>3</bitOffset> 5389 <bitWidth>1</bitWidth> 5390 <enumeratedValues> 5391 <enumeratedValue> 5392 <name>dis</name> 5393 <description>disabled.</description> 5394 <value>0</value> 5395 </enumeratedValue> 5396 <enumeratedValue> 5397 <name>en</name> 5398 <description>enabled.</description> 5399 <value>1</value> 5400 </enumeratedValue> 5401 </enumeratedValues> 5402 </field> 5403 <field> 5404 <name>SYSRAM4ECCEN</name> 5405 <description>ECC System RAM Enable.</description> 5406 <bitOffset>4</bitOffset> 5407 <bitWidth>1</bitWidth> 5408 <enumeratedValues> 5409 <enumeratedValue> 5410 <name>dis</name> 5411 <description>disabled.</description> 5412 <value>0</value> 5413 </enumeratedValue> 5414 <enumeratedValue> 5415 <name>en</name> 5416 <description>enabled.</description> 5417 <value>1</value> 5418 </enumeratedValue> 5419 </enumeratedValues> 5420 </field> 5421 <field> 5422 <name>FL0ECCEN</name> 5423 <description>Flash0 ECC Enable.</description> 5424 <bitOffset>11</bitOffset> 5425 <bitWidth>1</bitWidth> 5426 <enumeratedValues> 5427 <enumeratedValue> 5428 <name>dis</name> 5429 <description>disabled.</description> 5430 <value>0</value> 5431 </enumeratedValue> 5432 <enumeratedValue> 5433 <name>en</name> 5434 <description>enabled.</description> 5435 <value>1</value> 5436 </enumeratedValue> 5437 </enumeratedValues> 5438 </field> 5439 <field> 5440 <name>FL1ECCEN</name> 5441 <description>Flash1 ECC Enable.</description> 5442 <bitOffset>12</bitOffset> 5443 <bitWidth>1</bitWidth> 5444 <enumeratedValues> 5445 <enumeratedValue> 5446 <name>dis</name> 5447 <description>disabled.</description> 5448 <value>0</value> 5449 </enumeratedValue> 5450 <enumeratedValue> 5451 <name>en</name> 5452 <description>enabled.</description> 5453 <value>1</value> 5454 </enumeratedValue> 5455 </enumeratedValues> 5456 </field> 5457 </fields> 5458 </register> 5459 </registers> 5460 </peripheral> 5461<!--MCR Misc Control.--> 5462 <peripheral> 5463 <name>PWRSEQ</name> 5464 <description>Power Sequencer / Low Power Control Register.</description> 5465 <baseAddress>0x40006800</baseAddress> 5466 <addressBlock> 5467 <offset>0x00</offset> 5468 <size>0x400</size> 5469 <usage>registers</usage> 5470 </addressBlock> 5471 <registers> 5472 <register> 5473 <name>LPCN</name> 5474 <description>Low Power Control Register.</description> 5475 <addressOffset>0x00</addressOffset> 5476 <fields> 5477 <field> 5478 <name>RAMRET_EN</name> 5479 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 5480 <bitOffset>0</bitOffset> 5481 <bitWidth>2</bitWidth> 5482 </field> 5483 <field> 5484 <name>LDO_DIS</name> 5485 <description>LDO Disabled</description> 5486 <bitOffset>16</bitOffset> 5487 <bitWidth>1</bitWidth> 5488 </field> 5489 <field> 5490 <name>VCOREMON_DIS</name> 5491 <description>Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 5492 <bitOffset>20</bitOffset> 5493 <bitWidth>1</bitWidth> 5494 <enumeratedValues> 5495 <enumeratedValue> 5496 <name>en</name> 5497 <description>Enable if Bandgap is ON (default) </description> 5498 <value>0</value> 5499 </enumeratedValue> 5500 <enumeratedValue> 5501 <name>dis</name> 5502 <description>Disabled.</description> 5503 <value>1</value> 5504 </enumeratedValue> 5505 </enumeratedValues> 5506 </field> 5507 <field> 5508 <name>VDDAMON_DIS</name> 5509 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 5510 <bitOffset>22</bitOffset> 5511 <bitWidth>1</bitWidth> 5512 <enumeratedValues> 5513 <enumeratedValue> 5514 <name>en</name> 5515 <description>Enable if Bandgap is ON (default) </description> 5516 <value>0</value> 5517 </enumeratedValue> 5518 <enumeratedValue> 5519 <name>dis</name> 5520 <description>Disabled.</description> 5521 <value>1</value> 5522 </enumeratedValue> 5523 </enumeratedValues> 5524 </field> 5525 </fields> 5526 </register> 5527 <register> 5528 <name>LPWKST0</name> 5529 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 5530 <addressOffset>0x04</addressOffset> 5531 <fields> 5532 <field> 5533 <name>ST</name> 5534 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 5535 <bitOffset>0</bitOffset> 5536 <bitWidth>16</bitWidth> 5537 </field> 5538 </fields> 5539 </register> 5540 <register> 5541 <name>LPWKEN0</name> 5542 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 5543 <addressOffset>0x08</addressOffset> 5544 <fields> 5545 <field> 5546 <name>EN</name> 5547 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 5548 <bitOffset>0</bitOffset> 5549 <bitWidth>16</bitWidth> 5550 </field> 5551 </fields> 5552 </register> 5553 <register> 5554 <name>LPWKST1</name> 5555 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 5556 <addressOffset>0x0C</addressOffset> 5557 <fields> 5558 <field> 5559 <name>ST</name> 5560 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 5561 <bitOffset>0</bitOffset> 5562 <bitWidth>11</bitWidth> 5563 </field> 5564 </fields> 5565 </register> 5566 <register> 5567 <name>LPWKEN1</name> 5568 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 5569 <addressOffset>0x10</addressOffset> 5570 <fields> 5571 <field> 5572 <name>EN</name> 5573 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 5574 <bitOffset>0</bitOffset> 5575 <bitWidth>11</bitWidth> 5576 </field> 5577 </fields> 5578 </register> 5579 <register> 5580 <name>LPPWKST</name> 5581 <description>Low Power Peripheral Wakeup Status Register.</description> 5582 <addressOffset>0x30</addressOffset> 5583 <fields> 5584 <field> 5585 <name>BBMOD</name> 5586 <description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description> 5587 <bitOffset>16</bitOffset> 5588 <bitWidth>1</bitWidth> 5589 </field> 5590 <field> 5591 <name>RST</name> 5592 <description>Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup</description> 5593 <bitOffset>17</bitOffset> 5594 <bitWidth>1</bitWidth> 5595 </field> 5596 <field> 5597 <name>SDMA1</name> 5598 <description>Smart DMA (1) Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transitions from low to high or high to low</description> 5599 <bitOffset>18</bitOffset> 5600 <bitWidth>1</bitWidth> 5601 </field> 5602 </fields> 5603 </register> 5604 <register> 5605 <name>LPMEMSD</name> 5606 <description>Low Power Memory Shutdown Control.</description> 5607 <addressOffset>0x40</addressOffset> 5608 <fields> 5609 <field> 5610 <name>RAM0</name> 5611 <description>System RAM block 0 Shut Down.</description> 5612 <bitOffset>0</bitOffset> 5613 <bitWidth>1</bitWidth> 5614 <enumeratedValues> 5615 <enumeratedValue> 5616 <name>normal</name> 5617 <description>Normal Operating Mode.</description> 5618 <value>0</value> 5619 </enumeratedValue> 5620 <enumeratedValue> 5621 <name>shutdown</name> 5622 <description>Shutdown Mode.</description> 5623 <value>1</value> 5624 </enumeratedValue> 5625 </enumeratedValues> 5626 </field> 5627 <field> 5628 <name>RAM1</name> 5629 <description>System RAM block 1 Shut Down.</description> 5630 <bitOffset>1</bitOffset> 5631 <bitWidth>1</bitWidth> 5632 <enumeratedValues> 5633 <enumeratedValue> 5634 <name>normal</name> 5635 <description>Normal Operating Mode.</description> 5636 <value>0</value> 5637 </enumeratedValue> 5638 <enumeratedValue> 5639 <name>shutdown</name> 5640 <description>Shutdown Mode.</description> 5641 <value>1</value> 5642 </enumeratedValue> 5643 </enumeratedValues> 5644 </field> 5645 <field> 5646 <name>RAM2</name> 5647 <description>System RAM block 2 Shut Down.</description> 5648 <bitOffset>2</bitOffset> 5649 <bitWidth>1</bitWidth> 5650 <enumeratedValues> 5651 <enumeratedValue> 5652 <name>normal</name> 5653 <description>Normal Operating Mode.</description> 5654 <value>0</value> 5655 </enumeratedValue> 5656 <enumeratedValue> 5657 <name>shutdown</name> 5658 <description>Shutdown Mode.</description> 5659 <value>1</value> 5660 </enumeratedValue> 5661 </enumeratedValues> 5662 </field> 5663 <field> 5664 <name>RAM3</name> 5665 <description>System RAM block 3 Shut Down.</description> 5666 <bitOffset>3</bitOffset> 5667 <bitWidth>1</bitWidth> 5668 <enumeratedValues> 5669 <enumeratedValue> 5670 <name>normal</name> 5671 <description>Normal Operating Mode.</description> 5672 <value>0</value> 5673 </enumeratedValue> 5674 <enumeratedValue> 5675 <name>shutdown</name> 5676 <description>Shutdown Mode.</description> 5677 <value>1</value> 5678 </enumeratedValue> 5679 </enumeratedValues> 5680 </field> 5681 <field> 5682 <name>RAM4</name> 5683 <description>System RAM block 4 Shut Down.</description> 5684 <bitOffset>4</bitOffset> 5685 <bitWidth>1</bitWidth> 5686 <enumeratedValues> 5687 <enumeratedValue> 5688 <name>normal</name> 5689 <description>Normal Operating Mode.</description> 5690 <value>0</value> 5691 </enumeratedValue> 5692 <enumeratedValue> 5693 <name>shutdown</name> 5694 <description>Shutdown Mode.</description> 5695 <value>1</value> 5696 </enumeratedValue> 5697 </enumeratedValues> 5698 </field> 5699 <field> 5700 <name>ICACHE</name> 5701 <description>Instruction Cache RAM Shut Down.</description> 5702 <bitOffset>7</bitOffset> 5703 <bitWidth>1</bitWidth> 5704 <enumeratedValues> 5705 <enumeratedValue> 5706 <name>normal</name> 5707 <description>Normal Operating Mode.</description> 5708 <value>0</value> 5709 </enumeratedValue> 5710 <enumeratedValue> 5711 <name>shutdown</name> 5712 <description>Shutdown Mode.</description> 5713 <value>1</value> 5714 </enumeratedValue> 5715 </enumeratedValues> 5716 </field> 5717 <field> 5718 <name>ICACHEXIP</name> 5719 <description>XiP Instruction Cache RAM Shut Down.</description> 5720 <bitOffset>8</bitOffset> 5721 <bitWidth>1</bitWidth> 5722 <enumeratedValues> 5723 <enumeratedValue> 5724 <name>normal</name> 5725 <description>Normal Operating Mode.</description> 5726 <value>0</value> 5727 </enumeratedValue> 5728 <enumeratedValue> 5729 <name>shutdown</name> 5730 <description>Shutdown Mode.</description> 5731 <value>1</value> 5732 </enumeratedValue> 5733 </enumeratedValues> 5734 </field> 5735 <field> 5736 <name>ROM</name> 5737 <description>ROM Shut Down.</description> 5738 <bitOffset>12</bitOffset> 5739 <bitWidth>1</bitWidth> 5740 <enumeratedValues> 5741 <enumeratedValue> 5742 <name>normal</name> 5743 <description>Normal Operating Mode.</description> 5744 <value>0</value> 5745 </enumeratedValue> 5746 <enumeratedValue> 5747 <name>shutdown</name> 5748 <description>Shutdown Mode.</description> 5749 <value>1</value> 5750 </enumeratedValue> 5751 </enumeratedValues> 5752 </field> 5753 </fields> 5754 </register> 5755 <register> 5756 <name>GP0</name> 5757 <description>Back Up General Purpose Register 0</description> 5758 <addressOffset>0x48</addressOffset> 5759 </register> 5760 <register> 5761 <name>GP1</name> 5762 <description>Back Up General Purpose Register 1</description> 5763 <addressOffset>0x4C</addressOffset> 5764 </register> 5765 </registers> 5766 </peripheral> 5767<!--PWRSEQ Power Sequencer / Low Power Control Register.--> 5768 <peripheral> 5769 <name>SFE</name> 5770 <description>Serial Flash Emulator.</description> 5771 <baseAddress>0x400A0000</baseAddress> 5772 <addressBlock> 5773 <offset>0x00</offset> 5774 <size>0x1000</size> 5775 <usage>registers</usage> 5776 </addressBlock> 5777 <registers> 5778 <register> 5779 <name>CFG</name> 5780 <description>SFE Configuration Register.</description> 5781 <addressOffset>0x0400</addressOffset> 5782 <size>32</size> 5783 <fields> 5784 <field> 5785 <name>DRLE</name> 5786 <description>Data Rise Launch Edge Enable.</description> 5787 <bitOffset>0</bitOffset> 5788 <bitWidth>1</bitWidth> 5789 </field> 5790 <field> 5791 <name>FLOCK</name> 5792 <description>Flash Lock.</description> 5793 <bitOffset>15</bitOffset> 5794 <bitWidth>1</bitWidth> 5795 </field> 5796 <field> 5797 <name>RD_EN</name> 5798 <description>RAM Read Enable.</description> 5799 <bitOffset>16</bitOffset> 5800 <bitWidth>1</bitWidth> 5801 </field> 5802 <field> 5803 <name>WR_EN</name> 5804 <description>RAM Write Enable.</description> 5805 <bitOffset>17</bitOffset> 5806 <bitWidth>1</bitWidth> 5807 </field> 5808 <field> 5809 <name>RRLOCK</name> 5810 <description>RAM Read Lock.</description> 5811 <bitOffset>22</bitOffset> 5812 <bitWidth>1</bitWidth> 5813 </field> 5814 <field> 5815 <name>RWLOCK</name> 5816 <description>RAM Write Lock.</description> 5817 <bitOffset>23</bitOffset> 5818 <bitWidth>1</bitWidth> 5819 </field> 5820 </fields> 5821 </register> 5822 <register> 5823 <name>HFSA</name> 5824 <description>SFE Host Flash Start Address Register.</description> 5825 <addressOffset>0x0408</addressOffset> 5826 <fields> 5827 <field> 5828 <name>HFSA</name> 5829 <description> Serial Flash Host Flash Start Address.</description> 5830 <bitOffset>10</bitOffset> 5831 <bitWidth>22</bitWidth> 5832 </field> 5833 </fields> 5834 </register> 5835 <register> 5836 <name>HRSA</name> 5837 <description>SFE Host RAM Start Address Register.</description> 5838 <addressOffset>0x040C</addressOffset> 5839 <fields> 5840 <field> 5841 <name>HRSA</name> 5842 <description> Serial Flash Host RAM Start Address.</description> 5843 <bitOffset>10</bitOffset> 5844 <bitWidth>22</bitWidth> 5845 </field> 5846 </fields> 5847 </register> 5848 <register> 5849 <name>SFDP_SBA</name> 5850 <description>SFE Discoverable Parameter System Base Register.</description> 5851 <addressOffset>0x0410</addressOffset> 5852 <fields> 5853 <field> 5854 <name>SFDP_SBA</name> 5855 <description> SFDP upper 24 bits System Base Address.</description> 5856 <bitOffset>8</bitOffset> 5857 <bitWidth>24</bitWidth> 5858 </field> 5859 </fields> 5860 </register> 5861 <register> 5862 <name>FLASH_SBA</name> 5863 <description>Flash System Base Address Register.</description> 5864 <addressOffset>0x0414</addressOffset> 5865 <fields> 5866 <field> 5867 <name>FLASH_SBA</name> 5868 <description> FLASH upper 22 bits System Base Address.</description> 5869 <bitOffset>10</bitOffset> 5870 <bitWidth>22</bitWidth> 5871 </field> 5872 </fields> 5873 </register> 5874 <register> 5875 <name>FLASH_STA</name> 5876 <description>Flash System Top Address Register.</description> 5877 <addressOffset>0x0418</addressOffset> 5878 <fields> 5879 <field> 5880 <name>FLASH_STA</name> 5881 <description> FLASH upper 22 bits System Top Address.</description> 5882 <bitOffset>10</bitOffset> 5883 <bitWidth>22</bitWidth> 5884 </field> 5885 </fields> 5886 </register> 5887 <register> 5888 <name>RAM_SBA</name> 5889 <description>RAM System Base Address Register.</description> 5890 <addressOffset>0x041C</addressOffset> 5891 <fields> 5892 <field> 5893 <name>RAM_SBA</name> 5894 <description> RAM upper 22 bits System Base Address.</description> 5895 <bitOffset>10</bitOffset> 5896 <bitWidth>22</bitWidth> 5897 </field> 5898 </fields> 5899 </register> 5900 <register> 5901 <name>RAM_STA</name> 5902 <description>RAM System Top Address Register.</description> 5903 <addressOffset>0x0420</addressOffset> 5904 <fields> 5905 <field> 5906 <name>RAM_STA</name> 5907 <description> RAM upper 22 bits System Top Address.</description> 5908 <bitOffset>10</bitOffset> 5909 <bitWidth>22</bitWidth> 5910 </field> 5911 </fields> 5912 </register> 5913 </registers> 5914 </peripheral> 5915<!--SFE Serial Flash Emulator.--> 5916 <peripheral> 5917 <name>SIR</name> 5918 <description>System Initialization Registers.</description> 5919 <baseAddress>0x40000400</baseAddress> 5920 <access>read-only</access> 5921 <addressBlock> 5922 <offset>0x00</offset> 5923 <size>0x400</size> 5924 <usage>registers</usage> 5925 </addressBlock> 5926 <registers> 5927 <register> 5928 <name>SISTAT</name> 5929 <description>System Initialization Status Register.</description> 5930 <addressOffset>0x00</addressOffset> 5931 <access>read-only</access> 5932 <fields> 5933 <field> 5934 <name>MAGIC</name> 5935 <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> 5936 <bitOffset>0</bitOffset> 5937 <bitWidth>1</bitWidth> 5938 <access>read-only</access> 5939 <enumeratedValues> 5940 <usage>read</usage> 5941 <enumeratedValue> 5942 <name>magicNotSet</name> 5943 <description>Magic word was not set (OTP has not been initialized properly).</description> 5944 <value>0</value> 5945 </enumeratedValue> 5946 <enumeratedValue> 5947 <name>magicSet</name> 5948 <description>Magic word was set (OTP contains valid settings).</description> 5949 <value>1</value> 5950 </enumeratedValue> 5951 </enumeratedValues> 5952 </field> 5953 <field> 5954 <name>CRCERR</name> 5955 <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> 5956 <bitOffset>1</bitOffset> 5957 <bitWidth>1</bitWidth> 5958 <access>read-only</access> 5959 <enumeratedValues> 5960 <usage>read</usage> 5961 <enumeratedValue> 5962 <name>noError</name> 5963 <description>No CRC errors occurred during the read of the OTP memory block.</description> 5964 <value>0</value> 5965 </enumeratedValue> 5966 <enumeratedValue> 5967 <name>error</name> 5968 <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> 5969 <value>1</value> 5970 </enumeratedValue> 5971 </enumeratedValues> 5972 </field> 5973 </fields> 5974 </register> 5975 <register> 5976 <name>ERRADDR</name> 5977 <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> 5978 <addressOffset>0x04</addressOffset> 5979 <access>read-only</access> 5980 <fields> 5981 <field> 5982 <name>ERRADDR</name> 5983 <bitOffset>0</bitOffset> 5984 <bitWidth>32</bitWidth> 5985 </field> 5986 </fields> 5987 </register> 5988 <register> 5989 <name>FSTAT</name> 5990 <description>funcstat register.</description> 5991 <addressOffset>0x100</addressOffset> 5992 <access>read-only</access> 5993 <fields> 5994 <field> 5995 <name>FPU</name> 5996 <description>FPU Function.</description> 5997 <bitOffset>0</bitOffset> 5998 <bitWidth>1</bitWidth> 5999 <enumeratedValues> 6000 <enumeratedValue> 6001 <name>no</name> 6002 <value>0</value> 6003 </enumeratedValue> 6004 <enumeratedValue> 6005 <name>yes</name> 6006 <value>1</value> 6007 </enumeratedValue> 6008 </enumeratedValues> 6009 </field> 6010 <field> 6011 <name>NMI</name> 6012 <description>NMI function.</description> 6013 <bitOffset>11</bitOffset> 6014 <bitWidth>1</bitWidth> 6015 <enumeratedValues> 6016 <enumeratedValue> 6017 <name>no</name> 6018 <value>0</value> 6019 </enumeratedValue> 6020 <enumeratedValue> 6021 <name>yes</name> 6022 <value>1</value> 6023 </enumeratedValue> 6024 </enumeratedValues> 6025 </field> 6026 <field> 6027 <name>SFES</name> 6028 <description>SFES function.</description> 6029 <bitOffset>12</bitOffset> 6030 <bitWidth>1</bitWidth> 6031 <enumeratedValues> 6032 <enumeratedValue> 6033 <name>no</name> 6034 <value>0</value> 6035 </enumeratedValue> 6036 <enumeratedValue> 6037 <name>yes</name> 6038 <value>1</value> 6039 </enumeratedValue> 6040 </enumeratedValues> 6041 </field> 6042 </fields> 6043 </register> 6044 <register> 6045 <name>SFSTAT</name> 6046 <description>secfuncstat register.</description> 6047 <addressOffset>0x104</addressOffset> 6048 <access>read-only</access> 6049 <fields> 6050 <field> 6051 <name>TRNG</name> 6052 <description>TRNG function.</description> 6053 <bitOffset>2</bitOffset> 6054 <bitWidth>1</bitWidth> 6055 <enumeratedValues> 6056 <enumeratedValue> 6057 <name>no</name> 6058 <value>0</value> 6059 </enumeratedValue> 6060 <enumeratedValue> 6061 <name>yes</name> 6062 <value>1</value> 6063 </enumeratedValue> 6064 </enumeratedValues> 6065 </field> 6066 <field> 6067 <name>AES</name> 6068 <description>AES function.</description> 6069 <bitOffset>3</bitOffset> 6070 <bitWidth>1</bitWidth> 6071 <enumeratedValues> 6072 <enumeratedValue> 6073 <name>no</name> 6074 <value>0</value> 6075 </enumeratedValue> 6076 <enumeratedValue> 6077 <name>yes</name> 6078 <value>1</value> 6079 </enumeratedValue> 6080 </enumeratedValues> 6081 </field> 6082 <field> 6083 <name>SHA</name> 6084 <description>SHA function.</description> 6085 <bitOffset>4</bitOffset> 6086 <bitWidth>1</bitWidth> 6087 <enumeratedValues> 6088 <enumeratedValue> 6089 <name>no</name> 6090 <value>0</value> 6091 </enumeratedValue> 6092 <enumeratedValue> 6093 <name>yes</name> 6094 <value>1</value> 6095 </enumeratedValue> 6096 </enumeratedValues> 6097 </field> 6098 </fields> 6099 </register> 6100 </registers> 6101 </peripheral> 6102<!--SIR System Initialization Registers.--> 6103 <peripheral> 6104 <name>SMON</name> 6105 <description>The Security Monitor block used to monitor system threat conditions.</description> 6106 <baseAddress>0x40004000</baseAddress> 6107 <addressBlock> 6108 <offset>0x00</offset> 6109 <size>0x400</size> 6110 <usage>registers</usage> 6111 </addressBlock> 6112 <registers> 6113 <register> 6114 <name>EXTSCN</name> 6115 <description>External Sensor Control Register.</description> 6116 <addressOffset>0x00</addressOffset> 6117 <resetMask>0x3800FFC0</resetMask> 6118 <fields> 6119 <field> 6120 <name>EXTS_EN0</name> 6121 <description>External Sensor Enable for input/output pair 0.</description> 6122 <bitOffset>0</bitOffset> 6123 <bitWidth>1</bitWidth> 6124 <enumeratedValues> 6125 <enumeratedValue> 6126 <name>dis</name> 6127 <description>Disable.</description> 6128 <value>0</value> 6129 </enumeratedValue> 6130 <enumeratedValue> 6131 <name>en</name> 6132 <description>Enable.</description> 6133 <value>1</value> 6134 </enumeratedValue> 6135 </enumeratedValues> 6136 </field> 6137 <field> 6138 <name>EXTS_EN1</name> 6139 <description>External Sensor Enable for input/output pair 1.</description> 6140 <bitOffset>1</bitOffset> 6141 <bitWidth>1</bitWidth> 6142 <enumeratedValues> 6143 <enumeratedValue> 6144 <name>dis</name> 6145 <description>Disable.</description> 6146 <value>0</value> 6147 </enumeratedValue> 6148 <enumeratedValue> 6149 <name>en</name> 6150 <description>Enable.</description> 6151 <value>1</value> 6152 </enumeratedValue> 6153 </enumeratedValues> 6154 </field> 6155 <field> 6156 <name>EXTS_EN2</name> 6157 <description>External Sensor Enable for input/output pair 2.</description> 6158 <bitOffset>2</bitOffset> 6159 <bitWidth>1</bitWidth> 6160 <enumeratedValues> 6161 <enumeratedValue> 6162 <name>dis</name> 6163 <description>Disable.</description> 6164 <value>0</value> 6165 </enumeratedValue> 6166 <enumeratedValue> 6167 <name>en</name> 6168 <description>Enable.</description> 6169 <value>1</value> 6170 </enumeratedValue> 6171 </enumeratedValues> 6172 </field> 6173 <field> 6174 <name>EXTS_EN3</name> 6175 <description>External Sensor Enable for input/output pair 3.</description> 6176 <bitOffset>3</bitOffset> 6177 <bitWidth>1</bitWidth> 6178 <enumeratedValues> 6179 <enumeratedValue> 6180 <name>dis</name> 6181 <description>Disable.</description> 6182 <value>0</value> 6183 </enumeratedValue> 6184 <enumeratedValue> 6185 <name>en</name> 6186 <description>Enable.</description> 6187 <value>1</value> 6188 </enumeratedValue> 6189 </enumeratedValues> 6190 </field> 6191 <field> 6192 <name>EXTS_EN4</name> 6193 <description>External Sensor Enable for input/output pair 4.</description> 6194 <bitOffset>4</bitOffset> 6195 <bitWidth>1</bitWidth> 6196 <enumeratedValues> 6197 <enumeratedValue> 6198 <name>dis</name> 6199 <description>Disable.</description> 6200 <value>0</value> 6201 </enumeratedValue> 6202 <enumeratedValue> 6203 <name>en</name> 6204 <description>Enable.</description> 6205 <value>1</value> 6206 </enumeratedValue> 6207 </enumeratedValues> 6208 </field> 6209 <field> 6210 <name>EXTS_EN5</name> 6211 <description>External Sensor Enable for input/output pair 5.</description> 6212 <bitOffset>5</bitOffset> 6213 <bitWidth>1</bitWidth> 6214 <enumeratedValues> 6215 <enumeratedValue> 6216 <name>dis</name> 6217 <description>Disable.</description> 6218 <value>0</value> 6219 </enumeratedValue> 6220 <enumeratedValue> 6221 <name>en</name> 6222 <description>Enable.</description> 6223 <value>1</value> 6224 </enumeratedValue> 6225 </enumeratedValues> 6226 </field> 6227 <field> 6228 <name>EXTCNT</name> 6229 <description>External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.</description> 6230 <bitOffset>16</bitOffset> 6231 <bitWidth>5</bitWidth> 6232 </field> 6233 <field> 6234 <name>EXTFRQ</name> 6235 <description>External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.</description> 6236 <bitOffset>21</bitOffset> 6237 <bitWidth>3</bitWidth> 6238 <enumeratedValues> 6239 <enumeratedValue> 6240 <name>freq2000Hz</name> 6241 <description>Div 4 (2000Hz).</description> 6242 <value>0</value> 6243 </enumeratedValue> 6244 <enumeratedValue> 6245 <name>freq1000Hz</name> 6246 <description>Div 8 (1000Hz).</description> 6247 <value>1</value> 6248 </enumeratedValue> 6249 <enumeratedValue> 6250 <name>freq500Hz</name> 6251 <description>Div 16 (500Hz).</description> 6252 <value>2</value> 6253 </enumeratedValue> 6254 <enumeratedValue> 6255 <name>freq250Hz</name> 6256 <description>Div 32 (250Hz).</description> 6257 <value>3</value> 6258 </enumeratedValue> 6259 <enumeratedValue> 6260 <name>freq125Hz</name> 6261 <description>Div 64 (125Hz).</description> 6262 <value>4</value> 6263 </enumeratedValue> 6264 <enumeratedValue> 6265 <name>freq63Hz</name> 6266 <description>Div 128 (63Hz).</description> 6267 <value>5</value> 6268 </enumeratedValue> 6269 <enumeratedValue> 6270 <name>freq31Hz</name> 6271 <description>Div 256 (31Hz).</description> 6272 <value>6</value> 6273 </enumeratedValue> 6274 <enumeratedValue> 6275 <name>RFU</name> 6276 <description>Reserved. Do not use.</description> 6277 <value>7</value> 6278 </enumeratedValue> 6279 </enumeratedValues> 6280 </field> 6281 <field> 6282 <name>DIVCLK</name> 6283 <description>Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: 6284 If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.</description> 6285 <bitOffset>24</bitOffset> 6286 <bitWidth>3</bitWidth> 6287 <enumeratedValues> 6288 <enumeratedValue> 6289 <name>div1</name> 6290 <description>Divide by 1 (8000 Hz).</description> 6291 <value>0</value> 6292 </enumeratedValue> 6293 <enumeratedValue> 6294 <name>div2</name> 6295 <description>Divide by 2 (4000 Hz).</description> 6296 <value>1</value> 6297 </enumeratedValue> 6298 <enumeratedValue> 6299 <name>div4</name> 6300 <description>Divide by 4 (2000 Hz).</description> 6301 <value>2</value> 6302 </enumeratedValue> 6303 <enumeratedValue> 6304 <name>div8</name> 6305 <description>Divide by 8 (1000 Hz).</description> 6306 <value>3</value> 6307 </enumeratedValue> 6308 <enumeratedValue> 6309 <name>div16</name> 6310 <description>Divide by 16 (500 Hz).</description> 6311 <value>4</value> 6312 </enumeratedValue> 6313 <enumeratedValue> 6314 <name>div32</name> 6315 <description>Divide by 32 (250 Hz).</description> 6316 <value>5</value> 6317 </enumeratedValue> 6318 <enumeratedValue> 6319 <name>div64</name> 6320 <description>Divide by 64 (125 Hz).</description> 6321 <value>6</value> 6322 </enumeratedValue> 6323 </enumeratedValues> 6324 </field> 6325 <field> 6326 <name>BUSY</name> 6327 <description>Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.</description> 6328 <bitOffset>30</bitOffset> 6329 <bitWidth>1</bitWidth> 6330 <access>read-only</access> 6331 <enumeratedValues> 6332 <enumeratedValue> 6333 <name>idle</name> 6334 <description>Idle.</description> 6335 <value>0</value> 6336 </enumeratedValue> 6337 <enumeratedValue> 6338 <name>busy</name> 6339 <description>Update in Progress.</description> 6340 <value>1</value> 6341 </enumeratedValue> 6342 </enumeratedValues> 6343 </field> 6344 <field> 6345 <name>LOCK</name> 6346 <description>Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 6347 <bitOffset>31</bitOffset> 6348 <bitWidth>1</bitWidth> 6349 <enumeratedValues> 6350 <enumeratedValue> 6351 <name>unlocked</name> 6352 <description>Unlocked.</description> 6353 <value>0</value> 6354 </enumeratedValue> 6355 <enumeratedValue> 6356 <name>locked</name> 6357 <description>Locked.</description> 6358 <value>1</value> 6359 </enumeratedValue> 6360 </enumeratedValues> 6361 </field> 6362 </fields> 6363 </register> 6364 <register> 6365 <name>INTSCN</name> 6366 <description>Internal Sensor Control Register.</description> 6367 <addressOffset>0x04</addressOffset> 6368 <resetMask>0x7F00FFF7</resetMask> 6369 <fields> 6370 <field> 6371 <name>SHIELD_EN</name> 6372 <description>Die Shield Enable.</description> 6373 <bitOffset>0</bitOffset> 6374 <bitWidth>1</bitWidth> 6375 <enumeratedValues> 6376 <enumeratedValue> 6377 <name>dis</name> 6378 <description>Disable.</description> 6379 <value>0</value> 6380 </enumeratedValue> 6381 <enumeratedValue> 6382 <name>en</name> 6383 <description>Enable.</description> 6384 <value>1</value> 6385 </enumeratedValue> 6386 </enumeratedValues> 6387 </field> 6388 <field> 6389 <name>TEMP_EN</name> 6390 <description>Temperature Sensor Enable.</description> 6391 <bitOffset>1</bitOffset> 6392 <bitWidth>1</bitWidth> 6393 <enumeratedValues> 6394 <enumeratedValue> 6395 <name>dis</name> 6396 <description>Disable.</description> 6397 <value>0</value> 6398 </enumeratedValue> 6399 <enumeratedValue> 6400 <name>en</name> 6401 <description>Enable.</description> 6402 <value>1</value> 6403 </enumeratedValue> 6404 </enumeratedValues> 6405 </field> 6406 <field> 6407 <name>VBAT_EN</name> 6408 <description>Battery Monitor Enable.</description> 6409 <bitOffset>2</bitOffset> 6410 <bitWidth>1</bitWidth> 6411 <enumeratedValues> 6412 <enumeratedValue> 6413 <name>dis</name> 6414 <description>Disable.</description> 6415 <value>0</value> 6416 </enumeratedValue> 6417 <enumeratedValue> 6418 <name>en</name> 6419 <description>Enable.</description> 6420 <value>1</value> 6421 </enumeratedValue> 6422 </enumeratedValues> 6423 </field> 6424 <field> 6425 <name>DFD_EN</name> 6426 <description>Digital Fault Dector Enable</description> 6427 <bitOffset>3</bitOffset> 6428 <bitWidth>1</bitWidth> 6429 </field> 6430 <field> 6431 <name>DFD_NMI</name> 6432 <description>Digital Fault NMI Enable</description> 6433 <bitOffset>4</bitOffset> 6434 <bitWidth>1</bitWidth> 6435 </field> 6436 <field> 6437 <name>DFD_STDBY</name> 6438 <description>Digital Fault Dector Stand by Enable</description> 6439 <bitOffset>8</bitOffset> 6440 <bitWidth>1</bitWidth> 6441 </field> 6442 <field> 6443 <name>PUF_TRIM_ERASE</name> 6444 <description>Erase puf trim Enable</description> 6445 <bitOffset>10</bitOffset> 6446 <bitWidth>1</bitWidth> 6447 </field> 6448 <field> 6449 <name>LOTEMP_SEL</name> 6450 <description>Low Temperature Detection Select.</description> 6451 <bitOffset>16</bitOffset> 6452 <bitWidth>1</bitWidth> 6453 <enumeratedValues> 6454 <enumeratedValue> 6455 <name>neg50C</name> 6456 <description>-50 degrees C.</description> 6457 <value>0</value> 6458 </enumeratedValue> 6459 <enumeratedValue> 6460 <name>neg30C</name> 6461 <description>-30 degrees C.</description> 6462 <value>1</value> 6463 </enumeratedValue> 6464 </enumeratedValues> 6465 </field> 6466 <field> 6467 <name>VCORELOEN</name> 6468 <description>VCORE Undervoltage Detect Enable.</description> 6469 <bitOffset>18</bitOffset> 6470 <bitWidth>1</bitWidth> 6471 <enumeratedValues> 6472 <enumeratedValue> 6473 <name>dis</name> 6474 <description>Disable.</description> 6475 <value>0</value> 6476 </enumeratedValue> 6477 <enumeratedValue> 6478 <name>en</name> 6479 <description>Enable.</description> 6480 <value>1</value> 6481 </enumeratedValue> 6482 </enumeratedValues> 6483 </field> 6484 <field> 6485 <name>VCOREHIEN</name> 6486 <description>VCORE Overvoltage Detect Enable.</description> 6487 <bitOffset>19</bitOffset> 6488 <bitWidth>1</bitWidth> 6489 <enumeratedValues> 6490 <enumeratedValue> 6491 <name>dis</name> 6492 <description>Disable.</description> 6493 <value>0</value> 6494 </enumeratedValue> 6495 <enumeratedValue> 6496 <name>en</name> 6497 <description>Enable.</description> 6498 <value>1</value> 6499 </enumeratedValue> 6500 </enumeratedValues> 6501 </field> 6502 <field> 6503 <name>VDDLOEN</name> 6504 <description>VDD Undervoltage Detect Enable.</description> 6505 <bitOffset>20</bitOffset> 6506 <bitWidth>1</bitWidth> 6507 <enumeratedValues> 6508 <enumeratedValue> 6509 <name>dis</name> 6510 <description>Disable.</description> 6511 <value>0</value> 6512 </enumeratedValue> 6513 <enumeratedValue> 6514 <name>en</name> 6515 <description>Enable.</description> 6516 <value>1</value> 6517 </enumeratedValue> 6518 </enumeratedValues> 6519 </field> 6520 <field> 6521 <name>VDDHIEN</name> 6522 <description>VDD Overvoltage Detect Enable.</description> 6523 <bitOffset>21</bitOffset> 6524 <bitWidth>1</bitWidth> 6525 <enumeratedValues> 6526 <enumeratedValue> 6527 <name>dis</name> 6528 <description>Disable.</description> 6529 <value>0</value> 6530 </enumeratedValue> 6531 <enumeratedValue> 6532 <name>en</name> 6533 <description>Enable.</description> 6534 <value>1</value> 6535 </enumeratedValue> 6536 </enumeratedValues> 6537 </field> 6538 <field> 6539 <name>VGLEN</name> 6540 <description>Voltage Glitch Detection Enable.</description> 6541 <bitOffset>22</bitOffset> 6542 <bitWidth>1</bitWidth> 6543 <enumeratedValues> 6544 <enumeratedValue> 6545 <name>dis</name> 6546 <description>Disable.</description> 6547 <value>0</value> 6548 </enumeratedValue> 6549 <enumeratedValue> 6550 <name>en</name> 6551 <description>Enable.</description> 6552 <value>1</value> 6553 </enumeratedValue> 6554 </enumeratedValues> 6555 </field> 6556 <field> 6557 <name>LOCK</name> 6558 <description>Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 6559 <bitOffset>31</bitOffset> 6560 <bitWidth>1</bitWidth> 6561 <enumeratedValues> 6562 <enumeratedValue> 6563 <name>unlocked</name> 6564 <description>Unlocked.</description> 6565 <value>0</value> 6566 </enumeratedValue> 6567 <enumeratedValue> 6568 <name>locked</name> 6569 <description>Locked.</description> 6570 <value>1</value> 6571 </enumeratedValue> 6572 </enumeratedValues> 6573 </field> 6574 </fields> 6575 </register> 6576 <register> 6577 <name>SECALM</name> 6578 <description>Security Alarm Register.</description> 6579 <addressOffset>0x08</addressOffset> 6580 <resetValue>0x00000000</resetValue> 6581 <resetMask>0x00000000</resetMask> 6582 <fields> 6583 <field> 6584 <name>DRS</name> 6585 <description>Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.</description> 6586 <bitOffset>0</bitOffset> 6587 <bitWidth>1</bitWidth> 6588 <enumeratedValues> 6589 <enumeratedValue> 6590 <name>complete</name> 6591 <description>No operation/complete.</description> 6592 <value>0</value> 6593 </enumeratedValue> 6594 <enumeratedValue> 6595 <name>start</name> 6596 <description>Start operation.</description> 6597 <value>1</value> 6598 </enumeratedValue> 6599 </enumeratedValues> 6600 </field> 6601 <field> 6602 <name>KEYWIPE</name> 6603 <description>Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.</description> 6604 <bitOffset>1</bitOffset> 6605 <bitWidth>1</bitWidth> 6606 <enumeratedValues> 6607 <enumeratedValue> 6608 <name>complete</name> 6609 <description>No operation/complete.</description> 6610 <value>0</value> 6611 </enumeratedValue> 6612 <enumeratedValue> 6613 <name>start</name> 6614 <description>Start operation.</description> 6615 <value>1</value> 6616 </enumeratedValue> 6617 </enumeratedValues> 6618 </field> 6619 <field> 6620 <name>SHIELDF</name> 6621 <description>Die Shield Flag.</description> 6622 <bitOffset>2</bitOffset> 6623 <bitWidth>1</bitWidth> 6624 <enumeratedValues> 6625 <enumeratedValue> 6626 <name>noEvent</name> 6627 <description>The event has not occurred.</description> 6628 <value>0</value> 6629 </enumeratedValue> 6630 <enumeratedValue> 6631 <name>occurred</name> 6632 <description>The event has occurred.</description> 6633 <value>1</value> 6634 </enumeratedValue> 6635 </enumeratedValues> 6636 </field> 6637 <field> 6638 <name>LOTEMP</name> 6639 <description>Low Temperature Detect.</description> 6640 <bitOffset>3</bitOffset> 6641 <bitWidth>1</bitWidth> 6642 <enumeratedValues> 6643 <enumeratedValue> 6644 <name>noEvent</name> 6645 <description>The event has not occurred.</description> 6646 <value>0</value> 6647 </enumeratedValue> 6648 <enumeratedValue> 6649 <name>occurred</name> 6650 <description>The event has occurred.</description> 6651 <value>1</value> 6652 </enumeratedValue> 6653 </enumeratedValues> 6654 </field> 6655 <field> 6656 <name>HITEMP</name> 6657 <description>High Temperature Detect.</description> 6658 <bitOffset>4</bitOffset> 6659 <bitWidth>1</bitWidth> 6660 <enumeratedValues> 6661 <enumeratedValue> 6662 <name>noEvent</name> 6663 <description>The event has not occurred.</description> 6664 <value>0</value> 6665 </enumeratedValue> 6666 <enumeratedValue> 6667 <name>occurred</name> 6668 <description>The event has occurred.</description> 6669 <value>1</value> 6670 </enumeratedValue> 6671 </enumeratedValues> 6672 </field> 6673 <field> 6674 <name>BATLO</name> 6675 <description>Battery Undervoltage Detect.</description> 6676 <bitOffset>5</bitOffset> 6677 <bitWidth>1</bitWidth> 6678 <enumeratedValues> 6679 <enumeratedValue> 6680 <name>noEvent</name> 6681 <description>The event has not occurred.</description> 6682 <value>0</value> 6683 </enumeratedValue> 6684 <enumeratedValue> 6685 <name>occurred</name> 6686 <description>The event has occurred.</description> 6687 <value>1</value> 6688 </enumeratedValue> 6689 </enumeratedValues> 6690 </field> 6691 <field> 6692 <name>BATHI</name> 6693 <description>Battery Overvoltage Detect.</description> 6694 <bitOffset>6</bitOffset> 6695 <bitWidth>1</bitWidth> 6696 <enumeratedValues> 6697 <enumeratedValue> 6698 <name>noEvent</name> 6699 <description>The event has not occurred.</description> 6700 <value>0</value> 6701 </enumeratedValue> 6702 <enumeratedValue> 6703 <name>occurred</name> 6704 <description>The event has occurred.</description> 6705 <value>1</value> 6706 </enumeratedValue> 6707 </enumeratedValues> 6708 </field> 6709 <field> 6710 <name>EXTF</name> 6711 <description>External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 6712 <bitOffset>7</bitOffset> 6713 <bitWidth>1</bitWidth> 6714 <enumeratedValues> 6715 <enumeratedValue> 6716 <name>noEvent</name> 6717 <description>The event has not occurred.</description> 6718 <value>0</value> 6719 </enumeratedValue> 6720 <enumeratedValue> 6721 <name>occurred</name> 6722 <description>The event has occurred.</description> 6723 <value>1</value> 6724 </enumeratedValue> 6725 </enumeratedValues> 6726 </field> 6727 <field> 6728 <name>VDDLO</name> 6729 <description>VDD Undervoltage Detect Flag.</description> 6730 <bitOffset>8</bitOffset> 6731 <bitWidth>1</bitWidth> 6732 <enumeratedValues> 6733 <enumeratedValue> 6734 <name>noEvent</name> 6735 <description>The event has not occurred.</description> 6736 <value>0</value> 6737 </enumeratedValue> 6738 <enumeratedValue> 6739 <name>occurred</name> 6740 <description>The event has occurred.</description> 6741 <value>1</value> 6742 </enumeratedValue> 6743 </enumeratedValues> 6744 </field> 6745 <field> 6746 <name>VCORELO</name> 6747 <description>VCORE Undervoltage Detect Flag.</description> 6748 <bitOffset>9</bitOffset> 6749 <bitWidth>1</bitWidth> 6750 <enumeratedValues> 6751 <enumeratedValue> 6752 <name>noEvent</name> 6753 <description>The event has not occurred.</description> 6754 <value>0</value> 6755 </enumeratedValue> 6756 <enumeratedValue> 6757 <name>occurred</name> 6758 <description>The event has occurred.</description> 6759 <value>1</value> 6760 </enumeratedValue> 6761 </enumeratedValues> 6762 </field> 6763 <field> 6764 <name>VCOREHI</name> 6765 <description>VCORE Overvoltage Detect Flag.</description> 6766 <bitOffset>10</bitOffset> 6767 <bitWidth>1</bitWidth> 6768 <enumeratedValues> 6769 <enumeratedValue> 6770 <name>noEvent</name> 6771 <description>The event has not occurred.</description> 6772 <value>0</value> 6773 </enumeratedValue> 6774 <enumeratedValue> 6775 <name>occurred</name> 6776 <description>The event has occurred.</description> 6777 <value>1</value> 6778 </enumeratedValue> 6779 </enumeratedValues> 6780 </field> 6781 <field> 6782 <name>VDDHI</name> 6783 <description>VDD Overvoltage Flag.</description> 6784 <bitOffset>11</bitOffset> 6785 <bitWidth>1</bitWidth> 6786 <enumeratedValues> 6787 <enumeratedValue> 6788 <name>noEvent</name> 6789 <description>The event has not occurred.</description> 6790 <value>0</value> 6791 </enumeratedValue> 6792 <enumeratedValue> 6793 <name>occurred</name> 6794 <description>The event has occurred.</description> 6795 <value>1</value> 6796 </enumeratedValue> 6797 </enumeratedValues> 6798 </field> 6799 <field> 6800 <name>VGL</name> 6801 <description>Voltage Glitch Detection Flag.</description> 6802 <bitOffset>12</bitOffset> 6803 <bitWidth>1</bitWidth> 6804 <enumeratedValues> 6805 <enumeratedValue> 6806 <name>noEvent</name> 6807 <description>The event has not occurred.</description> 6808 <value>0</value> 6809 </enumeratedValue> 6810 <enumeratedValue> 6811 <name>occurred</name> 6812 <description>The event has occurred.</description> 6813 <value>1</value> 6814 </enumeratedValue> 6815 </enumeratedValues> 6816 </field> 6817 <field> 6818 <name>EXTSTAT0</name> 6819 <description>External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 6820 <bitOffset>16</bitOffset> 6821 <bitWidth>1</bitWidth> 6822 <enumeratedValues> 6823 <enumeratedValue> 6824 <name>noEvent</name> 6825 <description>The event has not occurred.</description> 6826 <value>0</value> 6827 </enumeratedValue> 6828 <enumeratedValue> 6829 <name>occurred</name> 6830 <description>The event has occurred.</description> 6831 <value>1</value> 6832 </enumeratedValue> 6833 </enumeratedValues> 6834 </field> 6835 <field> 6836 <name>EXTSTAT1</name> 6837 <description>External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 6838 <bitOffset>17</bitOffset> 6839 <bitWidth>1</bitWidth> 6840 <enumeratedValues> 6841 <enumeratedValue> 6842 <name>noEvent</name> 6843 <description>The event has not occurred.</description> 6844 <value>0</value> 6845 </enumeratedValue> 6846 <enumeratedValue> 6847 <name>occurred</name> 6848 <description>The event has occurred.</description> 6849 <value>1</value> 6850 </enumeratedValue> 6851 </enumeratedValues> 6852 </field> 6853 <field> 6854 <name>EXTSTAT2</name> 6855 <description>External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 6856 <bitOffset>18</bitOffset> 6857 <bitWidth>1</bitWidth> 6858 <enumeratedValues> 6859 <enumeratedValue> 6860 <name>noEvent</name> 6861 <description>The event has not occurred.</description> 6862 <value>0</value> 6863 </enumeratedValue> 6864 <enumeratedValue> 6865 <name>occurred</name> 6866 <description>The event has occurred.</description> 6867 <value>1</value> 6868 </enumeratedValue> 6869 </enumeratedValues> 6870 </field> 6871 <field> 6872 <name>EXTSTAT3</name> 6873 <description>External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 6874 <bitOffset>19</bitOffset> 6875 <bitWidth>1</bitWidth> 6876 <enumeratedValues> 6877 <enumeratedValue> 6878 <name>noEvent</name> 6879 <description>The event has not occurred.</description> 6880 <value>0</value> 6881 </enumeratedValue> 6882 <enumeratedValue> 6883 <name>occurred</name> 6884 <description>The event has occurred.</description> 6885 <value>1</value> 6886 </enumeratedValue> 6887 </enumeratedValues> 6888 </field> 6889 <field> 6890 <name>EXTSTAT4</name> 6891 <description>External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 6892 <bitOffset>20</bitOffset> 6893 <bitWidth>1</bitWidth> 6894 <enumeratedValues> 6895 <enumeratedValue> 6896 <name>noEvent</name> 6897 <description>The event has not occurred.</description> 6898 <value>0</value> 6899 </enumeratedValue> 6900 <enumeratedValue> 6901 <name>occurred</name> 6902 <description>The event has occurred.</description> 6903 <value>1</value> 6904 </enumeratedValue> 6905 </enumeratedValues> 6906 </field> 6907 <field> 6908 <name>EXTSTAT5</name> 6909 <description>External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 6910 <bitOffset>21</bitOffset> 6911 <bitWidth>1</bitWidth> 6912 <enumeratedValues> 6913 <enumeratedValue> 6914 <name>noEvent</name> 6915 <description>The event has not occurred.</description> 6916 <value>0</value> 6917 </enumeratedValue> 6918 <enumeratedValue> 6919 <name>occurred</name> 6920 <description>The event has occurred.</description> 6921 <value>1</value> 6922 </enumeratedValue> 6923 </enumeratedValues> 6924 </field> 6925 <field> 6926 <name>EXTSWARN0</name> 6927 <description>External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 6928 <bitOffset>24</bitOffset> 6929 <bitWidth>1</bitWidth> 6930 <enumeratedValues> 6931 <enumeratedValue> 6932 <name>noEvent</name> 6933 <description>The event has not occurred.</description> 6934 <value>0</value> 6935 </enumeratedValue> 6936 <enumeratedValue> 6937 <name>occurred</name> 6938 <description>The event has occurred.</description> 6939 <value>1</value> 6940 </enumeratedValue> 6941 </enumeratedValues> 6942 </field> 6943 <field> 6944 <name>EXTSWARN1</name> 6945 <description>External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 6946 <bitOffset>25</bitOffset> 6947 <bitWidth>1</bitWidth> 6948 <enumeratedValues> 6949 <enumeratedValue> 6950 <name>noEvent</name> 6951 <description>The event has not occurred.</description> 6952 <value>0</value> 6953 </enumeratedValue> 6954 <enumeratedValue> 6955 <name>occurred</name> 6956 <description>The event has occurred.</description> 6957 <value>1</value> 6958 </enumeratedValue> 6959 </enumeratedValues> 6960 </field> 6961 <field> 6962 <name>EXTSWARN2</name> 6963 <description>External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 6964 <bitOffset>26</bitOffset> 6965 <bitWidth>1</bitWidth> 6966 <enumeratedValues> 6967 <enumeratedValue> 6968 <name>noEvent</name> 6969 <description>The event has not occurred.</description> 6970 <value>0</value> 6971 </enumeratedValue> 6972 <enumeratedValue> 6973 <name>occurred</name> 6974 <description>The event has occurred.</description> 6975 <value>1</value> 6976 </enumeratedValue> 6977 </enumeratedValues> 6978 </field> 6979 <field> 6980 <name>EXTSWARN3</name> 6981 <description>External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 6982 <bitOffset>27</bitOffset> 6983 <bitWidth>1</bitWidth> 6984 <enumeratedValues> 6985 <enumeratedValue> 6986 <name>noEvent</name> 6987 <description>The event has not occurred.</description> 6988 <value>0</value> 6989 </enumeratedValue> 6990 <enumeratedValue> 6991 <name>occurred</name> 6992 <description>The event has occurred.</description> 6993 <value>1</value> 6994 </enumeratedValue> 6995 </enumeratedValues> 6996 </field> 6997 <field> 6998 <name>EXTSWARN4</name> 6999 <description>External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 7000 <bitOffset>28</bitOffset> 7001 <bitWidth>1</bitWidth> 7002 <enumeratedValues> 7003 <enumeratedValue> 7004 <name>noEvent</name> 7005 <description>The event has not occurred.</description> 7006 <value>0</value> 7007 </enumeratedValue> 7008 <enumeratedValue> 7009 <name>occurred</name> 7010 <description>The event has occurred.</description> 7011 <value>1</value> 7012 </enumeratedValue> 7013 </enumeratedValues> 7014 </field> 7015 <field> 7016 <name>EXTSWARN5</name> 7017 <description>External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 7018 <bitOffset>29</bitOffset> 7019 <bitWidth>1</bitWidth> 7020 <enumeratedValues> 7021 <enumeratedValue> 7022 <name>noEvent</name> 7023 <description>The event has not occurred.</description> 7024 <value>0</value> 7025 </enumeratedValue> 7026 <enumeratedValue> 7027 <name>occurred</name> 7028 <description>The event has occurred.</description> 7029 <value>1</value> 7030 </enumeratedValue> 7031 </enumeratedValues> 7032 </field> 7033 </fields> 7034 </register> 7035 <register> 7036 <name>SECDIAG</name> 7037 <description>Security Diagnostic Register.</description> 7038 <addressOffset>0x0C</addressOffset> 7039 <access>read-only</access> 7040 <resetValue>0x00000001</resetValue> 7041 <resetMask>0xFFC0FE02</resetMask> 7042 <fields> 7043 <field> 7044 <name>BORF</name> 7045 <description>Battery-On-Reset Flag. This bit is set once the back up battery is conneted.</description> 7046 <bitOffset>0</bitOffset> 7047 <bitWidth>1</bitWidth> 7048 <enumeratedValues> 7049 <enumeratedValue> 7050 <name>noEvent</name> 7051 <description>The event has not occurred.</description> 7052 <value>0</value> 7053 </enumeratedValue> 7054 <enumeratedValue> 7055 <name>occurred</name> 7056 <description>The event has occurred.</description> 7057 <value>1</value> 7058 </enumeratedValue> 7059 </enumeratedValues> 7060 </field> 7061 <field> 7062 <name>SHIELDF</name> 7063 <description>Die Shield Flag.</description> 7064 <bitOffset>2</bitOffset> 7065 <bitWidth>1</bitWidth> 7066 <enumeratedValues> 7067 <enumeratedValue> 7068 <name>noEvent</name> 7069 <description>The event has not occurred.</description> 7070 <value>0</value> 7071 </enumeratedValue> 7072 <enumeratedValue> 7073 <name>occurred</name> 7074 <description>The event has occurred.</description> 7075 <value>1</value> 7076 </enumeratedValue> 7077 </enumeratedValues> 7078 </field> 7079 <field> 7080 <name>LOTEMP</name> 7081 <description>Low Temperature Detect.</description> 7082 <bitOffset>3</bitOffset> 7083 <bitWidth>1</bitWidth> 7084 <enumeratedValues> 7085 <enumeratedValue> 7086 <name>noEvent</name> 7087 <description>The event has not occurred.</description> 7088 <value>0</value> 7089 </enumeratedValue> 7090 <enumeratedValue> 7091 <name>occurred</name> 7092 <description>The event has occurred.</description> 7093 <value>1</value> 7094 </enumeratedValue> 7095 </enumeratedValues> 7096 </field> 7097 <field> 7098 <name>HITEMP</name> 7099 <description>High Temperature Detect.</description> 7100 <bitOffset>4</bitOffset> 7101 <bitWidth>1</bitWidth> 7102 <enumeratedValues> 7103 <enumeratedValue> 7104 <name>noEvent</name> 7105 <description>The event has not occurred.</description> 7106 <value>0</value> 7107 </enumeratedValue> 7108 <enumeratedValue> 7109 <name>occurred</name> 7110 <description>The event has occurred.</description> 7111 <value>1</value> 7112 </enumeratedValue> 7113 </enumeratedValues> 7114 </field> 7115 <field> 7116 <name>BATLO</name> 7117 <description>Battery Undervoltage Detect.</description> 7118 <bitOffset>5</bitOffset> 7119 <bitWidth>1</bitWidth> 7120 <enumeratedValues> 7121 <enumeratedValue> 7122 <name>noEvent</name> 7123 <description>The event has not occurred.</description> 7124 <value>0</value> 7125 </enumeratedValue> 7126 <enumeratedValue> 7127 <name>occurred</name> 7128 <description>The event has occurred.</description> 7129 <value>1</value> 7130 </enumeratedValue> 7131 </enumeratedValues> 7132 </field> 7133 <field> 7134 <name>BATHI</name> 7135 <description>Battery Overvoltage Detect.</description> 7136 <bitOffset>6</bitOffset> 7137 <bitWidth>1</bitWidth> 7138 <enumeratedValues> 7139 <enumeratedValue> 7140 <name>noEvent</name> 7141 <description>The event has not occurred.</description> 7142 <value>0</value> 7143 </enumeratedValue> 7144 <enumeratedValue> 7145 <name>occurred</name> 7146 <description>The event has occurred.</description> 7147 <value>1</value> 7148 </enumeratedValue> 7149 </enumeratedValues> 7150 </field> 7151 <field> 7152 <name>DYNF</name> 7153 <description>Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 7154 <bitOffset>7</bitOffset> 7155 <bitWidth>1</bitWidth> 7156 <enumeratedValues> 7157 <enumeratedValue> 7158 <name>noEvent</name> 7159 <description>The event has not occurred.</description> 7160 <value>0</value> 7161 </enumeratedValue> 7162 <enumeratedValue> 7163 <name>occurred</name> 7164 <description>The event has occurred.</description> 7165 <value>1</value> 7166 </enumeratedValue> 7167 </enumeratedValues> 7168 </field> 7169 <field> 7170 <name>AESKT</name> 7171 <description>AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.</description> 7172 <bitOffset>8</bitOffset> 7173 <bitWidth>1</bitWidth> 7174 <enumeratedValues> 7175 <enumeratedValue> 7176 <name>incomplete</name> 7177 <description>Key has not been transferred.</description> 7178 <value>0</value> 7179 </enumeratedValue> 7180 <enumeratedValue> 7181 <name>complete</name> 7182 <description>Key has been transferred.</description> 7183 <value>1</value> 7184 </enumeratedValue> 7185 </enumeratedValues> 7186 </field> 7187 <field> 7188 <name>EXTSTAT0</name> 7189 <description>External Sensor 0 Detect.</description> 7190 <bitOffset>16</bitOffset> 7191 <bitWidth>1</bitWidth> 7192 <enumeratedValues> 7193 <enumeratedValue> 7194 <name>noEvent</name> 7195 <description>The event has not occurred.</description> 7196 <value>0</value> 7197 </enumeratedValue> 7198 <enumeratedValue> 7199 <name>occurred</name> 7200 <description>The event has occurred.</description> 7201 <value>1</value> 7202 </enumeratedValue> 7203 </enumeratedValues> 7204 </field> 7205 <field> 7206 <name>EXTSTAT1</name> 7207 <description>External Sensor 1 Detect.</description> 7208 <bitOffset>17</bitOffset> 7209 <bitWidth>1</bitWidth> 7210 <enumeratedValues> 7211 <enumeratedValue> 7212 <name>noEvent</name> 7213 <description>The event has not occurred.</description> 7214 <value>0</value> 7215 </enumeratedValue> 7216 <enumeratedValue> 7217 <name>occurred</name> 7218 <description>The event has occurred.</description> 7219 <value>1</value> 7220 </enumeratedValue> 7221 </enumeratedValues> 7222 </field> 7223 <field> 7224 <name>EXTSTAT2</name> 7225 <description>External Sensor 2 Detect.</description> 7226 <bitOffset>18</bitOffset> 7227 <bitWidth>1</bitWidth> 7228 <enumeratedValues> 7229 <enumeratedValue> 7230 <name>noEvent</name> 7231 <description>The event has not occurred.</description> 7232 <value>0</value> 7233 </enumeratedValue> 7234 <enumeratedValue> 7235 <name>occurred</name> 7236 <description>The event has occurred.</description> 7237 <value>1</value> 7238 </enumeratedValue> 7239 </enumeratedValues> 7240 </field> 7241 <field> 7242 <name>EXTSTAT3</name> 7243 <description>External Sensor 3 Detect.</description> 7244 <bitOffset>19</bitOffset> 7245 <bitWidth>1</bitWidth> 7246 <enumeratedValues> 7247 <enumeratedValue> 7248 <name>noEvent</name> 7249 <description>The event has not occurred.</description> 7250 <value>0</value> 7251 </enumeratedValue> 7252 <enumeratedValue> 7253 <name>occurred</name> 7254 <description>The event has occurred.</description> 7255 <value>1</value> 7256 </enumeratedValue> 7257 </enumeratedValues> 7258 </field> 7259 <field> 7260 <name>EXTSTAT4</name> 7261 <description>External Sensor 4 Detect.</description> 7262 <bitOffset>20</bitOffset> 7263 <bitWidth>1</bitWidth> 7264 <enumeratedValues> 7265 <enumeratedValue> 7266 <name>noEvent</name> 7267 <description>The event has not occurred.</description> 7268 <value>0</value> 7269 </enumeratedValue> 7270 <enumeratedValue> 7271 <name>occurred</name> 7272 <description>The event has occurred.</description> 7273 <value>1</value> 7274 </enumeratedValue> 7275 </enumeratedValues> 7276 </field> 7277 <field> 7278 <name>EXTSTAT5</name> 7279 <description>External Sensor 5 Detect.</description> 7280 <bitOffset>21</bitOffset> 7281 <bitWidth>1</bitWidth> 7282 <enumeratedValues> 7283 <enumeratedValue> 7284 <name>noEvent</name> 7285 <description>The event has not occurred.</description> 7286 <value>0</value> 7287 </enumeratedValue> 7288 <enumeratedValue> 7289 <name>occurred</name> 7290 <description>The event has occurred.</description> 7291 <value>1</value> 7292 </enumeratedValue> 7293 </enumeratedValues> 7294 </field> 7295 </fields> 7296 </register> 7297 <register> 7298 <name>SECST</name> 7299 <description>Security Monitor Status Register.</description> 7300 <addressOffset>0x34</addressOffset> 7301 <access>read-only</access> 7302 <fields> 7303 <field> 7304 <name>EXTSRS</name> 7305 <description>External Sensor Control Register Status.</description> 7306 <bitOffset>0</bitOffset> 7307 <bitWidth>1</bitWidth> 7308 <enumeratedValues> 7309 <enumeratedValue> 7310 <name>allowed</name> 7311 <description>Access authorized.</description> 7312 <value>0</value> 7313 </enumeratedValue> 7314 <enumeratedValue> 7315 <name>notAllowed</name> 7316 <description>Access not authorized.</description> 7317 <value>1</value> 7318 </enumeratedValue> 7319 </enumeratedValues> 7320 </field> 7321 <field> 7322 <name>INTSRS</name> 7323 <description>Internal Sensor Control Register Status.</description> 7324 <bitOffset>1</bitOffset> 7325 <bitWidth>1</bitWidth> 7326 <enumeratedValues> 7327 <enumeratedValue> 7328 <name>allowed</name> 7329 <description>Access authorized.</description> 7330 <value>0</value> 7331 </enumeratedValue> 7332 <enumeratedValue> 7333 <name>notAllowed</name> 7334 <description>Access not authorized.</description> 7335 <value>1</value> 7336 </enumeratedValue> 7337 </enumeratedValues> 7338 </field> 7339 <field> 7340 <name>SECALRS</name> 7341 <description>Security Alarm Register Status.</description> 7342 <bitOffset>2</bitOffset> 7343 <bitWidth>1</bitWidth> 7344 <enumeratedValues> 7345 <enumeratedValue> 7346 <name>allowed</name> 7347 <description>Access authorized.</description> 7348 <value>0</value> 7349 </enumeratedValue> 7350 <enumeratedValue> 7351 <name>notAllowed</name> 7352 <description>Access not authorized.</description> 7353 <value>1</value> 7354 </enumeratedValue> 7355 </enumeratedValues> 7356 </field> 7357 </fields> 7358 </register> 7359 <register> 7360 <name>SDBE</name> 7361 <description>Security Monitor Self Destruct Byte.</description> 7362 <addressOffset>0x38</addressOffset> 7363 <fields> 7364 <field> 7365 <name>DBYTE</name> 7366 <description>Self Destruct Byte</description> 7367 <bitOffset>0</bitOffset> 7368 <bitWidth>8</bitWidth> 7369 </field> 7370 <field> 7371 <name>SBDEN</name> 7372 <description>Self-Destruct Byte ENable.</description> 7373 <bitOffset>31</bitOffset> 7374 <bitWidth>1</bitWidth> 7375 </field> 7376 </fields> 7377 </register> 7378 </registers> 7379 </peripheral> 7380<!--SMON The Security Monitor block used to monitor system threat conditions.--> 7381 <peripheral> 7382 <name>SPI0</name> 7383 <description>SPI peripheral.</description> 7384 <baseAddress>0x40046000</baseAddress> 7385 <addressBlock> 7386 <offset>0x00</offset> 7387 <size>0x1000</size> 7388 <usage>registers</usage> 7389 </addressBlock> 7390 <interrupt> 7391 <name>SPI0</name> 7392 <value>16</value> 7393 </interrupt> 7394 <registers> 7395 <register> 7396 <name>DATA32</name> 7397 <description>Register for reading and writing the FIFO.</description> 7398 <addressOffset>0x00</addressOffset> 7399 <size>32</size> 7400 <access>read-write</access> 7401 <fields> 7402 <field> 7403 <name>DATA</name> 7404 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 7405 <bitOffset>0</bitOffset> 7406 <bitWidth>32</bitWidth> 7407 </field> 7408 </fields> 7409 </register> 7410 <register> 7411 <dim>2</dim> 7412 <dimIncrement>2</dimIncrement> 7413 <name>DATA16[%s]</name> 7414 <description>Register for reading and writing the FIFO.</description> 7415 <alternateRegister>DATA32</alternateRegister> 7416 <addressOffset>0x00</addressOffset> 7417 <size>16</size> 7418 <access>read-write</access> 7419 <fields> 7420 <field> 7421 <name>DATA</name> 7422 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 7423 <bitOffset>0</bitOffset> 7424 <bitWidth>16</bitWidth> 7425 </field> 7426 </fields> 7427 </register> 7428 <register> 7429 <dim>4</dim> 7430 <dimIncrement>1</dimIncrement> 7431 <name>DATA8[%s]</name> 7432 <description>Register for reading and writing the FIFO.</description> 7433 <alternateRegister>DATA32</alternateRegister> 7434 <addressOffset>0x00</addressOffset> 7435 <size>8</size> 7436 <access>read-write</access> 7437 <fields> 7438 <field> 7439 <name>DATA</name> 7440 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 7441 <bitOffset>0</bitOffset> 7442 <bitWidth>8</bitWidth> 7443 </field> 7444 </fields> 7445 </register> 7446 <register> 7447 <name>MSTR_CNTL</name> 7448 <description>Register for controlling SPI peripheral.</description> 7449 <addressOffset>0x04</addressOffset> 7450 <access>read-write</access> 7451 <fields> 7452 <field> 7453 <name>SPIEN</name> 7454 <description>SPI Enable.</description> 7455 <bitOffset>0</bitOffset> 7456 <bitWidth>1</bitWidth> 7457 <enumeratedValues> 7458 <enumeratedValue> 7459 <name>dis</name> 7460 <description>SPI is disabled.</description> 7461 <value>0</value> 7462 </enumeratedValue> 7463 <enumeratedValue> 7464 <name>en</name> 7465 <description>SPI is enabled.</description> 7466 <value>1</value> 7467 </enumeratedValue> 7468 </enumeratedValues> 7469 </field> 7470 <field> 7471 <name>MMEN</name> 7472 <description>Master Mode Enable.</description> 7473 <bitOffset>1</bitOffset> 7474 <bitWidth>1</bitWidth> 7475 <enumeratedValues> 7476 <enumeratedValue> 7477 <name>dis</name> 7478 <description>SPI is Slave mode.</description> 7479 <value>0</value> 7480 </enumeratedValue> 7481 <enumeratedValue> 7482 <name>en</name> 7483 <description>SPI is Master mode.</description> 7484 <value>1</value> 7485 </enumeratedValue> 7486 </enumeratedValues> 7487 </field> 7488 <field> 7489 <name>SSIO</name> 7490 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 7491 <bitOffset>4</bitOffset> 7492 <bitWidth>1</bitWidth> 7493 <enumeratedValues> 7494 <enumeratedValue> 7495 <name>output</name> 7496 <description>Slave select 0 is output.</description> 7497 <value>0</value> 7498 </enumeratedValue> 7499 <enumeratedValue> 7500 <name>input</name> 7501 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 7502 <value>1</value> 7503 </enumeratedValue> 7504 </enumeratedValues> 7505 </field> 7506 <field> 7507 <name>START</name> 7508 <description>Start Transmit.</description> 7509 <bitOffset>5</bitOffset> 7510 <bitWidth>1</bitWidth> 7511 <enumeratedValues> 7512 <enumeratedValue> 7513 <name>start</name> 7514 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 7515 <value>1</value> 7516 </enumeratedValue> 7517 </enumeratedValues> 7518 </field> 7519 <field> 7520 <name>SSCTRL</name> 7521 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 7522 <bitOffset>8</bitOffset> 7523 <bitWidth>1</bitWidth> 7524 <enumeratedValues> 7525 <enumeratedValue> 7526 <name>deassert</name> 7527 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 7528 <value>0</value> 7529 </enumeratedValue> 7530 <enumeratedValue> 7531 <name>assert</name> 7532 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 7533 <value>1</value> 7534 </enumeratedValue> 7535 </enumeratedValues> 7536 </field> 7537 <field> 7538 <name>SS</name> 7539 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 7540 <bitOffset>16</bitOffset> 7541 <bitWidth>3</bitWidth> 7542 <enumeratedValues> 7543 <enumeratedValue> 7544 <name>ss0</name> 7545 <description>SS0 is selected.</description> 7546 <value>0x1</value> 7547 </enumeratedValue> 7548 <enumeratedValue> 7549 <name>ss1</name> 7550 <description>SS1 is selected.</description> 7551 <value>0x2</value> 7552 </enumeratedValue> 7553 <enumeratedValue> 7554 <name>ss2</name> 7555 <description>SS2 is selected.</description> 7556 <value>0x4</value> 7557 </enumeratedValue> 7558 </enumeratedValues> 7559 </field> 7560 </fields> 7561 </register> 7562 <register> 7563 <name>TRNMT_SIZE</name> 7564 <description>Register for controlling SPI peripheral.</description> 7565 <addressOffset>0x08</addressOffset> 7566 <access>read-write</access> 7567 <fields> 7568 <field> 7569 <name>TX_NUM_CHAR</name> 7570 <description>Nubmer of Characters to transmit.</description> 7571 <bitOffset>0</bitOffset> 7572 <bitWidth>16</bitWidth> 7573 </field> 7574 <field> 7575 <name>RX_NUM_CHAR</name> 7576 <description>Nubmer of Characters to receive.</description> 7577 <bitOffset>16</bitOffset> 7578 <bitWidth>16</bitWidth> 7579 </field> 7580 </fields> 7581 </register> 7582 <register> 7583 <name>STATIC_CONFIG</name> 7584 <description>Register for controlling SPI peripheral.</description> 7585 <addressOffset>0x0C</addressOffset> 7586 <access>read-write</access> 7587 <fields> 7588 <field> 7589 <name>PHASE</name> 7590 <description>Clock Phase.</description> 7591 <bitOffset>0</bitOffset> 7592 <bitWidth>1</bitWidth> 7593 <enumeratedValues> 7594 <enumeratedValue> 7595 <name>rising_edge</name> 7596 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 7597 <value>0</value> 7598 </enumeratedValue> 7599 <enumeratedValue> 7600 <name>falling_edge</name> 7601 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 7602 <value>1</value> 7603 </enumeratedValue> 7604 </enumeratedValues> 7605 </field> 7606 <field> 7607 <name>CLKPOL</name> 7608 <description>Clock Polarity.</description> 7609 <bitOffset>1</bitOffset> 7610 <bitWidth>1</bitWidth> 7611 <enumeratedValues> 7612 <enumeratedValue> 7613 <name>normal</name> 7614 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 7615 <value>0</value> 7616 </enumeratedValue> 7617 <enumeratedValue> 7618 <name>inverted</name> 7619 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 7620 <value>1</value> 7621 </enumeratedValue> 7622 </enumeratedValues> 7623 </field> 7624 <field> 7625 <name>NUMBITS</name> 7626 <description>Number of Bits per character.</description> 7627 <bitOffset>8</bitOffset> 7628 <bitWidth>4</bitWidth> 7629 <enumeratedValues> 7630 <enumeratedValue> 7631 <name>0</name> 7632 <description>16 bits per character.</description> 7633 <value>0</value> 7634 </enumeratedValue> 7635 </enumeratedValues> 7636 </field> 7637 <field> 7638 <name>DATAWIDTH</name> 7639 <description>SPI Data width.</description> 7640 <bitOffset>12</bitOffset> 7641 <bitWidth>2</bitWidth> 7642 <enumeratedValues> 7643 <enumeratedValue> 7644 <name>mono</name> 7645 <description>1 data pin.</description> 7646 <value>0</value> 7647 </enumeratedValue> 7648 <enumeratedValue> 7649 <name>dual</name> 7650 <description>2 data pins.</description> 7651 <value>1</value> 7652 </enumeratedValue> 7653 <enumeratedValue> 7654 <name>quad</name> 7655 <description>4 data pins.</description> 7656 <value>2</value> 7657 </enumeratedValue> 7658 </enumeratedValues> 7659 </field> 7660 <field> 7661 <name>3WIRE</name> 7662 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 7663 <bitOffset>15</bitOffset> 7664 <bitWidth>1</bitWidth> 7665 <enumeratedValues> 7666 <enumeratedValue> 7667 <name>dis</name> 7668 <description>Use four wire mode (Mono only).</description> 7669 <value>0</value> 7670 </enumeratedValue> 7671 <enumeratedValue> 7672 <name>en</name> 7673 <description>Use three wire mode.</description> 7674 <value>1</value> 7675 </enumeratedValue> 7676 </enumeratedValues> 7677 </field> 7678 <field> 7679 <name>SSPOL</name> 7680 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 7681 <bitOffset>16</bitOffset> 7682 <bitWidth>8</bitWidth> 7683 <enumeratedValues> 7684 <enumeratedValue> 7685 <name>SS0_high</name> 7686 <description>SS0 active high.</description> 7687 <value>0x1</value> 7688 </enumeratedValue> 7689 <enumeratedValue> 7690 <name>SS1_high</name> 7691 <description>SS1 active high.</description> 7692 <value>0x2</value> 7693 </enumeratedValue> 7694 <enumeratedValue> 7695 <name>SS2_high</name> 7696 <description>SS2 active high.</description> 7697 <value>0x4</value> 7698 </enumeratedValue> 7699 </enumeratedValues> 7700 </field> 7701 </fields> 7702 </register> 7703 <register> 7704 <name>SS_TIME</name> 7705 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 7706 <addressOffset>0x10</addressOffset> 7707 <access>read-write</access> 7708 <fields> 7709 <field> 7710 <name>PRE</name> 7711 <description>Slave Select Pre delay 1.</description> 7712 <bitOffset>0</bitOffset> 7713 <bitWidth>8</bitWidth> 7714 <enumeratedValues> 7715 <enumeratedValue> 7716 <name>256</name> 7717 <description>256 system clocks between SS active and first serial clock edge.</description> 7718 <value>0</value> 7719 </enumeratedValue> 7720 </enumeratedValues> 7721 </field> 7722 <field> 7723 <name>POST</name> 7724 <description>Slave Select Post delay 2.</description> 7725 <bitOffset>8</bitOffset> 7726 <bitWidth>8</bitWidth> 7727 <enumeratedValues> 7728 <enumeratedValue> 7729 <name>256</name> 7730 <description>256 system clocks between last serial clock edge and SS inactive.</description> 7731 <value>0</value> 7732 </enumeratedValue> 7733 </enumeratedValues> 7734 </field> 7735 <field> 7736 <name>INACT</name> 7737 <description>Slave Select Inactive delay.</description> 7738 <bitOffset>16</bitOffset> 7739 <bitWidth>8</bitWidth> 7740 <enumeratedValues> 7741 <enumeratedValue> 7742 <name>256</name> 7743 <description>256 system clocks between transactions.</description> 7744 <value>0</value> 7745 </enumeratedValue> 7746 </enumeratedValues> 7747 </field> 7748 </fields> 7749 </register> 7750 <register> 7751 <name>CLK_CONFIG</name> 7752 <description>Register for controlling SPI clock rate.</description> 7753 <addressOffset>0x14</addressOffset> 7754 <access>read-write</access> 7755 <fields> 7756 <field> 7757 <name>LOW</name> 7758 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 7759 <bitOffset>0</bitOffset> 7760 <bitWidth>8</bitWidth> 7761 <enumeratedValues> 7762 <enumeratedValue> 7763 <name>dis</name> 7764 <description>Duty cycle control of serial clock generation is disabled.</description> 7765 <value>0</value> 7766 </enumeratedValue> 7767 </enumeratedValues> 7768 </field> 7769 <field> 7770 <name>HIGH</name> 7771 <description>High duty cycle control. In timer mode, reload[15:8].</description> 7772 <bitOffset>8</bitOffset> 7773 <bitWidth>8</bitWidth> 7774 <enumeratedValues> 7775 <enumeratedValue> 7776 <name>dis</name> 7777 <description>Duty cycle control of serial clock generation is disabled.</description> 7778 <value>0</value> 7779 </enumeratedValue> 7780 </enumeratedValues> 7781 </field> 7782 <field> 7783 <name>SCALE</name> 7784 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 7785 <bitOffset>16</bitOffset> 7786 <bitWidth>4</bitWidth> 7787 </field> 7788 </fields> 7789 </register> 7790 <register> 7791 <name>DMA</name> 7792 <description>Register for controlling DMA.</description> 7793 <addressOffset>0x1C</addressOffset> 7794 <access>read-write</access> 7795 <fields> 7796 <field> 7797 <name>TX_FIFO_LEVEL</name> 7798 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 7799 <bitOffset>0</bitOffset> 7800 <bitWidth>5</bitWidth> 7801 </field> 7802 <field> 7803 <name>TX_FIFO_EN</name> 7804 <description>Transmit FIFO enabled for SPI transactions.</description> 7805 <bitOffset>6</bitOffset> 7806 <bitWidth>1</bitWidth> 7807 <enumeratedValues> 7808 <enumeratedValue> 7809 <name>dis</name> 7810 <description>Transmit FIFO is not enabled.</description> 7811 <value>0</value> 7812 </enumeratedValue> 7813 <enumeratedValue> 7814 <name>en</name> 7815 <description>Transmit FIFO is enabled.</description> 7816 <value>1</value> 7817 </enumeratedValue> 7818 </enumeratedValues> 7819 </field> 7820 <field> 7821 <name>TX_FIFO_CLEAR</name> 7822 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 7823 <bitOffset>7</bitOffset> 7824 <bitWidth>1</bitWidth> 7825 <enumeratedValues> 7826 <enumeratedValue> 7827 <name>clear</name> 7828 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 7829 <value>1</value> 7830 </enumeratedValue> 7831 </enumeratedValues> 7832 </field> 7833 <field> 7834 <name>TX_FIFO_CNT</name> 7835 <description>Count of entries in TX FIFO.</description> 7836 <bitOffset>8</bitOffset> 7837 <bitWidth>6</bitWidth> 7838 <access>read-only</access> 7839 </field> 7840 <field> 7841 <name>TX_DMA_EN</name> 7842 <description>TX DMA Enable.</description> 7843 <bitOffset>15</bitOffset> 7844 <bitWidth>1</bitWidth> 7845 <enumeratedValues> 7846 <enumeratedValue> 7847 <name>dis</name> 7848 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 7849 <value>0</value> 7850 </enumeratedValue> 7851 <enumeratedValue> 7852 <name>en</name> 7853 <description>TX DMA requests are enabled.</description> 7854 <value>1</value> 7855 </enumeratedValue> 7856 </enumeratedValues> 7857 </field> 7858 <field> 7859 <name>RX_FIFO_LEVEL</name> 7860 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 7861 <bitOffset>16</bitOffset> 7862 <bitWidth>5</bitWidth> 7863 </field> 7864 <field> 7865 <name>RX_FIFO_EN</name> 7866 <description>Receive FIFO enabled for SPI transactions.</description> 7867 <bitOffset>22</bitOffset> 7868 <bitWidth>1</bitWidth> 7869 <enumeratedValues> 7870 <enumeratedValue> 7871 <name>dis</name> 7872 <description>Receive FIFO is not enabled.</description> 7873 <value>0</value> 7874 </enumeratedValue> 7875 <enumeratedValue> 7876 <name>en</name> 7877 <description>Receive FIFO is enabled.</description> 7878 <value>1</value> 7879 </enumeratedValue> 7880 </enumeratedValues> 7881 </field> 7882 <field> 7883 <name>RX_FIFO_CLEAR</name> 7884 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 7885 <bitOffset>23</bitOffset> 7886 <bitWidth>1</bitWidth> 7887 <enumeratedValues> 7888 <enumeratedValue> 7889 <name>clear</name> 7890 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 7891 <value>1</value> 7892 </enumeratedValue> 7893 </enumeratedValues> 7894 </field> 7895 <field> 7896 <name>RX_FIFO_CNT</name> 7897 <description>Count of entries in RX FIFO.</description> 7898 <bitOffset>24</bitOffset> 7899 <bitWidth>6</bitWidth> 7900 <access>read-only</access> 7901 </field> 7902 <field> 7903 <name>RX_DMA_EN</name> 7904 <description>RX DMA Enable.</description> 7905 <bitOffset>31</bitOffset> 7906 <bitWidth>1</bitWidth> 7907 <enumeratedValues> 7908 <enumeratedValue> 7909 <name>dis</name> 7910 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 7911 <value>0</value> 7912 </enumeratedValue> 7913 <enumeratedValue> 7914 <name>en</name> 7915 <description>RX DMA requests are enabled.</description> 7916 <value>1</value> 7917 </enumeratedValue> 7918 </enumeratedValues> 7919 </field> 7920 </fields> 7921 </register> 7922 <register> 7923 <name>INT_FL</name> 7924 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 7925 <addressOffset>0x20</addressOffset> 7926 <access>read-write</access> 7927 <fields> 7928 <field> 7929 <name>TXTHRLD</name> 7930 <description>TX FIFO Threshold Crossed.</description> 7931 <bitOffset>0</bitOffset> 7932 <bitWidth>1</bitWidth> 7933 <enumeratedValues> 7934 <enumeratedValue> 7935 <name>clear</name> 7936 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7937 <value>1</value> 7938 </enumeratedValue> 7939 </enumeratedValues> 7940 </field> 7941 <field> 7942 <name>TXEMPTY</name> 7943 <description>TX FIFO Empty.</description> 7944 <bitOffset>1</bitOffset> 7945 <bitWidth>1</bitWidth> 7946 <enumeratedValues> 7947 <enumeratedValue> 7948 <name>clear</name> 7949 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7950 <value>1</value> 7951 </enumeratedValue> 7952 </enumeratedValues> 7953 </field> 7954 <field> 7955 <name>RXTHRLD</name> 7956 <description>RX FIFO Threshold Crossed.</description> 7957 <bitOffset>2</bitOffset> 7958 <bitWidth>1</bitWidth> 7959 <enumeratedValues> 7960 <enumeratedValue> 7961 <name>clear</name> 7962 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7963 <value>1</value> 7964 </enumeratedValue> 7965 </enumeratedValues> 7966 </field> 7967 <field> 7968 <name>RXFULL</name> 7969 <description>RX FIFO FULL.</description> 7970 <bitOffset>3</bitOffset> 7971 <bitWidth>1</bitWidth> 7972 <enumeratedValues> 7973 <enumeratedValue> 7974 <name>clear</name> 7975 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7976 <value>1</value> 7977 </enumeratedValue> 7978 </enumeratedValues> 7979 </field> 7980 <field> 7981 <name>SSA</name> 7982 <description>Slave Select Asserted.</description> 7983 <bitOffset>4</bitOffset> 7984 <bitWidth>1</bitWidth> 7985 <enumeratedValues> 7986 <enumeratedValue> 7987 <name>clear</name> 7988 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7989 <value>1</value> 7990 </enumeratedValue> 7991 </enumeratedValues> 7992 </field> 7993 <field> 7994 <name>SSD</name> 7995 <description>Slave Select Deasserted.</description> 7996 <bitOffset>5</bitOffset> 7997 <bitWidth>1</bitWidth> 7998 <enumeratedValues> 7999 <enumeratedValue> 8000 <name>clear</name> 8001 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8002 <value>1</value> 8003 </enumeratedValue> 8004 </enumeratedValues> 8005 </field> 8006 <field> 8007 <name>FAULT</name> 8008 <description>Multi-Master Mode Fault.</description> 8009 <bitOffset>8</bitOffset> 8010 <bitWidth>1</bitWidth> 8011 <enumeratedValues> 8012 <enumeratedValue> 8013 <name>clear</name> 8014 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8015 <value>1</value> 8016 </enumeratedValue> 8017 </enumeratedValues> 8018 </field> 8019 <field> 8020 <name>ABORT</name> 8021 <description>Slave Abort Detected.</description> 8022 <bitOffset>9</bitOffset> 8023 <bitWidth>1</bitWidth> 8024 <enumeratedValues> 8025 <enumeratedValue> 8026 <name>clear</name> 8027 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8028 <value>1</value> 8029 </enumeratedValue> 8030 </enumeratedValues> 8031 </field> 8032 <field> 8033 <name>MSTRDONE</name> 8034 <description>Master Done, set when SPI Master has completed any transactions.</description> 8035 <bitOffset>11</bitOffset> 8036 <bitWidth>1</bitWidth> 8037 <enumeratedValues> 8038 <enumeratedValue> 8039 <name>clear</name> 8040 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8041 <value>1</value> 8042 </enumeratedValue> 8043 </enumeratedValues> 8044 </field> 8045 <field> 8046 <name>TXOVR</name> 8047 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 8048 <bitOffset>12</bitOffset> 8049 <bitWidth>1</bitWidth> 8050 <enumeratedValues> 8051 <enumeratedValue> 8052 <name>clear</name> 8053 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8054 <value>1</value> 8055 </enumeratedValue> 8056 </enumeratedValues> 8057 </field> 8058 <field> 8059 <name>TXUNDR</name> 8060 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 8061 <bitOffset>13</bitOffset> 8062 <bitWidth>1</bitWidth> 8063 <enumeratedValues> 8064 <enumeratedValue> 8065 <name>clear</name> 8066 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8067 <value>1</value> 8068 </enumeratedValue> 8069 </enumeratedValues> 8070 </field> 8071 <field> 8072 <name>RXOVR</name> 8073 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 8074 <bitOffset>14</bitOffset> 8075 <bitWidth>1</bitWidth> 8076 <enumeratedValues> 8077 <enumeratedValue> 8078 <name>clear</name> 8079 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8080 <value>1</value> 8081 </enumeratedValue> 8082 </enumeratedValues> 8083 </field> 8084 <field> 8085 <name>RXUNDR</name> 8086 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 8087 <bitOffset>15</bitOffset> 8088 <bitWidth>1</bitWidth> 8089 <enumeratedValues> 8090 <enumeratedValue> 8091 <name>clear</name> 8092 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8093 <value>1</value> 8094 </enumeratedValue> 8095 </enumeratedValues> 8096 </field> 8097 </fields> 8098 </register> 8099 <register> 8100 <name>INT_EN</name> 8101 <description>Register for enabling interrupts.</description> 8102 <addressOffset>0x24</addressOffset> 8103 <access>read-write</access> 8104 <fields> 8105 <field> 8106 <name>TXTHRLD</name> 8107 <description>TX FIFO Threshold interrupt enable.</description> 8108 <bitOffset>0</bitOffset> 8109 <bitWidth>1</bitWidth> 8110 <enumeratedValues> 8111 <enumeratedValue> 8112 <name>dis</name> 8113 <description>Interrupt is disabled.</description> 8114 <value>0</value> 8115 </enumeratedValue> 8116 <enumeratedValue> 8117 <name>en</name> 8118 <description>Interrupt is enabled.</description> 8119 <value>1</value> 8120 </enumeratedValue> 8121 </enumeratedValues> 8122 </field> 8123 <field> 8124 <name>TXEMPTY</name> 8125 <description>TX FIFO Empty interrupt enable.</description> 8126 <bitOffset>1</bitOffset> 8127 <bitWidth>1</bitWidth> 8128 <enumeratedValues> 8129 <enumeratedValue> 8130 <name>dis</name> 8131 <description>Interrupt is disabled.</description> 8132 <value>0</value> 8133 </enumeratedValue> 8134 <enumeratedValue> 8135 <name>en</name> 8136 <description>Interrupt is enabled.</description> 8137 <value>1</value> 8138 </enumeratedValue> 8139 </enumeratedValues> 8140 </field> 8141 <field> 8142 <name>RXTHRLD</name> 8143 <description>RX FIFO Threshold Crossed interrupt enable.</description> 8144 <bitOffset>2</bitOffset> 8145 <bitWidth>1</bitWidth> 8146 <enumeratedValues> 8147 <enumeratedValue> 8148 <name>dis</name> 8149 <description>Interrupt is disabled.</description> 8150 <value>0</value> 8151 </enumeratedValue> 8152 <enumeratedValue> 8153 <name>en</name> 8154 <description>Interrupt is enabled.</description> 8155 <value>1</value> 8156 </enumeratedValue> 8157 </enumeratedValues> 8158 </field> 8159 <field> 8160 <name>RXFULL</name> 8161 <description>RX FIFO FULL interrupt enable.</description> 8162 <bitOffset>3</bitOffset> 8163 <bitWidth>1</bitWidth> 8164 <enumeratedValues> 8165 <enumeratedValue> 8166 <name>dis</name> 8167 <description>Interrupt is disabled.</description> 8168 <value>0</value> 8169 </enumeratedValue> 8170 <enumeratedValue> 8171 <name>en</name> 8172 <description>Interrupt is enabled.</description> 8173 <value>1</value> 8174 </enumeratedValue> 8175 </enumeratedValues> 8176 </field> 8177 <field> 8178 <name>SSA</name> 8179 <description>Slave Select Asserted interrupt enable.</description> 8180 <bitOffset>4</bitOffset> 8181 <bitWidth>1</bitWidth> 8182 <enumeratedValues> 8183 <enumeratedValue> 8184 <name>dis</name> 8185 <description>Interrupt is disabled.</description> 8186 <value>0</value> 8187 </enumeratedValue> 8188 <enumeratedValue> 8189 <name>en</name> 8190 <description>Interrupt is enabled.</description> 8191 <value>1</value> 8192 </enumeratedValue> 8193 </enumeratedValues> 8194 </field> 8195 <field> 8196 <name>SSD</name> 8197 <description>Slave Select Deasserted interrupt enable.</description> 8198 <bitOffset>5</bitOffset> 8199 <bitWidth>1</bitWidth> 8200 <enumeratedValues> 8201 <enumeratedValue> 8202 <name>dis</name> 8203 <description>Interrupt is disabled.</description> 8204 <value>0</value> 8205 </enumeratedValue> 8206 <enumeratedValue> 8207 <name>en</name> 8208 <description>Interrupt is enabled.</description> 8209 <value>1</value> 8210 </enumeratedValue> 8211 </enumeratedValues> 8212 </field> 8213 <field> 8214 <name>FAULT</name> 8215 <description>Multi-Master Mode Fault interrupt enable.</description> 8216 <bitOffset>8</bitOffset> 8217 <bitWidth>1</bitWidth> 8218 <enumeratedValues> 8219 <enumeratedValue> 8220 <name>dis</name> 8221 <description>Interrupt is disabled.</description> 8222 <value>0</value> 8223 </enumeratedValue> 8224 <enumeratedValue> 8225 <name>en</name> 8226 <description>Interrupt is enabled.</description> 8227 <value>1</value> 8228 </enumeratedValue> 8229 </enumeratedValues> 8230 </field> 8231 <field> 8232 <name>ABORT</name> 8233 <description>Slave Abort Detected interrupt enable.</description> 8234 <bitOffset>9</bitOffset> 8235 <bitWidth>1</bitWidth> 8236 <enumeratedValues> 8237 <enumeratedValue> 8238 <name>dis</name> 8239 <description>Interrupt is disabled.</description> 8240 <value>0</value> 8241 </enumeratedValue> 8242 <enumeratedValue> 8243 <name>en</name> 8244 <description>Interrupt is enabled.</description> 8245 <value>1</value> 8246 </enumeratedValue> 8247 </enumeratedValues> 8248 </field> 8249 <field> 8250 <name>MSTRDONE</name> 8251 <description>Master Done interrupt enable.</description> 8252 <bitOffset>11</bitOffset> 8253 <bitWidth>1</bitWidth> 8254 <enumeratedValues> 8255 <enumeratedValue> 8256 <name>dis</name> 8257 <description>Interrupt is disabled.</description> 8258 <value>0</value> 8259 </enumeratedValue> 8260 <enumeratedValue> 8261 <name>en</name> 8262 <description>Interrupt is enabled.</description> 8263 <value>1</value> 8264 </enumeratedValue> 8265 </enumeratedValues> 8266 </field> 8267 <field> 8268 <name>TXOVR</name> 8269 <description>Transmit FIFO Overrun interrupt enable.</description> 8270 <bitOffset>12</bitOffset> 8271 <bitWidth>1</bitWidth> 8272 <enumeratedValues> 8273 <enumeratedValue> 8274 <name>dis</name> 8275 <description>Interrupt is disabled.</description> 8276 <value>0</value> 8277 </enumeratedValue> 8278 <enumeratedValue> 8279 <name>en</name> 8280 <description>Interrupt is enabled.</description> 8281 <value>1</value> 8282 </enumeratedValue> 8283 </enumeratedValues> 8284 </field> 8285 <field> 8286 <name>TXUNDR</name> 8287 <description>Transmit FIFO Underrun interrupt enable.</description> 8288 <bitOffset>13</bitOffset> 8289 <bitWidth>1</bitWidth> 8290 <enumeratedValues> 8291 <enumeratedValue> 8292 <name>dis</name> 8293 <description>Interrupt is disabled.</description> 8294 <value>0</value> 8295 </enumeratedValue> 8296 <enumeratedValue> 8297 <name>en</name> 8298 <description>Interrupt is enabled.</description> 8299 <value>1</value> 8300 </enumeratedValue> 8301 </enumeratedValues> 8302 </field> 8303 <field> 8304 <name>RXOVR</name> 8305 <description>Receive FIFO Overrun interrupt enable.</description> 8306 <bitOffset>14</bitOffset> 8307 <bitWidth>1</bitWidth> 8308 <enumeratedValues> 8309 <enumeratedValue> 8310 <name>dis</name> 8311 <description>Interrupt is disabled.</description> 8312 <value>0</value> 8313 </enumeratedValue> 8314 <enumeratedValue> 8315 <name>en</name> 8316 <description>Interrupt is enabled.</description> 8317 <value>1</value> 8318 </enumeratedValue> 8319 </enumeratedValues> 8320 </field> 8321 <field> 8322 <name>RXUNDR</name> 8323 <description>Receive FIFO Underrun interrupt enable.</description> 8324 <bitOffset>15</bitOffset> 8325 <bitWidth>1</bitWidth> 8326 <enumeratedValues> 8327 <enumeratedValue> 8328 <name>dis</name> 8329 <description>Interrupt is disabled.</description> 8330 <value>0</value> 8331 </enumeratedValue> 8332 <enumeratedValue> 8333 <name>en</name> 8334 <description>Interrupt is enabled.</description> 8335 <value>1</value> 8336 </enumeratedValue> 8337 </enumeratedValues> 8338 </field> 8339 </fields> 8340 </register> 8341 <register> 8342 <name>WAKE_FL</name> 8343 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 8344 <addressOffset>0x28</addressOffset> 8345 <access>read-write</access> 8346 <fields> 8347 <field> 8348 <name>TXTHRLD</name> 8349 <description>Wake on TX FIFO Threshold Crossed.</description> 8350 <bitOffset>0</bitOffset> 8351 <bitWidth>1</bitWidth> 8352 <enumeratedValues> 8353 <enumeratedValue> 8354 <name>clear</name> 8355 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8356 <value>1</value> 8357 </enumeratedValue> 8358 </enumeratedValues> 8359 </field> 8360 <field> 8361 <name>TXEMPTY</name> 8362 <description>Wake on TX FIFO Empty.</description> 8363 <bitOffset>1</bitOffset> 8364 <bitWidth>1</bitWidth> 8365 <enumeratedValues> 8366 <enumeratedValue> 8367 <name>clear</name> 8368 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8369 <value>1</value> 8370 </enumeratedValue> 8371 </enumeratedValues> 8372 </field> 8373 <field> 8374 <name>RXTHRLD</name> 8375 <description>Wake on RX FIFO Threshold Crossed.</description> 8376 <bitOffset>2</bitOffset> 8377 <bitWidth>1</bitWidth> 8378 <enumeratedValues> 8379 <enumeratedValue> 8380 <name>clear</name> 8381 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8382 <value>1</value> 8383 </enumeratedValue> 8384 </enumeratedValues> 8385 </field> 8386 <field> 8387 <name>RXFULL</name> 8388 <description>Wake on RX FIFO Full.</description> 8389 <bitOffset>3</bitOffset> 8390 <bitWidth>1</bitWidth> 8391 <enumeratedValues> 8392 <enumeratedValue> 8393 <name>clear</name> 8394 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 8395 <value>1</value> 8396 </enumeratedValue> 8397 </enumeratedValues> 8398 </field> 8399 </fields> 8400 </register> 8401 <register> 8402 <name>WAKE_EN</name> 8403 <description>Register for wake up enable.</description> 8404 <addressOffset>0x2C</addressOffset> 8405 <access>read-write</access> 8406 <fields> 8407 <field> 8408 <name>TXTHRLD</name> 8409 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 8410 <bitOffset>0</bitOffset> 8411 <bitWidth>1</bitWidth> 8412 <enumeratedValues> 8413 <enumeratedValue> 8414 <name>dis</name> 8415 <description>Wakeup source disabled.</description> 8416 <value>0</value> 8417 </enumeratedValue> 8418 <enumeratedValue> 8419 <name>en</name> 8420 <description>Wakeup source enabled.</description> 8421 <value>1</value> 8422 </enumeratedValue> 8423 </enumeratedValues> 8424 </field> 8425 <field> 8426 <name>TXEMPTY</name> 8427 <description>Wake on TX FIFO Empty Enable.</description> 8428 <bitOffset>1</bitOffset> 8429 <bitWidth>1</bitWidth> 8430 <enumeratedValues> 8431 <enumeratedValue> 8432 <name>dis</name> 8433 <description>Wakeup source disabled.</description> 8434 <value>0</value> 8435 </enumeratedValue> 8436 <enumeratedValue> 8437 <name>en</name> 8438 <description>Wakeup source enabled.</description> 8439 <value>1</value> 8440 </enumeratedValue> 8441 </enumeratedValues> 8442 </field> 8443 <field> 8444 <name>RXTHRLD</name> 8445 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 8446 <bitOffset>2</bitOffset> 8447 <bitWidth>1</bitWidth> 8448 <enumeratedValues> 8449 <enumeratedValue> 8450 <name>dis</name> 8451 <description>Wakeup source disabled.</description> 8452 <value>0</value> 8453 </enumeratedValue> 8454 <enumeratedValue> 8455 <name>en</name> 8456 <description>Wakeup source enabled.</description> 8457 <value>1</value> 8458 </enumeratedValue> 8459 </enumeratedValues> 8460 </field> 8461 <field> 8462 <name>RXFULL</name> 8463 <description>Wake on RX FIFO Full Enable.</description> 8464 <bitOffset>3</bitOffset> 8465 <bitWidth>1</bitWidth> 8466 <enumeratedValues> 8467 <enumeratedValue> 8468 <name>dis</name> 8469 <description>Wakeup source disabled.</description> 8470 <value>0</value> 8471 </enumeratedValue> 8472 <enumeratedValue> 8473 <name>en</name> 8474 <description>Wakeup source enabled.</description> 8475 <value>1</value> 8476 </enumeratedValue> 8477 </enumeratedValues> 8478 </field> 8479 </fields> 8480 </register> 8481 <register> 8482 <name>STAT</name> 8483 <description>SPI Status register.</description> 8484 <addressOffset>0x30</addressOffset> 8485 <access>read-only</access> 8486 <fields> 8487 <field> 8488 <name>BUSY</name> 8489 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 8490 <bitOffset>0</bitOffset> 8491 <bitWidth>1</bitWidth> 8492 <enumeratedValues> 8493 <enumeratedValue> 8494 <name>inactive</name> 8495 <description>SPI not active.</description> 8496 <value>0</value> 8497 </enumeratedValue> 8498 <enumeratedValue> 8499 <name>active</name> 8500 <description>SPI active.</description> 8501 <value>1</value> 8502 </enumeratedValue> 8503 </enumeratedValues> 8504 </field> 8505 </fields> 8506 </register> 8507 </registers> 8508 </peripheral> 8509<!--SPI0 SPI peripheral.--> 8510 <peripheral derivedFrom="SPI0"> 8511 <name>SPI1</name> 8512 <description>SPI peripheral. 1</description> 8513 <baseAddress>0x40047000</baseAddress> 8514 <interrupt> 8515 <name>SPI1</name> 8516 <description>SPI1 IRQ</description> 8517 <value>17</value> 8518 </interrupt> 8519 </peripheral> 8520<!--SPI1 SPI peripheral. 1--> 8521 <peripheral> 8522 <name>TMR0</name> 8523 <description>32-bit reloadable timer that can be used for timing and event counting.</description> 8524 <groupName>Timers</groupName> 8525 <baseAddress>0x40010000</baseAddress> 8526 <addressBlock> 8527 <offset>0x00</offset> 8528 <size>0x1000</size> 8529 <usage>registers</usage> 8530 </addressBlock> 8531 <interrupt> 8532 <name>TMR0</name> 8533 <description>TMR0 IRQ</description> 8534 <value>5</value> 8535 </interrupt> 8536 <registers> 8537 <register> 8538 <name>CNT</name> 8539 <description>Count. This register stores the current timer count.</description> 8540 <addressOffset>0x00</addressOffset> 8541 <resetValue>0x00000001</resetValue> 8542 </register> 8543 <register> 8544 <name>CMP</name> 8545 <description>Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.</description> 8546 <addressOffset>0x04</addressOffset> 8547 <resetValue>0x0000FFFF</resetValue> 8548 </register> 8549 <register> 8550 <name>PWM</name> 8551 <description>PWM. This register stores the value that is compared to the current timer count.</description> 8552 <addressOffset>0x08</addressOffset> 8553 </register> 8554 <register> 8555 <name>INTR</name> 8556 <description>Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.</description> 8557 <addressOffset>0x0C</addressOffset> 8558 <modifiedWriteValues>oneToClear</modifiedWriteValues> 8559 <fields> 8560 <field> 8561 <name>IRQ_CLR</name> 8562 <description>Clear Interrupt.</description> 8563 <bitOffset>0</bitOffset> 8564 <bitWidth>1</bitWidth> 8565 </field> 8566 </fields> 8567 </register> 8568 <register> 8569 <name>CN</name> 8570 <description>Timer Control Register.</description> 8571 <addressOffset>0x10</addressOffset> 8572 <fields> 8573 <field> 8574 <name>TMODE</name> 8575 <description>Timer Mode.</description> 8576 <bitOffset>0</bitOffset> 8577 <bitWidth>3</bitWidth> 8578 <enumeratedValues> 8579 <enumeratedValue> 8580 <name>oneShot</name> 8581 <description>One Shot Mode.</description> 8582 <value>0</value> 8583 </enumeratedValue> 8584 <enumeratedValue> 8585 <name>continuous</name> 8586 <description>Continuous Mode.</description> 8587 <value>1</value> 8588 </enumeratedValue> 8589 <enumeratedValue> 8590 <name>counter</name> 8591 <description>Counter Mode.</description> 8592 <value>2</value> 8593 </enumeratedValue> 8594 <enumeratedValue> 8595 <name>pwm</name> 8596 <description>PWM Mode.</description> 8597 <value>3</value> 8598 </enumeratedValue> 8599 <enumeratedValue> 8600 <name>capture</name> 8601 <description>Capture Mode.</description> 8602 <value>4</value> 8603 </enumeratedValue> 8604 <enumeratedValue> 8605 <name>compare</name> 8606 <description>Compare Mode.</description> 8607 <value>5</value> 8608 </enumeratedValue> 8609 <enumeratedValue> 8610 <name>gated</name> 8611 <description>Gated Mode.</description> 8612 <value>6</value> 8613 </enumeratedValue> 8614 <enumeratedValue> 8615 <name>captureCompare</name> 8616 <description>Capture/Compare Mode.</description> 8617 <value>7</value> 8618 </enumeratedValue> 8619 </enumeratedValues> 8620 </field> 8621 <field> 8622 <name>PRES</name> 8623 <description>Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].</description> 8624 <bitOffset>3</bitOffset> 8625 <bitWidth>3</bitWidth> 8626 <enumeratedValues> 8627 <enumeratedValue> 8628 <name>div1</name> 8629 <description>Divide by 1.</description> 8630 <value>0</value> 8631 </enumeratedValue> 8632 <enumeratedValue> 8633 <name>div2</name> 8634 <description>Divide by 2.</description> 8635 <value>1</value> 8636 </enumeratedValue> 8637 <enumeratedValue> 8638 <name>div4</name> 8639 <description>Divide by 4.</description> 8640 <value>2</value> 8641 </enumeratedValue> 8642 <enumeratedValue> 8643 <name>div8</name> 8644 <description>Divide by 8.</description> 8645 <value>3</value> 8646 </enumeratedValue> 8647 <enumeratedValue> 8648 <name>div16</name> 8649 <description>Divide by 16.</description> 8650 <value>4</value> 8651 </enumeratedValue> 8652 <enumeratedValue> 8653 <name>div32</name> 8654 <description>Divide by 32.</description> 8655 <value>5</value> 8656 </enumeratedValue> 8657 <enumeratedValue> 8658 <name>div64</name> 8659 <description>Divide by 64.</description> 8660 <value>6</value> 8661 </enumeratedValue> 8662 <enumeratedValue> 8663 <name>div128</name> 8664 <description>Divide by 128.</description> 8665 <value>7</value> 8666 </enumeratedValue> 8667 </enumeratedValues> 8668 </field> 8669 <field> 8670 <name>TPOL</name> 8671 <description>Timer input/output polarity bit.</description> 8672 <bitOffset>6</bitOffset> 8673 <bitWidth>1</bitWidth> 8674 <enumeratedValues> 8675 <enumeratedValue> 8676 <name>activeHi</name> 8677 <description>Active High.</description> 8678 <value>0</value> 8679 </enumeratedValue> 8680 <enumeratedValue> 8681 <name>activeLo</name> 8682 <description>Active Low.</description> 8683 <value>1</value> 8684 </enumeratedValue> 8685 </enumeratedValues> 8686 </field> 8687 <field> 8688 <name>TEN</name> 8689 <description>Timer Enable.</description> 8690 <bitOffset>7</bitOffset> 8691 <bitWidth>1</bitWidth> 8692 <enumeratedValues> 8693 <enumeratedValue> 8694 <name>dis</name> 8695 <description>Disable.</description> 8696 <value>0</value> 8697 </enumeratedValue> 8698 <enumeratedValue> 8699 <name>en</name> 8700 <description>Enable.</description> 8701 <value>1</value> 8702 </enumeratedValue> 8703 </enumeratedValues> 8704 </field> 8705 <field> 8706 <name>PRES3</name> 8707 <description>MSB of prescaler value.</description> 8708 <bitOffset>8</bitOffset> 8709 <bitWidth>1</bitWidth> 8710 </field> 8711 <field> 8712 <name>PWMSYNC</name> 8713 <description>Timer PWM Synchronization Mode Enable.</description> 8714 <bitOffset>9</bitOffset> 8715 <bitWidth>1</bitWidth> 8716 <enumeratedValues> 8717 <enumeratedValue> 8718 <name>dis</name> 8719 <description>Disable.</description> 8720 <value>0</value> 8721 </enumeratedValue> 8722 <enumeratedValue> 8723 <name>en</name> 8724 <description>Enable.</description> 8725 <value>1</value> 8726 </enumeratedValue> 8727 </enumeratedValues> 8728 </field> 8729 <field> 8730 <name>NOLHPOL</name> 8731 <description>Timer PWM output 0A polarity bit.</description> 8732 <bitOffset>10</bitOffset> 8733 <bitWidth>1</bitWidth> 8734 <enumeratedValues> 8735 <enumeratedValue> 8736 <name>dis</name> 8737 <description>Disable.</description> 8738 <value>0</value> 8739 </enumeratedValue> 8740 <enumeratedValue> 8741 <name>en</name> 8742 <description>Enable.</description> 8743 <value>1</value> 8744 </enumeratedValue> 8745 </enumeratedValues> 8746 </field> 8747 <field> 8748 <name>NOLLPOL</name> 8749 <description>Timer PWM output 0A' polarity bit.</description> 8750 <bitOffset>11</bitOffset> 8751 <bitWidth>1</bitWidth> 8752 <enumeratedValues> 8753 <enumeratedValue> 8754 <name>dis</name> 8755 <description>Disable.</description> 8756 <value>0</value> 8757 </enumeratedValue> 8758 <enumeratedValue> 8759 <name>en</name> 8760 <description>Enable.</description> 8761 <value>1</value> 8762 </enumeratedValue> 8763 </enumeratedValues> 8764 </field> 8765 <field> 8766 <name>PWMCKBD</name> 8767 <description>Timer PWM output 0A Mode Disable.</description> 8768 <bitOffset>12</bitOffset> 8769 <bitWidth>1</bitWidth> 8770 <enumeratedValues> 8771 <enumeratedValue> 8772 <name>dis</name> 8773 <description>Disable.</description> 8774 <value>1</value> 8775 </enumeratedValue> 8776 <enumeratedValue> 8777 <name>en</name> 8778 <description>Enable.</description> 8779 <value>0</value> 8780 </enumeratedValue> 8781 </enumeratedValues> 8782 </field> 8783 </fields> 8784 </register> 8785 </registers> 8786 </peripheral> 8787<!--TMR0 32-bit reloadable timer that can be used for timing and event counting.--> 8788 <peripheral derivedFrom="TMR0"> 8789 <name>TMR1</name> 8790 <description>32-bit reloadable timer that can be used for timing and event counting. 1</description> 8791 <baseAddress>0x40011000</baseAddress> 8792 <interrupt> 8793 <name>TMR1</name> 8794 <description>TMR1 IRQ</description> 8795 <value>6</value> 8796 </interrupt> 8797 </peripheral> 8798<!--TMR1 32-bit reloadable timer that can be used for timing and event counting. 1--> 8799 <peripheral derivedFrom="TMR0"> 8800 <name>TMR2</name> 8801 <description>32-bit reloadable timer that can be used for timing and event counting. 2</description> 8802 <baseAddress>0x40012000</baseAddress> 8803 <interrupt> 8804 <name>TMR2</name> 8805 <description>TMR2 IRQ</description> 8806 <value>7</value> 8807 </interrupt> 8808 </peripheral> 8809<!--TMR2 32-bit reloadable timer that can be used for timing and event counting. 2--> 8810 <peripheral derivedFrom="TMR0"> 8811 <name>TMR3</name> 8812 <description>32-bit reloadable timer that can be used for timing and event counting. 3</description> 8813 <baseAddress>0x40013000</baseAddress> 8814 <interrupt> 8815 <name>TMR3</name> 8816 <description>TMR3 IRQ</description> 8817 <value>8</value> 8818 </interrupt> 8819 </peripheral> 8820<!--TMR3 32-bit reloadable timer that can be used for timing and event counting. 3--> 8821 <peripheral> 8822 <name>TRNG</name> 8823 <description>Random Number Generator.</description> 8824 <baseAddress>0x4004D000</baseAddress> 8825 <addressBlock> 8826 <offset>0x00</offset> 8827 <size>0x1000</size> 8828 <usage>registers</usage> 8829 </addressBlock> 8830 <interrupt> 8831 <name>TRNG</name> 8832 <description>TRNG interrupt.</description> 8833 <value>4</value> 8834 </interrupt> 8835 <registers> 8836 <register> 8837 <name>CN</name> 8838 <description>TRNG Control Register.</description> 8839 <addressOffset>0x00</addressOffset> 8840 <resetValue>0x00000003</resetValue> 8841 <fields> 8842 <field> 8843 <name>RND_IRQ_EN</name> 8844 <description>To enable IRQ generation when a new 32-bit Random number is ready.</description> 8845 <bitOffset>1</bitOffset> 8846 <bitWidth>1</bitWidth> 8847 <enumeratedValues> 8848 <enumeratedValue> 8849 <name>disable</name> 8850 <description>Disable</description> 8851 <value>0</value> 8852 </enumeratedValue> 8853 <enumeratedValue> 8854 <name>enable</name> 8855 <description>Enable</description> 8856 <value>1</value> 8857 </enumeratedValue> 8858 </enumeratedValues> 8859 </field> 8860 <field> 8861 <name>AESKG_MEMPROTE</name> 8862 <description>AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.</description> 8863 <bitOffset>4</bitOffset> 8864 <bitWidth>1</bitWidth> 8865 </field> 8866 </fields> 8867 </register> 8868 <register> 8869 <name>ST</name> 8870 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 8871 <addressOffset>0x04</addressOffset> 8872 <access>read-only</access> 8873 <fields> 8874 <field> 8875 <name>RND_RDY</name> 8876 <description>32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.</description> 8877 <bitOffset>0</bitOffset> 8878 <bitWidth>1</bitWidth> 8879 <enumeratedValues> 8880 <enumeratedValue> 8881 <name>Busy</name> 8882 <description>TRNG Busy</description> 8883 <value>0</value> 8884 </enumeratedValue> 8885 <enumeratedValue> 8886 <name>Ready</name> 8887 <description>32 bit random data is ready</description> 8888 <value>1</value> 8889 </enumeratedValue> 8890 </enumeratedValues> 8891 </field> 8892 <field> 8893 <name>AESKGD_MEU_S</name> 8894 <description>Automatically AES transfer on going</description> 8895 <bitOffset>4</bitOffset> 8896 <bitWidth>1</bitWidth> 8897 </field> 8898 </fields> 8899 </register> 8900 <register> 8901 <name>DATA</name> 8902 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 8903 <addressOffset>0x08</addressOffset> 8904 <access>read-only</access> 8905 <fields> 8906 <field> 8907 <name>DATA</name> 8908 <description>Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.</description> 8909 <bitOffset>0</bitOffset> 8910 <bitWidth>32</bitWidth> 8911 </field> 8912 </fields> 8913 </register> 8914 </registers> 8915 </peripheral> 8916<!--TRNG Random Number Generator.--> 8917 <peripheral> 8918 <name>UART0</name> 8919 <description>UART</description> 8920 <baseAddress>0x40042000</baseAddress> 8921 <addressBlock> 8922 <offset>0</offset> 8923 <size>0x1000</size> 8924 <usage>registers</usage> 8925 </addressBlock> 8926 <interrupt> 8927 <name>UART0</name> 8928 <description>UART0 IRQ</description> 8929 <value>14</value> 8930 </interrupt> 8931 <registers> 8932 <register> 8933 <name>CTRL</name> 8934 <description>Control Register.</description> 8935 <addressOffset>0x00</addressOffset> 8936 <size>32</size> 8937 <fields> 8938 <field> 8939 <name>RXTHD</name> 8940 <description>Receive Threshhold.</description> 8941 <bitOffset>0</bitOffset> 8942 <bitWidth>4</bitWidth> 8943 </field> 8944 <field> 8945 <name>PAREN</name> 8946 <description>Enable/disable Parity bit (9th character).</description> 8947 <bitOffset>4</bitOffset> 8948 <bitWidth>1</bitWidth> 8949 <enumeratedValues> 8950 <enumeratedValue> 8951 <name>dis</name> 8952 <description>No Parity </description> 8953 <value>0</value> 8954 </enumeratedValue> 8955 <enumeratedValue> 8956 <name>en</name> 8957 <description>Parity enabled as 9th bit</description> 8958 <value>1</value> 8959 </enumeratedValue> 8960 </enumeratedValues> 8961 </field> 8962 <field> 8963 <name>PAREO</name> 8964 <description>When PARITY_EN=1, selects odd or even parity.</description> 8965 <bitOffset>5</bitOffset> 8966 <bitWidth>1</bitWidth> 8967 <enumeratedValues> 8968 <enumeratedValue> 8969 <name>Even</name> 8970 <description>Even parity selected.</description> 8971 <value>0</value> 8972 </enumeratedValue> 8973 <enumeratedValue> 8974 <name>ODD</name> 8975 <description>Odd parity selected.</description> 8976 <value>1</value> 8977 </enumeratedValue> 8978 </enumeratedValues> 8979 </field> 8980 <field> 8981 <name>PARMD</name> 8982 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 8983 <bitOffset>6</bitOffset> 8984 <bitWidth>1</bitWidth> 8985 <enumeratedValues> 8986 <enumeratedValue> 8987 <name>1</name> 8988 <description>Parity calculation is based on number of 1s in frame.</description> 8989 <value>0</value> 8990 </enumeratedValue> 8991 <enumeratedValue> 8992 <name>0</name> 8993 <description>Parity calculation is based on number of 0s in frame.</description> 8994 <value>1</value> 8995 </enumeratedValue> 8996 </enumeratedValues> 8997 </field> 8998 <field> 8999 <name>TXFLUSH</name> 9000 <description>Flushes the TX FIFO buffer.</description> 9001 <bitOffset>8</bitOffset> 9002 <bitWidth>1</bitWidth> 9003 </field> 9004 <field> 9005 <name>RXFLUSH</name> 9006 <description>Flushes the RX FIFO buffer.</description> 9007 <bitOffset>9</bitOffset> 9008 <bitWidth>1</bitWidth> 9009 </field> 9010 <field> 9011 <name>SIZE</name> 9012 <description>Selects UART character size.</description> 9013 <bitOffset>10</bitOffset> 9014 <bitWidth>2</bitWidth> 9015 <enumeratedValues> 9016 <enumeratedValue> 9017 <name>5</name> 9018 <description>5 bits.</description> 9019 <value>0</value> 9020 </enumeratedValue> 9021 <enumeratedValue> 9022 <name>6</name> 9023 <description>6 bits.</description> 9024 <value>1</value> 9025 </enumeratedValue> 9026 <enumeratedValue> 9027 <name>7</name> 9028 <description>7 bits.</description> 9029 <value>2</value> 9030 </enumeratedValue> 9031 <enumeratedValue> 9032 <name>8</name> 9033 <description>8 bits.</description> 9034 <value>3</value> 9035 </enumeratedValue> 9036 </enumeratedValues> 9037 </field> 9038 <field> 9039 <name>STOP</name> 9040 <description>Selects the number of stop bits that will be generated.</description> 9041 <bitOffset>12</bitOffset> 9042 <bitWidth>1</bitWidth> 9043 <enumeratedValues> 9044 <enumeratedValue> 9045 <name>1</name> 9046 <description>1 stop bit.</description> 9047 <value>0</value> 9048 </enumeratedValue> 9049 <enumeratedValue> 9050 <name>1_5</name> 9051 <description>1.5 stop bits.</description> 9052 <value>1</value> 9053 </enumeratedValue> 9054 </enumeratedValues> 9055 </field> 9056 </fields> 9057 </register> 9058 <register> 9059 <name>STAT</name> 9060 <description>Status Register.</description> 9061 <addressOffset>0x04</addressOffset> 9062 <size>32</size> 9063 <access>read-only</access> 9064 <fields> 9065 <field> 9066 <name>TXBUSY</name> 9067 <description>Read-only flag indicating the UART transmit status.</description> 9068 <bitOffset>0</bitOffset> 9069 <bitWidth>1</bitWidth> 9070 <access>read-only</access> 9071 </field> 9072 <field> 9073 <name>RXBUSY</name> 9074 <description>Read-only flag indicating the UART receiver status.</description> 9075 <bitOffset>1</bitOffset> 9076 <bitWidth>1</bitWidth> 9077 <access>read-only</access> 9078 </field> 9079 <field> 9080 <name>RXEMPTY</name> 9081 <description>Read-only flag indicating the RX FIFO state.</description> 9082 <bitOffset>4</bitOffset> 9083 <bitWidth>1</bitWidth> 9084 <access>read-only</access> 9085 </field> 9086 <field> 9087 <name>RXFULL</name> 9088 <description>Read-only flag indicating the RX FIFO state.</description> 9089 <bitOffset>5</bitOffset> 9090 <bitWidth>1</bitWidth> 9091 <access>read-only</access> 9092 </field> 9093 <field> 9094 <name>TXEMPTY</name> 9095 <description>Read-only flag indicating the TX FIFO state.</description> 9096 <bitOffset>6</bitOffset> 9097 <bitWidth>1</bitWidth> 9098 <access>read-only</access> 9099 </field> 9100 <field> 9101 <name>TXFULL</name> 9102 <description>Read-only flag indicating the TX FIFO state.</description> 9103 <bitOffset>7</bitOffset> 9104 <bitWidth>1</bitWidth> 9105 <access>read-only</access> 9106 </field> 9107 <field> 9108 <name>RXELT</name> 9109 <description>Indicates the number of bytes currently in the RX FIFO.</description> 9110 <bitOffset>8</bitOffset> 9111 <bitWidth>4</bitWidth> 9112 <access>read-only</access> 9113 </field> 9114 <field> 9115 <name>TXELT</name> 9116 <description>Indicates the number of bytes currently in the TX FIFO.</description> 9117 <bitOffset>12</bitOffset> 9118 <bitWidth>4</bitWidth> 9119 <access>read-only</access> 9120 </field> 9121 </fields> 9122 </register> 9123 <register> 9124 <name>INT_EN</name> 9125 <description>Interrupt Enable Register.</description> 9126 <addressOffset>0x08</addressOffset> 9127 <size>32</size> 9128 <fields> 9129 <field> 9130 <name>FRAMIE</name> 9131 <description>Enable for RX Frame Error Interrupt.</description> 9132 <bitOffset>0</bitOffset> 9133 <bitWidth>1</bitWidth> 9134 </field> 9135 <field> 9136 <name>PARITYIE</name> 9137 <description>Enable for RX Parity Error interrupt.</description> 9138 <bitOffset>1</bitOffset> 9139 <bitWidth>1</bitWidth> 9140 </field> 9141 <field> 9142 <name>OVERIE</name> 9143 <description>Enable for RX FIFO OVerrun interrupt.</description> 9144 <bitOffset>3</bitOffset> 9145 <bitWidth>1</bitWidth> 9146 </field> 9147 <field> 9148 <name>FFRXIE</name> 9149 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 9150 <bitOffset>4</bitOffset> 9151 <bitWidth>1</bitWidth> 9152 </field> 9153 <field> 9154 <name>FFTXOIE</name> 9155 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 9156 <bitOffset>5</bitOffset> 9157 <bitWidth>1</bitWidth> 9158 </field> 9159 <field> 9160 <name>FFTXHIE</name> 9161 <description>Enable for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less.</description> 9162 <bitOffset>6</bitOffset> 9163 <bitWidth>1</bitWidth> 9164 </field> 9165 </fields> 9166 </register> 9167 <register> 9168 <name>INT_STAT</name> 9169 <description>Interrupt Status Flags.</description> 9170 <addressOffset>0x0C</addressOffset> 9171 <size>32</size> 9172 <modifiedWriteValues>oneToClear</modifiedWriteValues> 9173 <fields> 9174 <field> 9175 <name>FRAMIS</name> 9176 <description>FLAG for RX Frame Error Interrupt.</description> 9177 <bitOffset>0</bitOffset> 9178 <bitWidth>1</bitWidth> 9179 </field> 9180 <field> 9181 <name>PARITYIS</name> 9182 <description>FLAG for RX Parity Error interrupt.</description> 9183 <bitOffset>1</bitOffset> 9184 <bitWidth>1</bitWidth> 9185 </field> 9186 <field> 9187 <name>OVERIS</name> 9188 <description>FLAG for RX FIFO Overrun interrupt.</description> 9189 <bitOffset>3</bitOffset> 9190 <bitWidth>1</bitWidth> 9191 </field> 9192 <field> 9193 <name>FFRXIS</name> 9194 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 9195 <bitOffset>4</bitOffset> 9196 <bitWidth>1</bitWidth> 9197 </field> 9198 <field> 9199 <name>FFTXOIS</name> 9200 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 9201 <bitOffset>5</bitOffset> 9202 <bitWidth>1</bitWidth> 9203 </field> 9204 <field> 9205 <name>FFTXHIS</name> 9206 <description>FLAG for interrupt when TX FIFO reaches half the number of bytes allowed in the fifo or less.</description> 9207 <bitOffset>6</bitOffset> 9208 <bitWidth>1</bitWidth> 9209 </field> 9210 </fields> 9211 </register> 9212 <register> 9213 <name>BAUD0</name> 9214 <description>Baud rate register. Integer portion.</description> 9215 <addressOffset>0x10</addressOffset> 9216 <size>32</size> 9217 <fields> 9218 <field> 9219 <name>IDIV</name> 9220 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 9221 <bitOffset>0</bitOffset> 9222 <bitWidth>12</bitWidth> 9223 </field> 9224 </fields> 9225 </register> 9226 <register> 9227 <name>BAUD1</name> 9228 <description>Baud rate register. Decimal Setting.</description> 9229 <addressOffset>0x14</addressOffset> 9230 <size>32</size> 9231 <fields> 9232 <field> 9233 <name>DDIV</name> 9234 <description>Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.</description> 9235 <bitOffset>0</bitOffset> 9236 <bitWidth>7</bitWidth> 9237 </field> 9238 </fields> 9239 </register> 9240 <register> 9241 <name>DATA</name> 9242 <description>FIFO Data buffer.</description> 9243 <addressOffset>0x20</addressOffset> 9244 <size>32</size> 9245 <fields> 9246 <field> 9247 <name>DATA</name> 9248 <description>Load/unload location for TX and RX FIFO buffers.</description> 9249 <bitOffset>0</bitOffset> 9250 <bitWidth>8</bitWidth> 9251 </field> 9252 <field> 9253 <name>PARITY</name> 9254 <description>Parity error flag for next byte to be read from FIFO.</description> 9255 <bitOffset>8</bitOffset> 9256 <bitWidth>1</bitWidth> 9257 </field> 9258 </fields> 9259 </register> 9260 <register> 9261 <name>DMA</name> 9262 <description>DMA Configuration.</description> 9263 <addressOffset>0x30</addressOffset> 9264 <size>32</size> 9265 <fields> 9266 <field> 9267 <name>TXCNT</name> 9268 <description>TX threshold for DMA transmission.</description> 9269 <bitOffset>0</bitOffset> 9270 <bitWidth>4</bitWidth> 9271 </field> 9272 <field> 9273 <name>TXEN</name> 9274 <description>TX DMA channel enable.</description> 9275 <bitOffset>4</bitOffset> 9276 <bitWidth>1</bitWidth> 9277 <enumeratedValues> 9278 <enumeratedValue> 9279 <name>dis</name> 9280 <description>DMA is disabled </description> 9281 <value>0</value> 9282 </enumeratedValue> 9283 <enumeratedValue> 9284 <name>en</name> 9285 <description>DMA is enabled </description> 9286 <value>1</value> 9287 </enumeratedValue> 9288 </enumeratedValues> 9289 </field> 9290 <field> 9291 <name>RXCNT</name> 9292 <description>RX threshold for DMA transmission.</description> 9293 <bitOffset>5</bitOffset> 9294 <bitWidth>4</bitWidth> 9295 </field> 9296 <field> 9297 <name>RXEN</name> 9298 <description>RX DMA channel enable.</description> 9299 <bitOffset>9</bitOffset> 9300 <bitWidth>1</bitWidth> 9301 <enumeratedValues> 9302 <enumeratedValue> 9303 <name>dis</name> 9304 <description>DMA is disabled </description> 9305 <value>0</value> 9306 </enumeratedValue> 9307 <enumeratedValue> 9308 <name>en</name> 9309 <description>DMA is enabled </description> 9310 <value>1</value> 9311 </enumeratedValue> 9312 </enumeratedValues> 9313 </field> 9314 </fields> 9315 </register> 9316 </registers> 9317 </peripheral> 9318<!--UART0 UART--> 9319 <peripheral> 9320 <name>WDT0</name> 9321 <description>Watchdog Timer 0</description> 9322 <baseAddress>0x40003000</baseAddress> 9323 <addressBlock> 9324 <offset>0x00</offset> 9325 <size>0x0400</size> 9326 <usage>registers</usage> 9327 </addressBlock> 9328 <interrupt> 9329 <name>WDT0</name> 9330 <value>1</value> 9331 </interrupt> 9332 <registers> 9333 <register> 9334 <name>CTRL</name> 9335 <description>Watchdog Timer Control Register.</description> 9336 <addressOffset>0x00</addressOffset> 9337 <resetMask>0x7FFFF000</resetMask> 9338 <fields> 9339 <field> 9340 <name>INT_PERIOD</name> 9341 <description>Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 9342 <bitOffset>0</bitOffset> 9343 <bitWidth>4</bitWidth> 9344 <enumeratedValues> 9345 <enumeratedValue> 9346 <name>wdt2pow31</name> 9347 <description>2**31 clock cycles.</description> 9348 <value>0</value> 9349 </enumeratedValue> 9350 <enumeratedValue> 9351 <name>wdt2pow30</name> 9352 <description>2**30 clock cycles.</description> 9353 <value>1</value> 9354 </enumeratedValue> 9355 <enumeratedValue> 9356 <name>wdt2pow29</name> 9357 <description>2**29 clock cycles.</description> 9358 <value>2</value> 9359 </enumeratedValue> 9360 <enumeratedValue> 9361 <name>wdt2pow28</name> 9362 <description>2**28 clock cycles.</description> 9363 <value>3</value> 9364 </enumeratedValue> 9365 <enumeratedValue> 9366 <name>wdt2pow27</name> 9367 <description>2^27 clock cycles.</description> 9368 <value>4</value> 9369 </enumeratedValue> 9370 <enumeratedValue> 9371 <name>wdt2pow26</name> 9372 <description>2**26 clock cycles.</description> 9373 <value>5</value> 9374 </enumeratedValue> 9375 <enumeratedValue> 9376 <name>wdt2pow25</name> 9377 <description>2**25 clock cycles.</description> 9378 <value>6</value> 9379 </enumeratedValue> 9380 <enumeratedValue> 9381 <name>wdt2pow24</name> 9382 <description>2**24 clock cycles.</description> 9383 <value>7</value> 9384 </enumeratedValue> 9385 <enumeratedValue> 9386 <name>wdt2pow23</name> 9387 <description>2**23 clock cycles.</description> 9388 <value>8</value> 9389 </enumeratedValue> 9390 <enumeratedValue> 9391 <name>wdt2pow22</name> 9392 <description>2**22 clock cycles.</description> 9393 <value>9</value> 9394 </enumeratedValue> 9395 <enumeratedValue> 9396 <name>wdt2pow21</name> 9397 <description>2**21 clock cycles.</description> 9398 <value>10</value> 9399 </enumeratedValue> 9400 <enumeratedValue> 9401 <name>wdt2pow20</name> 9402 <description>2**20 clock cycles.</description> 9403 <value>11</value> 9404 </enumeratedValue> 9405 <enumeratedValue> 9406 <name>wdt2pow19</name> 9407 <description>2**19 clock cycles.</description> 9408 <value>12</value> 9409 </enumeratedValue> 9410 <enumeratedValue> 9411 <name>wdt2pow18</name> 9412 <description>2**18 clock cycles.</description> 9413 <value>13</value> 9414 </enumeratedValue> 9415 <enumeratedValue> 9416 <name>wdt2pow17</name> 9417 <description>2**17 clock cycles.</description> 9418 <value>14</value> 9419 </enumeratedValue> 9420 <enumeratedValue> 9421 <name>wdt2pow16</name> 9422 <description>2**16 clock cycles.</description> 9423 <value>15</value> 9424 </enumeratedValue> 9425 </enumeratedValues> 9426 </field> 9427 <field> 9428 <name>RST_PERIOD</name> 9429 <description>Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 9430 <bitOffset>4</bitOffset> 9431 <bitWidth>4</bitWidth> 9432 <enumeratedValues> 9433 <enumeratedValue> 9434 <name>wdt2pow31</name> 9435 <description>2**31 clock cycles.</description> 9436 <value>0</value> 9437 </enumeratedValue> 9438 <enumeratedValue> 9439 <name>wdt2pow30</name> 9440 <description>2**30 clock cycles.</description> 9441 <value>1</value> 9442 </enumeratedValue> 9443 <enumeratedValue> 9444 <name>wdt2pow29</name> 9445 <description>2**29 clock cycles.</description> 9446 <value>2</value> 9447 </enumeratedValue> 9448 <enumeratedValue> 9449 <name>wdt2pow28</name> 9450 <description>2**28 clock cycles.</description> 9451 <value>3</value> 9452 </enumeratedValue> 9453 <enumeratedValue> 9454 <name>wdt2pow27</name> 9455 <description>2^27 clock cycles.</description> 9456 <value>4</value> 9457 </enumeratedValue> 9458 <enumeratedValue> 9459 <name>wdt2pow26</name> 9460 <description>2**26 clock cycles.</description> 9461 <value>5</value> 9462 </enumeratedValue> 9463 <enumeratedValue> 9464 <name>wdt2pow25</name> 9465 <description>2**25 clock cycles.</description> 9466 <value>6</value> 9467 </enumeratedValue> 9468 <enumeratedValue> 9469 <name>wdt2pow24</name> 9470 <description>2**24 clock cycles.</description> 9471 <value>7</value> 9472 </enumeratedValue> 9473 <enumeratedValue> 9474 <name>wdt2pow23</name> 9475 <description>2**23 clock cycles.</description> 9476 <value>8</value> 9477 </enumeratedValue> 9478 <enumeratedValue> 9479 <name>wdt2pow22</name> 9480 <description>2**22 clock cycles.</description> 9481 <value>9</value> 9482 </enumeratedValue> 9483 <enumeratedValue> 9484 <name>wdt2pow21</name> 9485 <description>2**21 clock cycles.</description> 9486 <value>10</value> 9487 </enumeratedValue> 9488 <enumeratedValue> 9489 <name>wdt2pow20</name> 9490 <description>2**20 clock cycles.</description> 9491 <value>11</value> 9492 </enumeratedValue> 9493 <enumeratedValue> 9494 <name>wdt2pow19</name> 9495 <description>2**19 clock cycles.</description> 9496 <value>12</value> 9497 </enumeratedValue> 9498 <enumeratedValue> 9499 <name>wdt2pow18</name> 9500 <description>2**18 clock cycles.</description> 9501 <value>13</value> 9502 </enumeratedValue> 9503 <enumeratedValue> 9504 <name>wdt2pow17</name> 9505 <description>2**17 clock cycles.</description> 9506 <value>14</value> 9507 </enumeratedValue> 9508 <enumeratedValue> 9509 <name>wdt2pow16</name> 9510 <description>2**16 clock cycles.</description> 9511 <value>15</value> 9512 </enumeratedValue> 9513 </enumeratedValues> 9514 </field> 9515 <field> 9516 <name>WDT_EN</name> 9517 <description>Watchdog Timer Enable.</description> 9518 <bitOffset>8</bitOffset> 9519 <bitWidth>1</bitWidth> 9520 <enumeratedValues> 9521 <enumeratedValue> 9522 <name>dis</name> 9523 <description>Disable.</description> 9524 <value>0</value> 9525 </enumeratedValue> 9526 <enumeratedValue> 9527 <name>en</name> 9528 <description>Enable.</description> 9529 <value>1</value> 9530 </enumeratedValue> 9531 </enumeratedValues> 9532 </field> 9533 <field> 9534 <name>INT_FLAG</name> 9535 <description>Watchdog Timer Interrupt Flag.</description> 9536 <bitOffset>9</bitOffset> 9537 <bitWidth>1</bitWidth> 9538 <modifiedWriteValues>oneToClear</modifiedWriteValues> 9539 <enumeratedValues> 9540 <enumeratedValue> 9541 <name>inactive</name> 9542 <description>No interrupt is pending.</description> 9543 <value>0</value> 9544 </enumeratedValue> 9545 <enumeratedValue> 9546 <name>pending</name> 9547 <description>An interrupt is pending.</description> 9548 <value>1</value> 9549 </enumeratedValue> 9550 </enumeratedValues> 9551 </field> 9552 <field> 9553 <name>INT_EN</name> 9554 <description>Watchdog Timer Interrupt Enable.</description> 9555 <bitOffset>10</bitOffset> 9556 <bitWidth>1</bitWidth> 9557 <enumeratedValues> 9558 <enumeratedValue> 9559 <name>dis</name> 9560 <description>Disable.</description> 9561 <value>0</value> 9562 </enumeratedValue> 9563 <enumeratedValue> 9564 <name>en</name> 9565 <description>Enable.</description> 9566 <value>1</value> 9567 </enumeratedValue> 9568 </enumeratedValues> 9569 </field> 9570 <field> 9571 <name>RST_EN</name> 9572 <description>Watchdog Timer Reset Enable.</description> 9573 <bitOffset>11</bitOffset> 9574 <bitWidth>1</bitWidth> 9575 <enumeratedValues> 9576 <enumeratedValue> 9577 <name>dis</name> 9578 <description>Disable.</description> 9579 <value>0</value> 9580 </enumeratedValue> 9581 <enumeratedValue> 9582 <name>en</name> 9583 <description>Enable.</description> 9584 <value>1</value> 9585 </enumeratedValue> 9586 </enumeratedValues> 9587 </field> 9588 <field> 9589 <name>RST_FLAG</name> 9590 <description>Watchdog Timer Reset Flag.</description> 9591 <bitOffset>31</bitOffset> 9592 <bitWidth>1</bitWidth> 9593 <enumeratedValues> 9594 <usage>read-write</usage> 9595 <enumeratedValue> 9596 <name>noEvent</name> 9597 <description>The event has not occurred.</description> 9598 <value>0</value> 9599 </enumeratedValue> 9600 <enumeratedValue> 9601 <name>occurred</name> 9602 <description>The event has occurred.</description> 9603 <value>1</value> 9604 </enumeratedValue> 9605 </enumeratedValues> 9606 </field> 9607 </fields> 9608 </register> 9609 <register> 9610 <name>RST</name> 9611 <description>Watchdog Timer Reset Register.</description> 9612 <addressOffset>0x04</addressOffset> 9613 <access>write-only</access> 9614 <fields> 9615 <field> 9616 <name>WDT_RST</name> 9617 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.</description> 9618 <bitOffset>0</bitOffset> 9619 <bitWidth>8</bitWidth> 9620 <enumeratedValues> 9621 <enumeratedValue> 9622 <name>seq0</name> 9623 <description>The first value to be written to reset the WDT.</description> 9624 <value>0x000000A5</value> 9625 </enumeratedValue> 9626 <enumeratedValue> 9627 <name>seq1</name> 9628 <description>The second value to be written to reset the WDT.</description> 9629 <value>0x0000005A</value> 9630 </enumeratedValue> 9631 </enumeratedValues> 9632 </field> 9633 </fields> 9634 </register> 9635 </registers> 9636 </peripheral> 9637<!--WDT0 Watchdog Timer 0--> 9638 <peripheral derivedFrom="WDT0"> 9639 <name>WDT1</name> 9640 <description>Watchdog Timer 0 1</description> 9641 <baseAddress>0x40003400</baseAddress> 9642 <interrupt> 9643 <name>WDT1</name> 9644 <description>WDT1 IRQ</description> 9645 <value>57</value> 9646 </interrupt> 9647 </peripheral> 9648<!--WDT1 Watchdog Timer 0 1--> 9649 </peripherals> 9650</device> 9651
