1 /****************************************************************************** 2 * 3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 4 * Analog Devices, Inc.), 5 * Copyright (C) 2023-2024 Analog Devices, Inc. 6 * 7 * Licensed under the Apache License, Version 2.0 (the "License"); 8 * you may not use this file except in compliance with the License. 9 * You may obtain a copy of the License at 10 * 11 * http://www.apache.org/licenses/LICENSE-2.0 12 * 13 * Unless required by applicable law or agreed to in writing, software 14 * distributed under the License is distributed on an "AS IS" BASIS, 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 16 * See the License for the specific language governing permissions and 17 * limitations under the License. 18 * 19 ******************************************************************************/ 20 21 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_MAX32520_H_ 22 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_MAX32520_H_ 23 24 #ifndef TARGET_NUM 25 #define TARGET_NUM 32520 26 #endif 27 28 #define MXC_NUMCORES 1 29 30 #include <stdint.h> 31 32 #ifndef FALSE 33 #define FALSE (0) 34 #endif 35 36 #ifndef TRUE 37 #define TRUE (1) 38 #endif 39 40 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ 41 #if defined(__GNUC__) 42 #ifndef __weak 43 #define __weak __attribute__((weak)) 44 #endif 45 46 #elif defined(__CC_ARM) 47 48 #define inline __inline 49 #pragma anon_unions 50 51 #endif 52 53 typedef enum { 54 NonMaskableInt_IRQn = -14, 55 HardFault_IRQn = -13, 56 MemoryManagement_IRQn = -12, 57 BusFault_IRQn = -11, 58 UsageFault_IRQn = -10, 59 SVCall_IRQn = -5, 60 DebugMonitor_IRQn = -4, 61 PendSV_IRQn = -2, 62 SysTick_IRQn = -1, 63 64 /* Device-specific interrupt sources (external to ARM core) */ 65 /* table entry number */ 66 /* |||| */ 67 /* |||| table offset address */ 68 /* vvvv vvvvvv */ 69 70 PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ 71 WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ 72 RSV2_IRQn, /* 0x12 0x0048 18: Reserved */ 73 RSV3_IRQn, /* 0x13 0x004C 19: Reserved */ 74 TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ 75 TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ 76 TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ 77 TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ 78 TMR3_IRQn, /* 0x18 0x0060 24: Timer 3*/ 79 RSV9_IRQn, /* 0x19 0x0064 25: Reserved */ 80 RSV10_IRQn, /* 0x1A 0x0068 26: Reserved */ 81 RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ 82 RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ 83 I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ 84 UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ 85 RSV15_IRQn, /* 0x1F 0x007C 31: Reserved */ 86 SPI0_IRQn, /* 0x20 0x0080 32: SPI0 */ 87 SPI1_IRQn, /* 0x21 0x0084 33: SPI1 */ 88 RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ 89 RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ 90 RSV20_IRQn, /* 0x24 0x0090 36: Reserved */ 91 RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ 92 RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ 93 FLC_IRQn, /* 0x27 0x009C 39: Flash Controller */ 94 GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ 95 GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO2 */ 96 RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ 97 CRYPTO_IRQn, /* 0x2B 0x00AC 43: Crypto */ 98 DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ 99 DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ 100 DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ 101 DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ 102 RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ 103 RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ 104 RSV34_IRQn, /* 0x32 0x00C8 50: Reserved */ 105 RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ 106 RSV36_IRQn, /* 0x34 0x00D0 52: Reserved */ 107 RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */ 108 RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ 109 RSV39_IRQn, /* 0x37 0x00DC 55: Reserved */ 110 RSV40_IRQn, /* 0x38 0x00E0 56: Reserved */ 111 RSV41_IRQn, /* 0x39 0x00E4 57: Reserved */ 112 RSV42_IRQn, /* 0x3A 0x00E8 58: Reserved */ 113 RSV43_IRQn, /* 0x3B 0x00EC 59: Reserved */ 114 RSV44_IRQn, /* 0x3C 0x00F0 60: Reserved */ 115 RSV45_IRQn, /* 0x3D 0x00F4 61: Reserved */ 116 RSV46_IRQn, /* 0x3E 0x00F8 62: Reserved */ 117 RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ 118 RSV48_IRQn, /* 0x40 0x0100 64: Reserved */ 119 RSV49_IRQn, /* 0x41 0x0104 65: Reserved */ 120 RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ 121 RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ 122 RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ 123 RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ 124 GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ 125 RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ 126 RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ 127 WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ 128 RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ 129 RSV59_IRQn, /* 0x4B 0x012C 75: Reserved */ 130 RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ 131 RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ 132 RSV62_IRQn, /* 0x4E 0x0138 78: Reserved */ 133 RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ 134 RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ 135 RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ 136 RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ 137 RSV67_IRQn, /* 0x53 0x014C 83: Reserved */ 138 RSV68_IRQn, /* 0x54 0x0150 84: Reserved */ 139 RSV69_IRQn, /* 0x55 0x0154 85: Reserved */ 140 RSV70_IRQn, /* 0x56 0x0158 86: Reserved */ 141 RSV71_IRQn, /* 0x57 0x015C 87: Reserved */ 142 RSV72_IRQn, /* 0x58 0x0160 88: Reserved */ 143 RSV73_IRQn, /* 0x59 0x0164 89: Reserved */ 144 RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */ 145 RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */ 146 RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ 147 RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ 148 RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ 149 RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ 150 RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ 151 RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ 152 ECC_IRQn, /* 0x62 0x0188 98: Error Correction */ 153 RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ 154 RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ 155 SCA_IRQn, /* 0x65 0x0194 101: SCA Crypto */ 156 RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ 157 RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ 158 RSV88_IRQn, /* 0x68 0x01A0 104: Reserved */ 159 RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ 160 RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ 161 RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ 162 RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ 163 RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ 164 RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ 165 RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ 166 SFE_IRQn, /* 0x70 0x01C0 112: SFE */ 167 MXC_IRQ_EXT_COUNT, 168 } IRQn_Type; 169 170 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) 171 172 /* ================================================================================ */ 173 /* ================ Processor and Core Peripheral Section ================ */ 174 /* ================================================================================ */ 175 176 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ 177 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ 178 #define __MPU_PRESENT 1 /*!< MPU present or not */ 179 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 180 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 181 #define __FPU_PRESENT 1 /*!< FPU present or not */ 182 183 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */ 184 #include "system_max32520.h" /*!< System Header */ 185 186 /* ================================================================================ */ 187 /* ================== Device Specific Memory Section ================== */ 188 /* ================================================================================ */ 189 190 #define MXC_ROM_MEM_BASE 0x00000000UL 191 #define MXC_ROM_MEM_SIZE 0x00020000UL 192 #define MXC_FLASH0_MEM_BASE 0x10000000UL 193 #define MXC_FLASH1_MEM_BASE 0x10100000UL 194 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE 195 #define MXC_FLASH_PAGE_SIZE 0x00004000UL 196 #define MXC_FLASH_MEM_SIZE 0x00200000UL 197 #define MXC_INFO0_MEM_BASE 0x10800000UL 198 #define MXC_INFO1_MEM_BASE 0x10806000UL 199 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE 200 #define MXC_INFO_MEM_SIZE 0x00008000UL 201 #define MXC_SRAM_MEM_BASE 0x20000000UL 202 #define MXC_SRAM_MEM_SIZE 0x0002A800UL 203 204 /* ================================================================================ */ 205 /* ================ Device Specific Peripheral Section ================ */ 206 /* ================================================================================ */ 207 208 /* 209 Base addresses and configuration settings for all MAX32520 peripheral modules. 210 */ 211 212 /******************************************************************************/ 213 /* Global control */ 214 #define MXC_BASE_GCR ((uint32_t)0x40000000UL) 215 #define MXC_GCR ((mxc_gcr_regs_t *)MXC_BASE_GCR) 216 217 /******************************************************************************/ 218 /* Non-battery backed SI Registers */ 219 #define MXC_BASE_SIR ((uint32_t)0x40000400UL) 220 #define MXC_SIR ((mxc_sir_regs_t *)MXC_BASE_SIR) 221 222 /******************************************************************************/ 223 /* Function Control */ 224 #define MXC_BASE_FCR ((uint32_t)0x40000800UL) 225 #define MXC_FCR ((mxc_nbbfc_regs_t *)MXC_BASE_FCR) 226 227 /******************************************************************************/ 228 /* Trust Protection Unit */ 229 #define MXC_BASE_CTB ((uint32_t)0x40001000UL) 230 #define MXC_CTB ((mxc_ctb_regs_t *)MXC_BASE_CTB) 231 232 /******************************************************************************/ 233 /* Watchdog */ 234 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) 235 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) 236 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL) 237 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) 238 239 /******************************************************************************/ 240 /* Security Monitor */ 241 #define MXC_BASE_SMON ((uint32_t)0x40004000UL) 242 #define MXC_SMON ((mxc_smon_regs_t *)MXC_BASE_SMON) 243 244 /******************************************************************************/ 245 /* AES Keys */ 246 #define MXC_BASE_AESKEYS ((uint32_t)0x40005000UL) 247 #define MXC_AESKEYS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS) 248 249 /******************************************************************************/ 250 /* Power Sequencer */ 251 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) 252 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) 253 254 /******************************************************************************/ 255 /* MISC Control Regs */ 256 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL) 257 #define MXC_MCR ((mxc_mcr_regs_t *)MXC_BASE_MCR) 258 259 /******************************************************************************/ 260 /* GPIO */ 261 #define MXC_CFG_GPIO_INSTANCES (2) 262 #define MXC_CFG_GPIO_PINS_PORT (16) 263 264 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) 265 #define MXC_GPIO0 ((mxc_gpio_regs_t *)MXC_BASE_GPIO0) 266 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL) 267 #define MXC_GPIO1 ((mxc_gpio_regs_t *)MXC_BASE_GPIO1) 268 269 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : (p) == MXC_GPIO1 ? 1 : -1) 270 271 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0) 272 273 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0) 274 275 /******************************************************************************/ 276 #define SEC(s) (((uint32_t)s) * 1000000UL) 277 #define MSEC(ms) (ms * 1000UL) 278 #define USEC(us) (us) 279 /* Timer */ 280 #define MXC_CFG_TMR_INSTANCES (4) 281 282 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) 283 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) 284 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) 285 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) 286 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) 287 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) 288 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL) 289 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) 290 291 #define MXC_TMR_GET_IRQ(i) \ 292 (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ 293 (i) == 1 ? TMR1_IRQn : \ 294 (i) == 2 ? TMR2_IRQn : \ 295 (i) == 3 ? TMR3_IRQn : \ 296 0) 297 298 #define MXC_TMR_GET_BASE(i) \ 299 ((i) == 0 ? MXC_BASE_TMR0 : \ 300 (i) == 1 ? MXC_BASE_TMR1 : \ 301 (i) == 2 ? MXC_BASE_TMR2 : \ 302 (i) == 3 ? MXC_BASE_TMR3 : \ 303 0) 304 305 #define MXC_TMR_GET_TMR(i) \ 306 ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : (i) == 3 ? MXC_TMR3 : 0) 307 308 #define MXC_TMR_GET_IDX(p) \ 309 ((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : (p) == MXC_TMR3 ? 3 : -1) 310 311 /******************************************************************************/ 312 /* I2C */ 313 #define MXC_I2C_INSTANCES (1) 314 315 #define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) 316 #define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0) 317 318 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : 0) 319 320 #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : 0) 321 322 #define MXC_I2C_GET_TMR(i) ((i) == 0 ? MXC_I2C0 : 0) 323 324 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : -1) 325 #define MXC_I2C_FIFO_DEPTH (8) 326 327 #define MXC_I2C_GET_I2C(p) ((p) == 0x0 ? MXC_I2C0 : 0) 328 329 /******************************************************************************/ 330 /* UART / Serial Port Interface */ 331 #define MXC_UART_INSTANCES (1) 332 #define MXC_UART_FIFO_DEPTH (8) 333 334 #define MXC_BASE_UART0 ((uint32_t)0x40020000UL) 335 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) 336 337 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) 338 339 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : 0) 340 341 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : 0) 342 343 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : -1) 344 345 /******************************************************************************/ 346 /* DMA */ 347 #define MXC_DMA_CHANNELS (4) 348 #define MXC_DMA_INSTANCES (1) 349 350 #define MXC_BASE_DMA ((uint32_t)0x40028000UL) 351 #define MXC_DMA ((mxc_dma_regs_t *)MXC_BASE_DMA) 352 353 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) 354 355 #define MXC_DMA_CH_GET_IRQ(i) \ 356 ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ 357 ((i) == 1) ? DMA1_IRQn : \ 358 ((i) == 2) ? DMA2_IRQn : \ 359 ((i) == 3) ? DMA3_IRQn : \ 360 0)) 361 362 /******************************************************************************/ 363 /* FLC */ 364 #define MXC_FLC_INSTANCES (1) 365 366 #define MXC_BASE_FLC ((uint32_t)0x40029000UL) 367 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) 368 369 #define MXC_FLC0 MXC_FLC 370 #define FLC0_IRQn FLC_IRQn 371 372 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC_IRQn : 0) 373 374 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC : 0) 375 376 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) 377 378 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC ? 0 : -1) 379 380 /******************************************************************************/ 381 /* Instruction Cache */ 382 #define MXC_BASE_ICC ((uint32_t)0x4002A000UL) 383 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) 384 385 /******************************************************************************/ 386 /* SPI */ 387 #define MXC_SPI_INSTANCES (2) 388 #define MXC_SPI_SS_INSTANCES (4) 389 #define MXC_SPI_FIFO_DEPTH (32) 390 391 #define MXC_BASE_SPI0 ((uint32_t)0x40046000UL) 392 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) 393 #define MXC_BASE_SPI1 ((uint32_t)0x40047000UL) 394 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) 395 396 #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : (p) == MXC_SPI1 ? 1 : -1) 397 398 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : (i) == 1 ? MXC_BASE_SPI1 : 0) 399 400 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : (i) == 1 ? MXC_SPI1 : 0) 401 402 #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI0_IRQn : (i) == 1 ? SPI1_IRQn : 0) 403 404 /******************************************************************************/ 405 /* TRNG */ 406 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL) 407 #define MXC_TRNG ((mxc_trng_regs_t *)MXC_BASE_TRNG) 408 409 /******************************************************************************/ 410 /* SFE */ 411 #define MXC_BASE_SFE ((uint32_t)0x400A0000UL) 412 #define MXC_SFE ((mxc_sfe_regs_t *)MXC_BASE_SFE) 413 414 /******************************************************************************/ 415 /* CSPIS */ 416 #define MXC_BASE_CSPIS ((uint32_t)0x400A0000UL) 417 #define MXC_CSPIS ((mxc_cspis_regs_t *)MXC_BASE_CSPIS) 418 419 #define CSPIS_IRQn SFE_IRQn 420 421 /******************************************************************************/ 422 /* Bit Shifting */ 423 #define MXC_F_BIT_0 (1 << 0) 424 #define MXC_F_BIT_1 (1 << 1) 425 #define MXC_F_BIT_2 (1 << 2) 426 #define MXC_F_BIT_3 (1 << 3) 427 #define MXC_F_BIT_4 (1 << 4) 428 #define MXC_F_BIT_5 (1 << 5) 429 #define MXC_F_BIT_6 (1 << 6) 430 #define MXC_F_BIT_7 (1 << 7) 431 #define MXC_F_BIT_8 (1 << 8) 432 #define MXC_F_BIT_9 (1 << 9) 433 #define MXC_F_BIT_10 (1 << 10) 434 #define MXC_F_BIT_11 (1 << 11) 435 #define MXC_F_BIT_12 (1 << 12) 436 #define MXC_F_BIT_13 (1 << 13) 437 #define MXC_F_BIT_14 (1 << 14) 438 #define MXC_F_BIT_15 (1 << 15) 439 #define MXC_F_BIT_16 (1 << 16) 440 #define MXC_F_BIT_17 (1 << 17) 441 #define MXC_F_BIT_18 (1 << 18) 442 #define MXC_F_BIT_19 (1 << 19) 443 #define MXC_F_BIT_20 (1 << 20) 444 #define MXC_F_BIT_21 (1 << 21) 445 #define MXC_F_BIT_22 (1 << 22) 446 #define MXC_F_BIT_23 (1 << 23) 447 #define MXC_F_BIT_24 (1 << 24) 448 #define MXC_F_BIT_25 (1 << 25) 449 #define MXC_F_BIT_26 (1 << 26) 450 #define MXC_F_BIT_27 (1 << 27) 451 #define MXC_F_BIT_28 (1 << 28) 452 #define MXC_F_BIT_29 (1 << 29) 453 #define MXC_F_BIT_30 (1 << 30) 454 #define MXC_F_BIT_31 (1 << 31) 455 456 /******************************************************************************/ 457 /* Bit Banding */ 458 #define BITBAND(reg, bit) \ 459 ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ 460 ((bit) << 2)) 461 462 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) 463 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) 464 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) 465 466 #define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) 467 468 /******************************************************************************/ 469 /* SCB CPACR */ 470 471 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ 472 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ 473 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ 474 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ 475 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ 476 477 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_MAX32520_H_ 478
