1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 85 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 86 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 87 __R uint32_t rsv_0x30_0x3f[4]; 88 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 89 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 90 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 91 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 92 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 93 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 94 __R uint32_t rsv_0x58_0x63[3]; 95 __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */ 96 __IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */ 97 __IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */ 98 __IO uint32_t eccaddr; /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */ 99 } mxc_gcr_regs_t; 100 101 /* Register offsets for module GCR */ 102 /** 103 * @ingroup gcr_registers 104 * @defgroup GCR_Register_Offsets Register Offsets 105 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 106 * @{ 107 */ 108 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 109 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 110 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 111 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 112 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 113 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 114 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 115 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 116 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 117 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 118 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 119 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 120 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 121 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 122 #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 123 #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 124 #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 125 #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 126 /**@} end of group gcr_registers */ 127 128 /** 129 * @ingroup gcr_registers 130 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 131 * @brief System Control. 132 * @{ 133 */ 134 #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 0 /**< SYSCTRL_BSTAPEN Position */ 135 #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ 136 137 #define MXC_F_GCR_SYSCTRL_FLASH0_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH0_PAGE_FLIP Position */ 138 #define MXC_F_GCR_SYSCTRL_FLASH0_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH0_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH0_PAGE_FLIP Mask */ 139 140 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ 141 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ 142 143 #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ 144 #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ 145 146 #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ 147 #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ 148 149 #define MXC_F_GCR_SYSCTRL_MDU_KEYSZ_POS 21 /**< SYSCTRL_MDU_KEYSZ Position */ 150 #define MXC_F_GCR_SYSCTRL_MDU_KEYSZ ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_MDU_KEYSZ_POS)) /**< SYSCTRL_MDU_KEYSZ Mask */ 151 152 /**@} end of group GCR_SYSCTRL_Register */ 153 154 /** 155 * @ingroup gcr_registers 156 * @defgroup GCR_RST0 GCR_RST0 157 * @brief Reset. 158 * @{ 159 */ 160 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 161 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 162 163 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 164 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 165 166 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 167 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 168 169 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 170 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 171 172 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 173 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 174 175 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 176 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 177 178 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 179 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 180 181 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 182 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 183 184 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 185 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 186 187 #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ 188 #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ 189 190 #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ 191 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 192 193 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 194 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 195 196 #define MXC_F_GCR_RST0_CRYPTO_POS 18 /**< RST0_CRYPTO Position */ 197 #define MXC_F_GCR_RST0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CRYPTO_POS)) /**< RST0_CRYPTO Mask */ 198 199 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 200 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 201 202 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 203 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 204 205 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 206 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 207 208 /**@} end of group GCR_RST0_Register */ 209 210 /** 211 * @ingroup gcr_registers 212 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 213 * @brief Clock Control. 214 * @{ 215 */ 216 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 217 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 218 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 219 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 220 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 221 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 222 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 223 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 224 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 225 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 226 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 227 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 228 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 229 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 230 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 231 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 232 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 233 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 234 235 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 236 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 237 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 238 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 239 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 240 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 241 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 242 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 243 244 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 245 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 246 247 #define MXC_F_GCR_CLKCTRL_CCD_POS 15 /**< CLKCTRL_CCD Position */ 248 #define MXC_F_GCR_CLKCTRL_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_CCD_POS)) /**< CLKCTRL_CCD Mask */ 249 250 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 18 /**< CLKCTRL_IPO_EN Position */ 251 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 252 253 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 254 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 255 256 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 257 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 258 259 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 26 /**< CLKCTRL_IPO_RDY Position */ 260 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 261 262 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 263 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 264 265 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 266 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 267 268 /**@} end of group GCR_CLKCTRL_Register */ 269 270 /** 271 * @ingroup gcr_registers 272 * @defgroup GCR_PM GCR_PM 273 * @brief Power Management. 274 * @{ 275 */ 276 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 277 #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 278 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 279 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 280 #define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ 281 #define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ 282 #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ 283 #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ 284 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 285 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 286 287 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 288 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 289 290 #define MXC_F_GCR_PM_IPO_PD_POS 15 /**< PM_IPO_PD Position */ 291 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 292 293 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 294 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 295 296 /**@} end of group GCR_PM_Register */ 297 298 /** 299 * @ingroup gcr_registers 300 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 301 * @brief Peripheral Clock Divider. 302 * @{ 303 */ 304 #define MXC_F_GCR_PCLKDIV_PCF_POS 0 /**< PCLKDIV_PCF Position */ 305 #define MXC_F_GCR_PCLKDIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_PCF_POS)) /**< PCLKDIV_PCF Mask */ 306 #define MXC_V_GCR_PCLKDIV_PCF_96MHZ ((uint32_t)0x2UL) /**< PCLKDIV_PCF_96MHZ Value */ 307 #define MXC_S_GCR_PCLKDIV_PCF_96MHZ (MXC_V_GCR_PCLKDIV_PCF_96MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_96MHZ Setting */ 308 #define MXC_V_GCR_PCLKDIV_PCF_48MHZ ((uint32_t)0x3UL) /**< PCLKDIV_PCF_48MHZ Value */ 309 #define MXC_S_GCR_PCLKDIV_PCF_48MHZ (MXC_V_GCR_PCLKDIV_PCF_48MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_48MHZ Setting */ 310 #define MXC_V_GCR_PCLKDIV_PCF_24MHZ ((uint32_t)0x4UL) /**< PCLKDIV_PCF_24MHZ Value */ 311 #define MXC_S_GCR_PCLKDIV_PCF_24MHZ (MXC_V_GCR_PCLKDIV_PCF_24MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_24MHZ Setting */ 312 #define MXC_V_GCR_PCLKDIV_PCF_12MHZ ((uint32_t)0x5UL) /**< PCLKDIV_PCF_12MHZ Value */ 313 #define MXC_S_GCR_PCLKDIV_PCF_12MHZ (MXC_V_GCR_PCLKDIV_PCF_12MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_12MHZ Setting */ 314 #define MXC_V_GCR_PCLKDIV_PCF_6MHZ ((uint32_t)0x6UL) /**< PCLKDIV_PCF_6MHZ Value */ 315 #define MXC_S_GCR_PCLKDIV_PCF_6MHZ (MXC_V_GCR_PCLKDIV_PCF_6MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_6MHZ Setting */ 316 #define MXC_V_GCR_PCLKDIV_PCF_3MHZ ((uint32_t)0x7UL) /**< PCLKDIV_PCF_3MHZ Value */ 317 #define MXC_S_GCR_PCLKDIV_PCF_3MHZ (MXC_V_GCR_PCLKDIV_PCF_3MHZ << MXC_F_GCR_PCLKDIV_PCF_POS) /**< PCLKDIV_PCF_3MHZ Setting */ 318 319 #define MXC_F_GCR_PCLKDIV_PCFWEN_POS 3 /**< PCLKDIV_PCFWEN Position */ 320 #define MXC_F_GCR_PCLKDIV_PCFWEN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_PCFWEN_POS)) /**< PCLKDIV_PCFWEN Mask */ 321 322 #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 14 /**< PCLKDIV_AON_CLKDIV Position */ 323 #define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ 324 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV_4 Value */ 325 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_4 Setting */ 326 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV_8 Value */ 327 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_8 Setting */ 328 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV_16 Value */ 329 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_16 Setting */ 330 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV_32 Value */ 331 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV_32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV_32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV_32 Setting */ 332 333 /**@} end of group GCR_PCLKDIV_Register */ 334 335 /** 336 * @ingroup gcr_registers 337 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 338 * @brief Peripheral Clock Disable. 339 * @{ 340 */ 341 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 342 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 343 344 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 345 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 346 347 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 348 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 349 350 #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ 351 #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ 352 353 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ 354 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 355 356 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 357 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 358 359 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 360 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 361 362 #define MXC_F_GCR_PCLKDIS0_CRYPTO_POS 14 /**< PCLKDIS0_CRYPTO Position */ 363 #define MXC_F_GCR_PCLKDIS0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CRYPTO_POS)) /**< PCLKDIS0_CRYPTO Mask */ 364 365 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 366 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 367 368 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 369 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 370 371 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 372 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 373 374 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 375 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 376 377 /**@} end of group GCR_PCLKDIS0_Register */ 378 379 /** 380 * @ingroup gcr_registers 381 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 382 * @brief Memory Clock Control Register. 383 * @{ 384 */ 385 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 386 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 387 388 #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ 389 #define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ 390 391 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 16 /**< MEMCTRL_RAM0LS_EN Position */ 392 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ 393 394 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 17 /**< MEMCTRL_RAM1LS_EN Position */ 395 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ 396 397 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 18 /**< MEMCTRL_RAM2LS_EN Position */ 398 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ 399 400 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 19 /**< MEMCTRL_RAM3LS_EN Position */ 401 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ 402 403 #define MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS 20 /**< MEMCTRL_RAM4LS_EN Position */ 404 #define MXC_F_GCR_MEMCTRL_RAM4LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS)) /**< MEMCTRL_RAM4LS_EN Mask */ 405 406 #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 24 /**< MEMCTRL_ICC0LS_EN Position */ 407 #define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ 408 409 #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 29 /**< MEMCTRL_ROMLS_EN Position */ 410 #define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ 411 412 /**@} end of group GCR_MEMCTRL_Register */ 413 414 /** 415 * @ingroup gcr_registers 416 * @defgroup GCR_MEMZ GCR_MEMZ 417 * @brief Memory Zeroize Control. 418 * @{ 419 */ 420 #define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ 421 #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ 422 423 #define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ 424 #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ 425 426 #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ 427 #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ 428 429 #define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ 430 #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ 431 432 #define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ 433 #define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ 434 435 #define MXC_F_GCR_MEMZ_ICC0_POS 8 /**< MEMZ_ICC0 Position */ 436 #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ 437 438 /**@} end of group GCR_MEMZ_Register */ 439 440 /** 441 * @ingroup gcr_registers 442 * @defgroup GCR_SYSST GCR_SYSST 443 * @brief System Status Register. 444 * @{ 445 */ 446 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 447 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 448 449 /**@} end of group GCR_SYSST_Register */ 450 451 /** 452 * @ingroup gcr_registers 453 * @defgroup GCR_RST1 GCR_RST1 454 * @brief Reset 1. 455 * @{ 456 */ 457 #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ 458 #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ 459 460 #define MXC_F_GCR_RST1_SFES_POS 28 /**< RST1_SFES Position */ 461 #define MXC_F_GCR_RST1_SFES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SFES_POS)) /**< RST1_SFES Mask */ 462 463 /**@} end of group GCR_RST1_Register */ 464 465 /** 466 * @ingroup gcr_registers 467 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 468 * @brief Peripheral Clock Disable. 469 * @{ 470 */ 471 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 472 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 473 474 #define MXC_F_GCR_PCLKDIS1_WDT0_POS 27 /**< PCLKDIS1_WDT0 Position */ 475 #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ 476 477 #define MXC_F_GCR_PCLKDIS1_WDT1_POS 28 /**< PCLKDIS1_WDT1 Position */ 478 #define MXC_F_GCR_PCLKDIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT1_POS)) /**< PCLKDIS1_WDT1 Mask */ 479 480 #define MXC_F_GCR_PCLKDIS1_SFES_POS 30 /**< PCLKDIS1_SFES Position */ 481 #define MXC_F_GCR_PCLKDIS1_SFES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SFES_POS)) /**< PCLKDIS1_SFES Mask */ 482 483 /**@} end of group GCR_PCLKDIS1_Register */ 484 485 /** 486 * @ingroup gcr_registers 487 * @defgroup GCR_EVENTEN GCR_EVENTEN 488 * @brief Event Enable Register. 489 * @{ 490 */ 491 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 492 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 493 494 #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ 495 #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ 496 497 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 498 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 499 500 /**@} end of group GCR_EVENTEN_Register */ 501 502 /** 503 * @ingroup gcr_registers 504 * @defgroup GCR_REVISION GCR_REVISION 505 * @brief Revision Register. 506 * @{ 507 */ 508 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 509 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 510 511 /**@} end of group GCR_REVISION_Register */ 512 513 /** 514 * @ingroup gcr_registers 515 * @defgroup GCR_SYSIE GCR_SYSIE 516 * @brief System Status Interrupt Enable Register. 517 * @{ 518 */ 519 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 520 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 521 522 /**@} end of group GCR_SYSIE_Register */ 523 524 /** 525 * @ingroup gcr_registers 526 * @defgroup GCR_ECCERR GCR_ECCERR 527 * @brief ECC Error Register 528 * @{ 529 */ 530 #define MXC_F_GCR_ECCERR_RAM0_POS 0 /**< ECCERR_RAM0 Position */ 531 #define MXC_F_GCR_ECCERR_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM0_POS)) /**< ECCERR_RAM0 Mask */ 532 533 #define MXC_F_GCR_ECCERR_RAM1_POS 1 /**< ECCERR_RAM1 Position */ 534 #define MXC_F_GCR_ECCERR_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM1_POS)) /**< ECCERR_RAM1 Mask */ 535 536 #define MXC_F_GCR_ECCERR_RAM2_POS 2 /**< ECCERR_RAM2 Position */ 537 #define MXC_F_GCR_ECCERR_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM2_POS)) /**< ECCERR_RAM2 Mask */ 538 539 #define MXC_F_GCR_ECCERR_RAM3_POS 3 /**< ECCERR_RAM3 Position */ 540 #define MXC_F_GCR_ECCERR_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM3_POS)) /**< ECCERR_RAM3 Mask */ 541 542 #define MXC_F_GCR_ECCERR_RAM4_POS 4 /**< ECCERR_RAM4 Position */ 543 #define MXC_F_GCR_ECCERR_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM4_POS)) /**< ECCERR_RAM4 Mask */ 544 545 /**@} end of group GCR_ECCERR_Register */ 546 547 /** 548 * @ingroup gcr_registers 549 * @defgroup GCR_ECCCED GCR_ECCCED 550 * @brief ECC Not Double Error Detect Register 551 * @{ 552 */ 553 #define MXC_F_GCR_ECCCED_RAM0_POS 0 /**< ECCCED_RAM0 Position */ 554 #define MXC_F_GCR_ECCCED_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM0_POS)) /**< ECCCED_RAM0 Mask */ 555 556 #define MXC_F_GCR_ECCCED_RAM1_POS 1 /**< ECCCED_RAM1 Position */ 557 #define MXC_F_GCR_ECCCED_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM1_POS)) /**< ECCCED_RAM1 Mask */ 558 559 #define MXC_F_GCR_ECCCED_RAM2_POS 2 /**< ECCCED_RAM2 Position */ 560 #define MXC_F_GCR_ECCCED_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM2_POS)) /**< ECCCED_RAM2 Mask */ 561 562 #define MXC_F_GCR_ECCCED_RAM3_POS 3 /**< ECCCED_RAM3 Position */ 563 #define MXC_F_GCR_ECCCED_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM3_POS)) /**< ECCCED_RAM3 Mask */ 564 565 #define MXC_F_GCR_ECCCED_RAM4_POS 4 /**< ECCCED_RAM4 Position */ 566 #define MXC_F_GCR_ECCCED_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM4_POS)) /**< ECCCED_RAM4 Mask */ 567 568 /**@} end of group GCR_ECCCED_Register */ 569 570 /** 571 * @ingroup gcr_registers 572 * @defgroup GCR_ECCIE GCR_ECCIE 573 * @brief ECC IRQ Enable Register 574 * @{ 575 */ 576 #define MXC_F_GCR_ECCIE_RAM0_POS 0 /**< ECCIE_RAM0 Position */ 577 #define MXC_F_GCR_ECCIE_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM0_POS)) /**< ECCIE_RAM0 Mask */ 578 579 #define MXC_F_GCR_ECCIE_RAM1_POS 1 /**< ECCIE_RAM1 Position */ 580 #define MXC_F_GCR_ECCIE_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM1_POS)) /**< ECCIE_RAM1 Mask */ 581 582 #define MXC_F_GCR_ECCIE_RAM2_POS 2 /**< ECCIE_RAM2 Position */ 583 #define MXC_F_GCR_ECCIE_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM2_POS)) /**< ECCIE_RAM2 Mask */ 584 585 #define MXC_F_GCR_ECCIE_RAM3_POS 3 /**< ECCIE_RAM3 Position */ 586 #define MXC_F_GCR_ECCIE_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM3_POS)) /**< ECCIE_RAM3 Mask */ 587 588 #define MXC_F_GCR_ECCIE_RAM4_POS 4 /**< ECCIE_RAM4 Position */ 589 #define MXC_F_GCR_ECCIE_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM4_POS)) /**< ECCIE_RAM4 Mask */ 590 591 /**@} end of group GCR_ECCIE_Register */ 592 593 /** 594 * @ingroup gcr_registers 595 * @defgroup GCR_ECCADDR GCR_ECCADDR 596 * @brief ECC Error Address Register 597 * @{ 598 */ 599 #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ 600 #define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ 601 602 #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ 603 #define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ 604 605 #define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ 606 #define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ 607 608 #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ 609 #define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ 610 611 #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ 612 #define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ 613 614 #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ 615 #define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ 616 617 /**@} end of group GCR_ECCADDR_Register */ 618 619 #ifdef __cplusplus 620 } 621 #endif 622 623 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_GCR_REGS_H_ 624
