1 /******************************************************************************
2 *
3 * Copyright (C) 2023-2025 Analog Devices, Inc.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18
19 #ifndef LIBRARIES_ZEPHYR_MAX_INCLUDE_WRAP_MAX32_TMR_H_
20 #define LIBRARIES_ZEPHYR_MAX_INCLUDE_WRAP_MAX32_TMR_H_
21
22 /***** Includes *****/
23 #include <tmr.h>
24 #include <lp.h>
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 typedef struct {
31 mxc_tmr_pres_t pres;
32 mxc_tmr_mode_t mode;
33 int bitMode; /* Some PN does not support it, check mxc_tmr_bit_mode_t in tmr.h file */
34 int clock; /* Some PN does not support it, check mxc_tmr_clock_t in tmr.h file */
35 uint32_t cmp_cnt; /**< Compare register value in timer ticks */
36 unsigned pol; /**< Polarity (0 or 1) */
37 } wrap_mxc_tmr_cfg_t;
38
39 /*
40 * MAX32665, MAX32666 related mapping
41 */
42 #if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
43
44 /* All timers are 32bits */
45 #define WRAP_MXC_IS_32B_TIMER(idx) (1)
46
Wrap_MXC_TMR_Init(mxc_tmr_regs_t * tmr,wrap_mxc_tmr_cfg_t * cfg)47 static inline int Wrap_MXC_TMR_Init(mxc_tmr_regs_t *tmr, wrap_mxc_tmr_cfg_t *cfg)
48 {
49 mxc_tmr_cfg_t mxc_cfg;
50
51 mxc_cfg.pres = cfg->pres;
52 mxc_cfg.mode = cfg->mode;
53 mxc_cfg.cmp_cnt = cfg->cmp_cnt;
54 mxc_cfg.pol = cfg->pol;
55
56 MXC_TMR_Init(tmr, &mxc_cfg);
57 return 0;
58 }
59
Wrap_MXC_TMR_GetClockIndex(int z_clock)60 static inline int Wrap_MXC_TMR_GetClockIndex(int z_clock)
61 {
62 if (z_clock == 0) {
63 /* Only peripheral clock is supported, just retunr 0 */
64 return 0;
65 } else {
66 return -1; /* Not supported */
67 }
68 }
69
Wrap_MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,wrap_mxc_tmr_cfg_t * cfg)70 void Wrap_MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, wrap_mxc_tmr_cfg_t *cfg)
71 {
72 (void)tmr;
73 (void)cfg;
74 }
75
Wrap_MXC_TMR_ClearWakeupFlags(mxc_tmr_regs_t * tmr)76 void Wrap_MXC_TMR_ClearWakeupFlags(mxc_tmr_regs_t *tmr)
77 {
78 (void)tmr;
79 }
80
Wrap_MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)81 void Wrap_MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
82 {
83 (void)tmr;
84 }
85
Wrap_MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)86 void Wrap_MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
87 {
88 (void)tmr;
89 }
90
Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t * tmr)91 int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr)
92 {
93 uint32_t mask = MXC_F_TMR_INTR_IRQ;
94 uint32_t flags;
95
96 flags = MXC_TMR_GetFlags(tmr);
97
98 return ((flags & mask) == mask);
99 }
100
101 /*
102 * MAX32690, MAX32655 related mapping
103 */
104 #elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
105 defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
106 defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
107 defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX78002) || \
108 defined(CONFIG_SOC_MAX78000)
109
110 #if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675)
111 /* All timers are 32bits */
112 #define WRAP_MXC_IS_32B_TIMER(idx) (1)
113 #elif defined(CONFIG_SOC_MAX32662)
114 #define WRAP_MXC_IS_32B_TIMER(idx) (MXC_TMR_GET_IDX(idx) == 3 ? 0 : 1)
115 #else
116 #define WRAP_MXC_IS_32B_TIMER(idx) \
117 (MXC_TMR_GET_IDX(idx) == 4 ? 0 : MXC_TMR_GET_IDX(idx) == 5 ? 0 : 1)
118 #endif
119
Wrap_MXC_TMR_Init(mxc_tmr_regs_t * tmr,wrap_mxc_tmr_cfg_t * cfg)120 static inline int Wrap_MXC_TMR_Init(mxc_tmr_regs_t *tmr, wrap_mxc_tmr_cfg_t *cfg)
121 {
122 mxc_tmr_cfg_t mxc_cfg;
123
124 mxc_cfg.pres = cfg->pres;
125 mxc_cfg.mode = cfg->mode;
126 mxc_cfg.cmp_cnt = cfg->cmp_cnt;
127 mxc_cfg.pol = cfg->pol;
128 mxc_cfg.bitMode = (mxc_tmr_bit_mode_t)cfg->bitMode;
129 mxc_cfg.clock = (mxc_tmr_clock_t)cfg->clock;
130
131 #if defined(CONFIG_SOC_MAX32662)
132 return MXC_TMR_Init(tmr, &mxc_cfg, 0, (sys_map_t)0);
133 #else
134 return MXC_TMR_Init(tmr, &mxc_cfg, 0); // init_pins not used
135 #endif
136 }
137
Wrap_MXC_TMR_GetClockIndex(int z_clock)138 static inline int Wrap_MXC_TMR_GetClockIndex(int z_clock)
139 {
140 switch (z_clock) {
141 case 0: // ADI_MAX32_PRPH_CLK_SRC_PCLK
142 return MXC_TMR_APB_CLK;
143 case 1: // ADI_MAX32_PRPH_CLK_SRC_EXTCLK
144 return MXC_TMR_EXT_CLK;
145 case 2: // ADI_MAX32_PRPH_CLK_SRC_IBRO
146 return MXC_TMR_8M_CLK;
147 #if !defined(CONFIG_SOC_MAX78002) && !defined(CONFIG_SOC_MAX78000)
148 case 3: //ADI_MAX32_PRPH_CLK_SRC_ERFO
149 return MXC_TMR_32M_CLK;
150 #endif
151 case 4: //ADI_MAX32_PRPH_CLK_SRC_ERTCO
152 return MXC_TMR_32K_CLK;
153 case 5: //ADI_MAX32_PRPH_CLK_SRC_INRO
154 return MXC_TMR_INRO_CLK;
155 #if defined(CONFIG_SOC_MAX32655) || defined(CONFIG_SOC_MAX32680) || \
156 defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX78002) || defined(CONFIG_SOC_MAX78000)
157 case 6: //ADI_MAX32_PRPH_CLK_SRC_ISO
158 return MXC_TMR_ISO_CLK;
159 #endif
160 }
161
162 return -1; /* Not supported */
163 }
164
Wrap_MXC_TMR_EnableWakeup(mxc_tmr_regs_t * tmr,wrap_mxc_tmr_cfg_t * cfg)165 void Wrap_MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, wrap_mxc_tmr_cfg_t *cfg)
166 {
167 mxc_tmr_cfg_t mxc_cfg;
168
169 mxc_cfg.pres = cfg->pres;
170 mxc_cfg.mode = cfg->mode;
171 mxc_cfg.cmp_cnt = cfg->cmp_cnt;
172 mxc_cfg.pol = cfg->pol;
173 mxc_cfg.bitMode = (mxc_tmr_bit_mode_t)cfg->bitMode;
174 mxc_cfg.clock = (mxc_tmr_clock_t)cfg->clock;
175
176 // Enable wakeup source in power seq register
177 MXC_LP_EnableTimerWakeup(tmr);
178 // Enable Timer wake-up source
179 MXC_TMR_EnableWakeup(tmr, &mxc_cfg);
180 }
181
Wrap_MXC_TMR_ClearWakeupFlags(mxc_tmr_regs_t * tmr)182 void Wrap_MXC_TMR_ClearWakeupFlags(mxc_tmr_regs_t *tmr)
183 {
184 if (tmr->wkfl & MXC_F_TMR_WKFL_A) {
185 // Write 1 to clear
186 tmr->wkfl |= MXC_F_TMR_WKFL_A;
187 }
188 }
189
Wrap_MXC_TMR_DisableInt(mxc_tmr_regs_t * tmr)190 void Wrap_MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr)
191 {
192 MXC_TMR_DisableInt(tmr);
193 }
194
Wrap_MXC_TMR_EnableInt(mxc_tmr_regs_t * tmr)195 void Wrap_MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr)
196 {
197 MXC_TMR_EnableInt(tmr);
198 }
199
Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t * tmr)200 int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr)
201 {
202 uint32_t mask = MXC_F_TMR_INTFL_IRQ_A | MXC_F_TMR_INTFL_IRQ_B;
203 uint32_t flags;
204
205 flags = MXC_TMR_GetFlags(tmr);
206
207 return ((flags & mask) == mask);
208 }
209
210 #endif // part number
211
212 #ifdef __cplusplus
213 }
214 #endif
215
216 #endif // LIBRARIES_ZEPHYR_MAX_INCLUDE_WRAP_MAX32_TMR_H_
217
