1 /******************************************************************************
2 *
3 * Copyright (C) 2023-2025 Analog Devices, Inc.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 ******************************************************************************/
18
19 #ifndef LIBRARIES_ZEPHYR_MAX_INCLUDE_WRAP_MAX32_I2C_H_
20 #define LIBRARIES_ZEPHYR_MAX_INCLUDE_WRAP_MAX32_I2C_H_
21
22 /***** Includes *****/
23 #include <i2c.h>
24
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28
29 /*
30 * MAX32665, MAX32666 related mapping
31 */
32 #if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666)
33
34 /*
35 * Control register bits
36 */
37 #define ADI_MAX32_I2C_CTRL_MASTER MXC_F_I2C_CTRL_MST
38
39 /*
40 * Interrupt enable bits
41 */
42 #define ADI_MAX32_I2C_INT_EN0_RX_THD MXC_F_I2C_INT_EN0_RX_THRESH
43 #define ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT MXC_F_I2C_INT_EN0_TX_LOCK_OUT
44 #define ADI_MAX32_I2C_INT_EN0_TX_THD MXC_F_I2C_INT_EN0_TX_THRESH
45 #define ADI_MAX32_I2C_INT_EN0_DONE MXC_F_I2C_INT_EN0_DONE
46 #define ADI_MAX32_I2C_INT_EN0_STOP MXC_F_I2C_INT_EN0_STOP
47 #define ADI_MAX32_I2C_INT_EN0_ADDR_MATCH MXC_F_I2C_INT_EN0_ADDR_MATCH
48 #define ADI_MAX32_I2C_INT_EN0_ADDR_ACK MXC_F_I2C_INT_EN0_ADDR_ACK
49 #define ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW MXC_F_I2C_INT_EN1_RX_OVERFLOW
50 #define ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW MXC_F_I2C_INT_EN1_TX_UNDERFLOW
51
52 #define ADI_MAX32_I2C_INT_EN0_ERR \
53 (MXC_F_I2C_INT_EN0_ARB_ER | MXC_F_I2C_INT_EN0_TO_ER | MXC_F_I2C_INT_EN0_ADDR_NACK_ER | \
54 MXC_F_I2C_INT_EN0_DATA_ER | MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER | MXC_F_I2C_INT_EN0_START_ER | \
55 MXC_F_I2C_INT_EN0_STOP_ER)
56
57 /*
58 * Interrupt flags
59 */
60 #define ADI_MAX32_I2C_INT_FL0_RX_THD MXC_F_I2C_INT_FL0_RX_THRESH
61 #define ADI_MAX32_I2C_INT_FL0_TX_LOCK_OUT MXC_F_I2C_INT_FL0_TX_LOCK_OUT
62 #define ADI_MAX32_I2C_INT_FL0_TX_THD MXC_F_I2C_INT_FL0_TX_THRESH
63 #define ADI_MAX32_I2C_INT_FL0_ADDR_MATCH MXC_F_I2C_INT_FL0_ADDR_MATCH
64 #define ADI_MAX32_I2C_INT_FL0_ADDR_ACK MXC_F_I2C_INT_FL0_ADDR_ACK
65 #define ADI_MAX32_I2C_INT_FL0_STOP MXC_F_I2C_INT_FL0_STOP
66 #define ADI_MAX32_I2C_INT_FL0_DONE MXC_F_I2C_INT_FL0_DONE
67 #define ADI_MAX32_I2C_INT_FL1_RX_OVERFLOW MXC_F_I2C_INT_FL1_RX_OVERFLOW
68
69 #define ADI_MAX32_I2C_INT_FL0_ERR \
70 (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | MXC_F_I2C_INT_FL0_ADDR_NACK_ER | \
71 MXC_F_I2C_INT_FL0_DATA_ER | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
72 MXC_F_I2C_INT_FL0_STOP_ER)
73
74 /*
75 * DMA enable bits
76 */
77 #define ADI_MAX32_I2C_DMA_RX_EN MXC_F_I2C_DMA_RXEN
78 #define ADI_MAX32_I2C_DMA_TX_EN MXC_F_I2C_DMA_TXEN
79
Wrap_MXC_I2C_GetIntEn(mxc_i2c_regs_t * i2c,unsigned int * int_en0,unsigned int * int_en1)80 static inline void Wrap_MXC_I2C_GetIntEn(mxc_i2c_regs_t *i2c, unsigned int *int_en0,
81 unsigned int *int_en1)
82 {
83 *int_en0 = i2c->int_en0;
84 *int_en1 = i2c->int_en1;
85 }
86
Wrap_MXC_I2C_SetIntEn(mxc_i2c_regs_t * i2c,unsigned int int_en0,unsigned int int_en1)87 static inline void Wrap_MXC_I2C_SetIntEn(mxc_i2c_regs_t *i2c, unsigned int int_en0,
88 unsigned int int_en1)
89 {
90 i2c->int_en0 = int_en0;
91 i2c->int_en1 = int_en1;
92 }
93
Wrap_MXC_I2C_GetTxFIFOLevel(mxc_i2c_regs_t * i2c)94 static inline uint32_t Wrap_MXC_I2C_GetTxFIFOLevel(mxc_i2c_regs_t *i2c)
95 {
96 return (i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TXFIFO) >> MXC_F_I2C_TX_CTRL1_TXFIFO_POS;
97 }
98
Wrap_MXC_I2C_SetRxCount(mxc_i2c_regs_t * i2c,unsigned int len)99 static inline void Wrap_MXC_I2C_SetRxCount(mxc_i2c_regs_t *i2c, unsigned int len)
100 {
101 if (len < 256) {
102 i2c->rx_ctrl1 = len;
103 } else {
104 i2c->rx_ctrl1 = 0;
105 }
106 }
107
Wrap_MXC_I2C_WaitForRestart(mxc_i2c_regs_t * i2c)108 static inline void Wrap_MXC_I2C_WaitForRestart(mxc_i2c_regs_t *i2c)
109 {
110 while (i2c->master_ctrl & MXC_F_I2C_MASTER_CTRL_RESTART) {}
111 }
112
Wrap_MXC_I2C_Start(mxc_i2c_regs_t * i2c)113 static inline void Wrap_MXC_I2C_Start(mxc_i2c_regs_t *i2c)
114 {
115 i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
116 }
117
Wrap_MXC_I2C_Restart(mxc_i2c_regs_t * i2c)118 static inline void Wrap_MXC_I2C_Restart(mxc_i2c_regs_t *i2c)
119 {
120 i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
121 }
122
Wrap_MXC_I2C_Stop(mxc_i2c_regs_t * i2c)123 static inline void Wrap_MXC_I2C_Stop(mxc_i2c_regs_t *i2c)
124 {
125 i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
126 }
127
128 /*
129 * MAX32690, MAX32655 related mapping
130 */
131 #elif defined(CONFIG_SOC_MAX32690) || defined(CONFIG_SOC_MAX32655) || \
132 defined(CONFIG_SOC_MAX32670) || defined(CONFIG_SOC_MAX32672) || \
133 defined(CONFIG_SOC_MAX32662) || defined(CONFIG_SOC_MAX32675) || \
134 defined(CONFIG_SOC_MAX32680) || defined(CONFIG_SOC_MAX78002) || \
135 defined(CONFIG_SOC_MAX78000)
136
137 /*
138 * Control register bits
139 */
140 #define ADI_MAX32_I2C_CTRL_MASTER MXC_F_I2C_CTRL_MST_MODE
141
142 /*
143 * Interrupt enable bits
144 */
145 #define ADI_MAX32_I2C_INT_EN0_RX_THD MXC_F_I2C_INTEN0_RX_THD
146 #define ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT MXC_F_I2C_INTEN0_TX_LOCKOUT
147 #define ADI_MAX32_I2C_INT_EN0_TX_THD MXC_F_I2C_INTEN0_TX_THD
148 #define ADI_MAX32_I2C_INT_EN0_DONE MXC_F_I2C_INTEN0_DONE
149 #define ADI_MAX32_I2C_INT_EN0_STOP MXC_F_I2C_INTEN0_STOP
150 #define ADI_MAX32_I2C_INT_EN0_ADDR_MATCH MXC_F_I2C_INTEN0_ADDR_MATCH
151 #define ADI_MAX32_I2C_INT_EN0_ADDR_ACK MXC_F_I2C_INTEN0_ADDR_ACK
152 #define ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW MXC_F_I2C_INTEN1_RX_OV
153 #define ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW MXC_F_I2C_INTEN1_TX_UN
154
155 #define ADI_MAX32_I2C_INT_EN0_ERR \
156 (MXC_F_I2C_INTEN0_ARB_ERR | MXC_F_I2C_INTEN0_TO_ERR | MXC_F_I2C_INTEN0_ADDR_NACK_ERR | \
157 MXC_F_I2C_INTEN0_DATA_ERR | MXC_F_I2C_INTEN0_DNR_ERR | MXC_F_I2C_INTEN0_START_ERR | \
158 MXC_F_I2C_INTEN0_STOP_ERR)
159
160 /*
161 * Interrupt flags
162 */
163 #define ADI_MAX32_I2C_INT_FL0_RX_THD MXC_F_I2C_INTFL0_RX_THD
164 #define ADI_MAX32_I2C_INT_FL0_TX_LOCK_OUT MXC_F_I2C_INTFL0_TX_LOCKOUT
165 #define ADI_MAX32_I2C_INT_FL0_TX_THD MXC_F_I2C_INTFL0_TX_THD
166 #define ADI_MAX32_I2C_INT_FL0_ADDR_MATCH MXC_F_I2C_INTFL0_ADDR_MATCH
167 #define ADI_MAX32_I2C_INT_FL0_ADDR_ACK MXC_F_I2C_INTFL0_ADDR_ACK
168 #define ADI_MAX32_I2C_INT_FL0_STOP MXC_F_I2C_INTFL0_STOP
169 #define ADI_MAX32_I2C_INT_FL0_DONE MXC_F_I2C_INTFL0_DONE
170 #define ADI_MAX32_I2C_INT_FL1_RX_OVERFLOW MXC_F_I2C_INTFL1_RX_OV
171
172 #define ADI_MAX32_I2C_INT_FL0_ERR \
173 (MXC_F_I2C_INTFL0_ARB_ERR | MXC_F_I2C_INTFL0_TO_ERR | MXC_F_I2C_INTFL0_ADDR_NACK_ERR | \
174 MXC_F_I2C_INTFL0_DATA_ERR | MXC_F_I2C_INTFL0_DNR_ERR | MXC_F_I2C_INTFL0_START_ERR | \
175 MXC_F_I2C_INTFL0_STOP_ERR)
176
177 /*
178 * DMA enable bits
179 */
180 #define ADI_MAX32_I2C_DMA_RX_EN MXC_F_I2C_DMA_RX_EN
181 #define ADI_MAX32_I2C_DMA_TX_EN MXC_F_I2C_DMA_TX_EN
182
183 static inline void Wrap_MXC_I2C_GetIntEn(mxc_i2c_regs_t *i2c, unsigned int *int_en0,
184 unsigned int *int_en1)
185 {
186 *int_en0 = i2c->inten0;
187 *int_en1 = i2c->inten1;
188 }
189
190 static inline void Wrap_MXC_I2C_SetIntEn(mxc_i2c_regs_t *i2c, unsigned int int_en0,
191 unsigned int int_en1)
192 {
193 i2c->inten0 = int_en0;
194 i2c->inten1 = int_en1;
195 }
196
197 static inline uint32_t Wrap_MXC_I2C_GetTxFIFOLevel(mxc_i2c_regs_t *i2c)
198 {
199 return (i2c->txctrl1 & MXC_F_I2C_TXCTRL1_LVL) >> MXC_F_I2C_TXCTRL1_LVL_POS;
200 }
201
202 static inline void Wrap_MXC_I2C_SetRxCount(mxc_i2c_regs_t *i2c, unsigned int len)
203 {
204 if (len < 256) {
205 i2c->rxctrl1 = len;
206 } else {
207 i2c->rxctrl1 = 0;
208 }
209 }
210
211 static inline void Wrap_MXC_I2C_WaitForRestart(mxc_i2c_regs_t *i2c)
212 {
213 while (i2c->mstctrl & MXC_F_I2C_MSTCTRL_RESTART) {}
214 }
215
216 static inline void Wrap_MXC_I2C_Start(mxc_i2c_regs_t *i2c)
217 {
218 i2c->mstctrl |= MXC_F_I2C_MSTCTRL_START;
219 }
220
221 static inline void Wrap_MXC_I2C_Restart(mxc_i2c_regs_t *i2c)
222 {
223 i2c->mstctrl |= MXC_F_I2C_MSTCTRL_RESTART;
224 }
225
226 static inline void Wrap_MXC_I2C_Stop(mxc_i2c_regs_t *i2c)
227 {
228 i2c->mstctrl |= MXC_F_I2C_MSTCTRL_STOP;
229 }
230
231 #endif
232
233 #ifdef __cplusplus
234 }
235 #endif
236
237 #endif // LIBRARIES_ZEPHYR_MAX_INCLUDE_WRAP_MAX32_I2C_H_
238
