1/*
2Purpose:    The text might be of interest in another place.
3            We have to decide whether we want to use it.
4
5            Until a decision is made, do not delete the file.
6
7Usage:      Storage of text. Not used in doxygen.
8
9Created:    March 21, 2014
10Author :    Bruno
11Changed:
12*/
13
14
15
16/**
17\struct     ARM_NAND_DEVICE
18\details
19Stores the characteristics of a NAND Flash device. This includes the page layout configuration, NAND type,
20device number (chip select), number of blocks, pages, sectors, and error correction code.
21
22<b>Parameter for:</b>
23  - \ref ARM_NAND_Initialize
24
25*******************************************************************************************************************/
26
27/**
28\struct     ARM_NAND_ECC_INFO_x
29\details
30Stores the default NAND page layout definition (with \ref spare_size and \ref spare_offset),
31which contains a \b Spare area after each sector. The struct \b ARM_NAND_ECC_INFO defines the \b Spare area.
32
33The page size is defined as the sum of \b User area plus \b Spare area.
34Each page has a small number of associated "spare" bytes (typically 1/32 of the data size) to store the Error Correction Algorithms (ECC).
35
36The following standard page sizes are available:
37
38Page Size| User + Spare Area
39---------|-------------------
40528      |  512 +  16 bytes
412112     | 2048 +  64 bytes
424224     | 4096 + 128 bytes
438448     | 8192 + 256 bytes
44
45
46\image html NAND_PageLayout.png "Default Page Layout"
47
48<p>&nbsp;</p>
49\image html NAND_SpareArea.png "Organization of the default 16-byte Spare area"
50
51NAND devices require bad block management by the driver software or by a separate controller chip.
52For example, SD cards have mechanisms that execute wear leveling and  bad block management.
53The memory capacity shrinks as more blocks are marked bad.
54The block size is a value specified as amount of flash pages.
55
56The following block sizes are available:
57
58Block Size| Pages
59----------|-------------------
60  8       |   8
61 16       |  16
62 32       |  32
63 64       |  64
64128       | 128
65256       | 256
66
67\note
68NAND chip manufacturers document the order in which pages can be written.
69Typically, single pages of an erase block must be written in sequential order starting from the first. Random-order writes are prohibited or unspecified.
70
71<b>Parameter for:</b>
72  - \ref ARM_NAND_DEVICE structure
73*******************************************************************************************************************/
74