1# Register Mapping {#regMap_pg}
2
3The table below associates some common register names used in CMSIS to the register names
4used in Technical Reference Manuals.
5
6<table class="cmtable" summary="Register Mapping">
7    <tr>
8      <th>CMSIS Register Name</th>
9      <th>Cortex-M3/M4/M7</th>
10      <th>Cortex-M0/M0+</th>
11      <th>Register Name</th>
12    </tr>
13    <tr>
14      <th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access</th>
15    </tr>
16    <tr>
17      <td>NVIC->ISER[]</td>
18      <td>NVIC_ISER0..7</td>
19      <td>ISER</td>
20      <td>Interrupt Set-Enable Registers</td>
21    </tr>
22    <tr>
23      <td>NVIC->ICER[]</td>
24      <td>NVIC_ICER0..7</td>
25      <td>ICER</td>
26      <td>Interrupt Clear-Enable Registers</td>
27    </tr>
28   <tr>
29      <td>NVIC->ISPR[]</td>
30      <td>NVIC_ISPR0..7</td>
31      <td>ISPR</td>
32      <td>Interrupt Set-Pending Registers</td>
33    </tr>
34  <tr>
35      <td>NVIC->ICPR[]</td>
36      <td>NVIC_ICPR0..7</td>
37      <td>ICPR</td>
38      <td>Interrupt Clear-Pending Registers</td>
39    </tr>
40  <tr>
41      <td>NVIC->IABR[]</td>
42      <td>NVIC_IABR0..7</td>
43      <td>-</td>
44      <td>Interrupt Active Bit Register</td>
45  </tr>
46  <tr>
47      <td>NVIC->IP[]</td>
48      <td>NVIC_IPR0..59</td>
49      <td>IPR0..7</td>
50      <td>Interrupt Priority Register</td>
51  </tr>
52  <tr>
53      <td>NVIC->STIR</td>
54      <td>STIR</td>
55      <td>-</td>
56      <td>Software Triggered Interrupt Register</td>
57  </tr>
58  <tr>
59    <th colspan="4">System Control Block (SCB) Register Access</th>
60  </tr>
61  <tr>
62      <td>SCB->CPUID</td>
63      <td>CPUID</td>
64      <td>CPUID</td>
65      <td>CPUID Base Register</td>
66  </tr>
67  <tr>
68      <td>SCB->ICSR</td>
69      <td>ICSR</td>
70      <td>ICSR</td>
71      <td>Interrupt Control and State Register</td>
72  </tr>
73  <tr>
74      <td>SCB->VTOR</td>
75      <td>VTOR</td>
76      <td>-</td>
77      <td>Vector Table Offset Register</td>
78  </tr>
79  <tr>
80      <td>SCB->AIRCR</td>
81      <td>AIRCR</td>
82      <td>AIRCR</td>
83      <td>Application Interrupt and Reset Control Register</td>
84  </tr>
85  <tr>
86      <td>SCB->SCR</td>
87      <td>SCR</td>
88      <td>SCR</td>
89      <td>System Control Register</td>
90  </tr>
91  <tr>
92      <td>SCB->CCR</td>
93      <td>CCR</td>
94      <td>CCR</td>
95      <td>Configuration and Control Register</td>
96  </tr>
97  <tr>
98      <td>SCB->SHP[]</td>
99      <td>SHPR1..3</td>
100      <td>SHPR2..3</td>
101      <td>System Handler Priority Registers</td>
102  </tr>
103  <tr>
104      <td>SCB->SHCSR</td>
105      <td>SHCSR</td>
106      <td>SHCSR</td>
107      <td>System Handler Control and State Register</td>
108  </tr>
109  <tr>
110      <td>SCB->CFSR</td>
111      <td>CFSR</td>
112      <td>-</td>
113      <td>Configurable Fault Status Registers</td>
114  </tr>
115  <tr>
116      <td>SCB->HFSR</td>
117      <td>HFSR</td>
118      <td>-</td>
119      <td>HardFault Status Register</td>
120  </tr>
121  <tr>
122      <td>SCB->DFSR</td>
123      <td>DFSR</td>
124      <td>-</td>
125      <td>Debug Fault Status Register</td>
126  </tr>
127  <tr>
128      <td>SCB->MMFAR</td>
129      <td>MMFAR</td>
130      <td>-</td>
131      <td>MemManage Fault Address Register</td>
132  </tr>
133  <tr>
134      <td>SCB->BFAR</td>
135      <td>BFAR</td>
136      <td>-</td>
137      <td>BusFault Address Register</td>
138  </tr>
139  <tr>
140      <td>SCB->AFSR</td>
141      <td>AFSR</td>
142      <td>-</td>
143      <td>Auxiliary Fault Status Register</td>
144  </tr>
145  <tr>
146      <td>SCB->PFR[]</td>
147      <td>ID_PFR0..1</td>
148      <td>-</td>
149      <td>Processor Feature Registers</td>
150  </tr>
151  <tr>
152      <td>SCB->DFR</td>
153      <td>ID_DFR0</td>
154      <td>-</td>
155      <td>Debug Feature Register</td>
156  </tr>
157  <tr>
158      <td>SCB->ADR</td>
159      <td>ID_AFR0</td>
160      <td>-</td>
161      <td>Auxiliary Feature Register</td>
162  </tr>
163  <tr>
164      <td>SCB->MMFR[]</td>
165      <td>ID_MMFR0..3</td>
166      <td>-</td>
167      <td>Memory Model Feature Registers</td>
168  </tr>
169  <tr>
170      <td>SCB->ISAR[]</td>
171      <td>ID_ISAR0..4</td>
172      <td>-</td>
173      <td>Instruction Set Attributes Registers</td>
174  </tr>
175  <tr>
176      <td>SCB->CPACR</td>
177      <td>CPACR</td>
178      <td>-</td>
179      <td>Coprocessor Access Control Register</td>
180  </tr>
181  <tr>
182    <th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access</th>
183  </tr>
184  <tr>
185      <td>SCnSCB->ICTR</td>
186      <td>ICTR</td>
187      <td>-</td>
188      <td>Interrupt Controller Type Register</td>
189  </tr>
190  <tr>
191      <td>SCnSCB->ACTLR</td>
192      <td>ACTLR</td>
193      <td>-</td>
194      <td>Auxiliary Control Register</td>
195  </tr>
196  <tr>
197    <th colspan="4">System Timer (SysTick) Control and Status Register Access</th>
198  </tr>
199  <tr>
200      <td>SysTick->CTRL</td>
201      <td>STCSR</td>
202      <td>SYST_CSR</td>
203      <td>SysTick Control and Status Register</td>
204  </tr>
205  <tr>
206      <td>SysTick->LOAD</td>
207      <td>STRVR</td>
208      <td>SYST_RVR</td>
209      <td>SysTick Reload Value Register</td>
210  </tr>
211  <tr>
212      <td>SysTick->VAL</td>
213      <td>STCVR</td>
214      <td>SYST_CVR</td>
215      <td>SysTick Current Value Register</td>
216  </tr>
217  <tr>
218      <td>SysTick->CALIB</td>
219      <td>STCR</td>
220      <td>SYST_CALIB</td>
221      <td>SysTick Calibaration Value Register</td>
222  </tr>
223  <tr>
224    <th colspan="4">Data Watchpoint and Trace (DWT) Register Access</th>
225  </tr>
226  <tr>
227      <td>DWT->CTRL</td>
228      <td>DWT_CTRL</td>
229      <td>-</td>
230      <td>Control Register</td>
231  </tr>
232  <tr>
233      <td>DWT->CYCCNT</td>
234      <td>DWT_CYCCNT</td>
235      <td>-</td>
236      <td>Cycle Count Register</td>
237  </tr>
238  <tr>
239      <td>DWT->CPICNT</td>
240      <td>DWT_CPICNT</td>
241      <td>-</td>
242      <td>CPI Count Register</td>
243  </tr>
244  <tr>
245      <td>DWT->EXCCNT</td>
246      <td>DWT_EXCCNT</td>
247      <td>-</td>
248      <td>Exception Overhead Count Register</td>
249  </tr>
250  <tr>
251      <td>DWT->SLEEPCNT</td>
252      <td>DWT_SLEEPCNT</td>
253      <td>-</td>
254      <td>Sleep Count Register</td>
255  </tr>
256  <tr>
257      <td>DWT->LSUCNT</td>
258      <td>DWT_LSUCNT</td>
259      <td>-</td>
260      <td>LSU Count Register</td>
261  </tr>
262  <tr>
263      <td>DWT->FOLDCNT</td>
264      <td>DWT_FOLDCNT</td>
265      <td>-</td>
266      <td>Folded-instruction Count Register</td>
267  </tr>
268  <tr>
269      <td>DWT->PCSR</td>
270      <td>DWT_PCSR</td>
271      <td>-</td>
272      <td>Program Counter Sample Register</td>
273  </tr>
274  <tr>
275      <td>DWT->COMP0..3</td>
276      <td>DWT_COMP0..3</td>
277      <td>-</td>
278      <td>Comparator Register 0..3</td>
279  </tr>
280  <tr>
281      <td>DWT->MASK0..3</td>
282      <td>DWT_MASK0..3</td>
283      <td>-</td>
284      <td>Mask Register 0..3</td>
285  </tr>
286  <tr>
287      <td>DWT->FUNCTION0..3</td>
288      <td>DWT_FUNCTION0..3</td>
289      <td>-</td>
290      <td>Function Register 0..3</td>
291  </tr>
292  <tr>
293    <th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access</th>
294  </tr>
295  <tr>
296      <td>ITM->PORT[]</td>
297      <td>ITM_STIM0..31</td>
298      <td>-</td>
299      <td>Stimulus Port Registers</td>
300  </tr>
301  <tr>
302      <td>ITM->TER</td>
303      <td>ITM_TER</td>
304      <td>-</td>
305      <td>Trace Enable Register</td>
306  </tr>
307  <tr>
308      <td>ITM->TPR</td>
309      <td>ITM_TPR</td>
310      <td>-</td>
311      <td>ITM Trace Privilege Register</td>
312  </tr>
313  <tr>
314      <td>ITM->TCR</td>
315      <td>ITM_TCR</td>
316      <td>-</td>
317      <td>Trace Control Register</td>
318  </tr>
319  <tr>
320    <th colspan="4">Trace Port Interface (TPIU) Register Access</th>
321  </tr>
322  <tr>
323      <td>TPI->SSPSR</td>
324      <td>TPIU_SSPR</td>
325      <td>-</td>
326      <td>Supported Parallel Port Size Register</td>
327  </tr>
328  <tr>
329      <td>TPI->CSPSR</td>
330      <td>TPIU_CSPSR</td>
331      <td>-</td>
332      <td>Current Parallel Port Size Register</td>
333  </tr>
334  <tr>
335      <td>TPI->ACPR</td>
336      <td>TPIU_ACPR</td>
337      <td>-</td>
338      <td>Asynchronous Clock Prescaler Register</td>
339  </tr>
340  <tr>
341      <td>TPI->SPPR</td>
342      <td>TPIU_SPPR</td>
343      <td>-</td>
344      <td>Selected Pin Protocol Register</td>
345  </tr>
346  <tr>
347      <td>TPI->FFSR</td>
348      <td>TPIU_FFSR</td>
349      <td>-</td>
350      <td>Formatter and Flush Status Register</td>
351  </tr>
352  <tr>
353      <td>TPI->FFCR</td>
354      <td>TPIU_FFCR</td>
355      <td>-</td>
356      <td>Formatter and Flush Control Register</td>
357  </tr>
358  <tr>
359      <td>TPI->FSCR</td>
360      <td>TPIU_FSCR</td>
361      <td>-</td>
362      <td>Formatter Synchronization Counter Register</td>
363  </tr>
364  <tr>
365      <td>TPI->TRIGGER</td>
366      <td>TRIGGER</td>
367      <td>-</td>
368      <td>TRIGGER</td>
369  </tr>
370  <tr>
371      <td>TPI->FIFO0</td>
372      <td>FIFO data 0</td>
373      <td>-</td>
374      <td>Integration ETM Data</td>
375  </tr>
376  <tr>
377      <td>TPI->ITATBCTR2</td>
378      <td>ITATBCTR2</td>
379      <td>-</td>
380      <td>ITATBCTR2</td>
381  </tr>
382  <tr>
383      <td>TPI->ITATBCTR0</td>
384      <td>ITATBCTR0</td>
385      <td>-</td>
386      <td>ITATBCTR0</td>
387  </tr>
388  <tr>
389      <td>TPI->FIFO1</td>
390      <td>FIFO data 1</td>
391      <td>-</td>
392      <td>Integration ITM Data</td>
393  </tr>
394  <tr>
395      <td>TPI->ITCTRL</td>
396      <td>TPIU_ITCTRL</td>
397      <td>-</td>
398      <td>Integration Mode Control</td>
399  </tr>
400  <tr>
401      <td>TPI->CLAIMSET</td>
402      <td>CLAIMSET</td>
403      <td>-</td>
404      <td>Claim tag set</td>
405  </tr>
406  <tr>
407      <td>TPI->CLAIMCLR</td>
408      <td>CLAIMCLR</td>
409      <td>-</td>
410      <td>Claim tag clear</td>
411  </tr>
412  <tr>
413      <td>TPI->DEVID</td>
414      <td>TPIU_DEVID</td>
415      <td>-</td>
416      <td>TPIU_DEVID</td>
417  </tr>
418  <tr>
419      <td>TPI->DEVTYPE</td>
420      <td>TPIU_DEVTYPE</td>
421      <td>-</td>
422      <td>TPIU_DEVTYPE</td>
423  </tr>
424  <tr>
425    <th colspan="4">Memory Protection Unit (MPU) Register Access</th>
426  </tr>
427  <tr>
428      <td>MPU->TYPE</td>
429      <td>MPU_TYPE</td>
430      <td>-</td>
431      <td>MPU Type Register</td>
432  </tr>
433  <tr>
434      <td>MPU->CTRL</td>
435      <td>MPU_CTRL</td>
436      <td>-</td>
437      <td>MPU Control Register</td>
438  </tr>
439  <tr>
440      <td>MPU->RNR</td>
441      <td>MPU_RNR</td>
442      <td>-</td>
443      <td>MPU Region Number Register</td>
444  </tr>
445  <tr>
446      <td>MPU->RBAR</td>
447      <td>MPU_RBAR</td>
448      <td>-</td>
449      <td>MPU Region Base Address Register</td>
450  </tr>
451  <tr>
452      <td>MPU->RASR</td>
453      <td>MPU_RASR</td>
454      <td>-</td>
455      <td>MPU Region Attribute and Size Register</td>
456  </tr>
457  <tr>
458      <td>MPU->RBAR_A1..3</td>
459      <td>MPU_RBAR_A1..3</td>
460      <td>-</td>
461      <td>MPU alias Register</td>
462  </tr>
463  <tr>
464      <td>MPU->RASR_A1..3</td>
465      <td>MPU_RASR_A1..3</td>
466      <td>-</td>
467      <td>MPU alias Register</td>
468  </tr>
469  <tr>
470    <th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]</th>
471  </tr>
472  <tr>
473      <td>FPU->FPCCR</td>
474      <td>FPCCR</td>
475      <td>-</td>
476      <td>FP Context Control Register</td>
477  </tr>
478  <tr>
479      <td>FPU->FPCAR</td>
480      <td>FPCAR</td>
481      <td>-</td>
482      <td>FP Context Address Register</td>
483  </tr>
484  <tr>
485      <td>FPU->FPDSCR</td>
486      <td>FPDSCR</td>
487      <td>-</td>
488      <td>FP Default Status Control Register</td>
489  </tr>
490  <tr>
491      <td>FPU->MVFR0..1</td>
492      <td>MVFR0..1</td>
493      <td>-</td>
494      <td>Media and VFP Feature Registers</td>
495  </tr>
496</table>
497