1# Revision History {#core_revisionHistory}
2
3CMSIS-Core (M) component is maintained with its own versioning that gets officially updated upon releases of the [CMSIS Software Pack](../General/cmsis_pack.html).
4
5The table below provides information about the changes delivered with specific versions of CMSIS-Core (M).
6
7<table class="cmtable" summary="Revision History">
8    <tr>
9      <th>Version</th>
10      <th>Description</th>
11    </tr>
12    <tr>
13      <td>V6.1.0</td>
14      <td>
15        <ul>
16          <li>Added support for Cortex-M52</li>
17          <li>Added deprecated CoreDebug symbols for CMSIS 5 compatibility</li>
18          <li>Added define CMSIS_DISABLE_DEPRECATED to hide deprecated symbols</li>
19        </ul>
20      </td>
21    </tr>
22    <tr>
23      <td>V6.0.0</td>
24      <td>
25        <ul>
26          <li>Core(M) and Core(A) joined into single Core component</li>
27          <li>Core header files reworked, aligned with Cortex-M Technical Reference Manuals (TRMs).
28              <br/>See \ref core6_changes "Breaking changes in CMSIS-Core v6 header files" for details, and [GitHub issue #122](https://github.com/ARM-software/CMSIS_6/issues/122).</li>
29          <li>Previously deprecated features removed</li>
30          <li>Dropped support for Arm Compiler 5</li>
31        </ul>
32      </td>
33    </tr>
34    <tr>
35      <td>V5.6.0</td>
36      <td>
37        <ul>
38          <li>Added: Arm Cortex-M85 cpu support</li>
39          <li>Added: Arm China Star-MC1 cpu support</li>
40          <li>Updated: system_ARMCM55.c</li>
41        </ul>
42      </td>
43    </tr>
44    <tr>
45      <td>V5.5.0</td>
46      <td>
47        <ul>
48          <li>Updated GCC LinkerDescription, GCC Assembler startup</li>
49          <li>Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC</li>
50          <li>Changed C-Startup to default Startup.</li>
51          </li>
52            Updated Armv8-M Assembler startup to use GAS syntax<br>
53            Note: Updating existing projects may need manual user interaction!
54          </li>
55        </ul>
56      </td>
57    </tr>
58    <tr>
59      <td>V5.4.0</td>
60      <td>
61        <ul>
62          <li>Added: Cortex-M55 cpu support</li>
63          <li>Enhanced: MVE support for Armv8.1-MML</li>
64          <li>Fixed: Device config define checks</li>
65          <li>Added: \ref cache_functions_m7 for Armv7-M and later</li>
66        </ul>
67      </td>
68    </tr>
69    <tr>
70      <td>V5.3.0</td>
71      <td>
72        <ul>
73          <li>Added: Provisions for compiler-independent C startup code.</li>
74        </ul>
75      </td>
76    </tr>
77    <tr>
78      <td>V5.2.1</td>
79      <td>
80        <ul>
81          <li>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0</li>
82        </ul>
83      </td>
84    </tr>
85    <tr>
86      <td>V5.2.0</td>
87      <td>
88        <ul>
89          <li>Added: Cortex-M35P support.</li>
90          <li>Added: Cortex-M1 support.
91          <li>Added: Armv8.1 architecture support.
92          <li>Added: \ref __RESTRICT and \ref __STATIC_FORCEINLINE compiler control macros.
93        </ul>
94      </td>
95    </tr>
96    <tr>
97      <td>V5.1.2</td>
98      <td>
99        <ul>
100          <li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
101          <li>Added __NO_RETURN to  __NVIC_SystemReset() to silence compiler warnings.</li>
102          <li>Added support for Cortex-M1 (beta).</li>
103          <li>Removed usage of register keyword.</li>
104          <li>Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.</li>
105          <li>Enhanced MPUv7 API with defines for memory access attributes.</li>
106        </ul>
107      </td>
108    </tr>
109    <tr>
110      <td>V5.1.1</td>
111      <td>
112        <ul>
113          <li>Aligned MSPLIM and PSPLIM access functions along supported compilers.</li>
114        </ul>
115      </td>
116    </tr>
117    <tr>
118      <td>V5.1.0</td>
119      <td>
120        <ul>
121          <li>Added MPU Functions for ARMv8-M for Cortex-M23/M33.</li>
122          <li>Moved __SSAT and __USAT intrinsics to CMSIS-Core.</li>
123          <li>Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.</li>
124        </ul>
125      </td>
126    </tr>
127    <tr>
128      <td>V5.0.2</td>
129      <td>
130        <ul>
131          <li>Added macros  \ref \__UNALIGNED_UINT16_READ,  \ref \__UNALIGNED_UINT16_WRITE.</li>
132          <li>Added macros  \ref \__UNALIGNED_UINT32_READ,  \ref \__UNALIGNED_UINT32_WRITE.</li>
133          <li>Deprecated macro __UNALIGNED_UINT32.</li>
134          <li>Changed \ref version_control_gr macros to be core agnostic.</li>
135          <li>Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.</li>
136        </ul>
137      </td>
138    </tr>
139    <tr>
140      <td>V5.0.1</td>
141      <td>
142        <ul>
143          <li>Added: macro \ref \__PACKED_STRUCT.</li>
144          <li>Added: uVisor support.</li>
145        </ul>
146      </td>
147    </tr>
148    <tr>
149      <td>V5.00</td>
150      <td>
151        <ul>
152          <li>Added: Cortex-M23, Cortex-M33 support.</li>
153          <li>Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
154          <li>Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
155          <li>Reworked: SAU register and functions.</li>
156          <li>Added: macro \ref \__ALIGNED.</li>
157          <li>Updated: function \ref SCB_EnableICache.</li>
158          <li>Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.</li>
159          <li>Added: macro \ref \__PACKED.</li>
160          <li>Updated: compiler specific include files.</li>
161          <li>Updated: core dependant include files.</li>
162          <li>Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.</li>
163        </ul>
164      </td>
165    </tr>
166    <tr>
167      <td>V5.00<br>Beta 6</td>
168      <td>
169        <ul>
170          <li>Added: SCB_CFSR register bit definitions.</li>
171          <li>Added: function \ref NVIC_GetEnableIRQ.</li>
172          <li>Updated: core instruction macros \ref \__NOP, \ref \__WFI, \ref \__WFE, \ref \__SEV for toolchain GCC.</li>
173        </ul>
174      </td>
175    </tr>
176    <tr>
177      <td>V5.00<br>Beta 5</td>
178      <td>
179        <ul>
180          <li>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.</li>
181          <li>Added: DSP libraries build projects to CMSIS pack.</li>
182        </ul>
183      </td>
184    </tr>
185    <tr>
186      <td>V5.00<br>Beta 4</td>
187      <td>
188        <ul>
189          <li>Updated: ARMv8M device files.</li>
190          <li>Corrected: ARMv8MBL interrupts.</li>
191          <li>Reworked: NVIC functions.</li>
192        </ul>
193      </td>
194    </tr>
195    <tr>
196      <td>V5.00<br>Beta 2</td>
197      <td>
198        <ul>
199          <li>Changed: ARMv8M SAU regions to 8.</li>
200          <li>Changed: moved function \ref TZ_SAU_Setup to file partition_&lt;device&gt;.h.</li>
201          <li>Changed: license under Apache-2.0.</li>
202          <li>Added: check if macro is defined before use.</li>
203          <li>Corrected: function \ref SCB_DisableDCache.</li>
204          <li>Corrected: macros \ref \_VAL2FLD, \ref \_FLD2VAL.</li>
205          <li>Added: NVIC function virtualization with macros \ref CMSIS_NVIC_VIRTUAL and \ref CMSIS_VECTAB_VIRTUAL.</li>
206        </ul>
207      </td>
208    </tr>
209    <tr>
210      <td>V5.00<br>Beta 1</td>
211      <td>
212        <ul>
213          <li>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.</li>
214          <li>Renamed: core\_*.h to lower case.</li>
215          <li>Added: function \ref SCB_GetFPUType to all CMSIS cores.</li>
216          <li>Added: ARMv8-M support.</li>
217        </ul>
218      </td>
219    </tr>
220    <tr>
221      <td>V4.30</td>
222      <td>
223        <ul>
224          <li>Corrected: DoxyGen function parameter comments.</li>
225          <li>Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).</li>
226          <li>Corrected: GCC toolchain: suppressed irrelevant compiler warnings.</li>
227          <li>Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).</li>
228        </ul>
229      </td>
230    </tr>
231    <tr>
232      <td>V4.20</td>
233      <td>
234        <ul>
235          <li>Corrected: MISRA-C:2004 violations.</li>
236          <li>Corrected: predefined macro for TI CCS Compiler.</li>
237          <li>Corrected: function \ref __SHADD16 in arm_math.h.</li>
238          <li>Updated: cache functions for Cortex-M7.</li>
239          <li>Added: macros \ref _VAL2FLD, \ref _FLD2VAL to core\_*.h.</li>
240          <li>Updated: functions \ref __QASX, \ref __QSAX, \ref __SHASX, \ref __SHSAX.</li>
241          <li>Corrected: potential bug in function \ref __SHADD16.</li>
242        </ul>
243      </td>
244    </tr>
245    <tr>
246      <td>V4.10</td>
247      <td>
248        <ul>
249          <li>Corrected: MISRA-C:2004 violations.</li>
250          <li>Corrected: intrinsic functions \ref __DSB, \ref __DMB, \ref __ISB.</li>
251          <li>Corrected: register definitions for ITCMCR register.</li>
252          <li>Corrected: register definitions for \ref CONTROL_Type register.</li>
253          <li>Added: functions \ref SCB_GetFPUType, \ref SCB_InvalidateDCache_by_Addr to core_cm7.h.</li>
254          <li>Added: register definitions for \ref APSR_Type, \ref IPSR_Type, \ref xPSR_Type register.</li>
255          <li>Added: \ref __set_BASEPRI_MAX function to core_cmFunc.h.</li>
256          <li>Added: intrinsic functions \ref __RBIT, \ref __CLZ  for Cortex-M0/CortexM0+.</li>
257        </ul>
258      </td>
259    </tr>
260    <tr>
261      <td>V4.00</td>
262      <td>
263        <ul>
264          <li>Added: Cortex-M7 support.</li>
265          <li>Added: intrinsic functions for \ref __RRX, \ref __LDRBT, \ref __LDRHT, \ref __LDRT, \ref __STRBT, \ref __STRHT, and \ref __STRT</li>
266        </ul>
267      </td>
268    </tr>
269    <tr>
270      <td>V3.40</td>
271      <td>
272       <ul>
273         <li>Corrected: C++ include guard settings.</li>
274       </ul>
275     </td>
276    </tr>
277    <tr>
278      <td>V3.30</td>
279      <td>
280        <ul>
281          <li>Added: COSMIC tool chain support.</li>
282          <li>Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.</li>
283          <li>Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.</li>
284          <li>Corrected: GCC/CLang warnings.</li>
285        </ul>
286      </td>
287    </tr>
288    <tr>
289      <td>V3.20</td>
290      <td>
291        <ul>
292          <li>Added: \ref __BKPT instruction intrinsic.</li>
293          <li>Added: \ref __SMMLA instruction intrinsic for Cortex-M4.</li>
294          <li>Corrected: \ref ITM_SendChar.</li>
295          <li>Corrected: \ref __enable_irq, \ref __disable_irq and inline assembly for GCC Compiler.</li>
296          <li>Corrected: \ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.</li>
297          <li>Corrected: rework of in-line assembly functions to remove potential compiler warnings.</li>
298        </ul>
299      </td>
300    </tr>
301    <tr>
302      <td>V3.01</td>
303      <td>
304       <ul>
305         <li>Added support for Cortex-M0+ processor.</li>
306       </ul>
307     </td>
308    </tr>
309    <tr>
310      <td>V3.00</td>
311      <td>
312        <ul>
313          <li>Added support for GNU GCC ARM Embedded Compiler.</li>
314          <li>Added function \ref __ROR.</li>
315          <li>Added \ref regMap_pg for TPIU, DWT.</li>
316          <li>Added support for \ref core_config_sect "SC000 and SC300 processors".</li>
317          <li>Corrected \ref ITM_SendChar function.</li>
318          <li>Corrected the functions \ref __STREXB, \ref __STREXH, \ref __STREXW for the GNU GCC compiler section.</li>
319          <li>Documentation restructured.</li>
320        </ul>
321      </td>
322    </tr>
323    <tr>
324      <td>V2.10</td>
325      <td>
326        <ul>
327          <li>Updated documentation.</li>
328          <li>Updated CMSIS core include files.</li>
329          <li>Changed CMSIS/Device folder structure.</li>
330          <li>Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.</li>
331          <li>Reworked CMSIS DSP library examples.</li>
332        </ul>
333      </td>
334    </tr>
335    <tr>
336      <td>V2.00</td>
337      <td>
338       <ul>
339         <li>Added support for Cortex-M4 processor.</li>
340       </ul>
341     </td>
342    </tr>
343    <tr>
344      <td>V1.30</td>
345      <td>
346        <ul>
347          <li>Reworked Startup Concept.</li>
348          <li>Added additional Debug Functionality.</li>
349          <li>Changed folder structure.</li>
350          <li>Added doxygen comments.</li>
351          <li>Added definitions for bit.</li>
352        </ul>
353      </td>
354    </tr>
355    <tr>
356      <td>V1.01</td>
357      <td>
358       <ul>
359         <li>Added support for Cortex-M0 processor.</li>
360       </ul>
361      </td>
362    </tr>
363    <tr>
364      <td>V1.01</td>
365      <td>
366       <ul>
367         <li>Added intrinsic functions for \ref __LDREXB, \ref __LDREXH, \ref __LDREXW, \ref __STREXB, \ref __STREXH, \ref __STREXW, and \ref __CLREX</li>
368       </ul>
369     </td>
370    </tr>
371    <tr>
372      <td>V1.00</td>
373      <td>
374       <ul>
375         <li>Initial Release for Cortex-M3 processor.</li>
376       </ul>
377     </td>
378    </tr>
379</table>
380
381\section core6_changes Breaking changes in CMSIS-Core 6
382
383\ref cmsis_standard_files in CMSIS-Core v6.0.0 have received a number of changes that are incompatible with CMSIS-Core v5.6.0.
384
385In summary, following types of incompatible changes are present:
386
387 - struct member is renamed in an existing structure (e.g. NVIC->PR -> NVIC->IPR)
388 - struct name is changed (e.g. CoreDebug_Type -> DCB_Type)
389 - define name is changed (e.g. CoreDebug_DEMCR_TRCENA_Msk -> DCB_DEMCR_TRCENA_Msk)
390
391For the latest two types, CMSIS-Core v6.1 and higher provide also the original CMSIS 5 symbols as deprecated and so improve the backward compatibility. See section \ref deprecated_gr.
392
393Additionally, the [GitHub issue #122](https://github.com/ARM-software/CMSIS_6/issues/122) discusses how to resolve such incompatibilities.
394
395Below is detailed information about the changes relevant for each Cortex-M core.
396
397**Cortex-M0, Cortex-M0+, Cortex-M1:**
398
399- struct NVIC_Type
400  - member IP renamed to IPR
401- struct SCB_Type
402  - member SHP renamed to SHPR
403
404**Cortex-M3, Cortex-M4:**
405
406- struct NVIC_Type
407  - member IP renamed to IPR
408- struct SCB_Type
409  - member SHP renamed to SHPR
410  - member PFR renamed to ID_PFR
411  - member PFR renamed to ID_PFR
412  - member DFR renamed to ID_PFR
413  - member ADR renamed to ID_AFR
414  - member MMFR renamed to ID_MMFR
415  - member ISAR renamed to ID_ISAR
416  - member STIR added
417- struct ITM_Type:
418  - members PIDx and CIDx removed
419- define names for ITM_TCR_* changed
420- define names for ITM_LSR_* changed
421- struct TPI_Type renamed to TPIU_Type
422- define names for TPI_* renamed to TPIU_*
423- define names for FPU_MVFR0/1_* changed (Cortex-M4)
424- struct CoreDebug_Type renamed to DCB_Type
425- defines for CoreDebug_* renamed to DCB_*
426
427**Cortex-M7:**
428
429- struct NVIC_Type
430  - member IP renamed to IPR
431- struct SCB_Type
432  - member ID_MFR renamed to ID_MMFR
433- struct ITM_Type:
434  - members PIDx and CIDx removed
435- define names for ITM_TCR_* changed
436- define names for ITM_LSR_* changed
437- struct TPI_Type renamed to TPIU_Type
438- define names for TPI_* renamed to TPIU_*
439- define names for FPU_MVFR0/1_* changed
440- struct CoreDebug_Type renamed to DCB_Type
441- defines for CoreDebug_* renamed to DCB_*
442
443**Cortex-M23:**
444
445- struct DWT_Type
446  - member RESERVED0[6] replaced by CYCCNT, CPICNT, EXCCNT, SLEEPCNT, LSUCNT, FOLDCNT
447  - other RESERVED members mainly removed
448- struct TPI_Type renamed to TPIU_Type
449- define names for TPI_* renamed to TPIU_*
450- struct CoreDebug_Type removed (struct DCB_Type already existed)
451- defines CoreDebug_* removed (defines DCB_* already existed)
452
453**Cortex-M33:**
454
455- struct ITM_Type:
456  - members LAR, LSR removed
457  - members PIDx and CIDx removed
458- struct TPI_Type renamed to TPIU_Type
459- define names for TPI_* renamed to TPIU_*
460- define names for FPU_MVFR0/1_* changed
461- struct CoreDebug_Type removed (struct DCB_Type already existed)
462- defines CoreDebug_* removed (defines DCB_* already existed)
463
464**Cortex-M55, Cortex-M85:**
465
466- struct ITM_Type:
467  - members LAR, LSR removed
468  - members PIDx and CIDx removed
469- struct DWT_Type:
470  - members PIDx and CIDx removed
471- struct EWIC_Type
472  - all members renamed
473- define names EWIC_* changed
474- struct TPI_Type renamed to TPIU_Type
475  - members LAR, LSR replaced
476- define names for TPI_* renamed to TPIU_*
477- struct PMU_Type
478  - members PIDx and CIDx removed
479- struct CoreDebug_Type removed (struct DCB_Type already existed)
480- defines CoreDebug_* removed (defines DCB_* already existed)
481- struct DIB_Type
482  - members DLAR, DLSR removed (replaced by RESERVED0[2])
483- defines for DIB_DLAR_* and DIB_DLSR_* removed
484