1 /*----------------------------------------------------------------------------- 2 * Name: CV_Config.h 3 * Purpose: CV Config header 4 *---------------------------------------------------------------------------- 5 * Copyright (c) 2017 - 2021 ARM Limited. All rights reserved. 6 *----------------------------------------------------------------------------*/ 7 #ifndef __CV_CONFIG_H 8 #define __CV_CONFIG_H 9 10 #include "RTE_Components.h" 11 #include CMSIS_device_header 12 13 //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 14 15 // <h> Common Test Settings 16 // <o> Print Output Format <0=> Plain Text <1=> XML 17 // <i> Set the test results output format to plain text or XML 18 #ifndef PRINT_XML_REPORT 19 #define PRINT_XML_REPORT 0 20 #endif 21 // <o> Buffer size for assertions results 22 // <i> Set the buffer size for assertions results buffer 23 #define BUFFER_ASSERTIONS 128U 24 // </h> 25 26 // <h> Disable Test Cases 27 // <i> Uncheck to disable an individual test case 28 // <q0> TC_CoreInstr_NOP 29 #define TC_COREINSTR_NOP_EN 1 30 // <q0> TC_CoreInstr_REV 31 #define TC_COREINSTR_REV_EN 1 32 // <q0> TC_CoreInstr_REV16 33 #define TC_COREINSTR_REV16_EN 1 34 // <q0> TC_CoreInstr_REVSH 35 #define TC_COREINSTR_REVSH_EN 1 36 // <q0> TC_CoreInstr_ROR 37 #define TC_COREINSTR_ROR_EN 1 38 // <q0> TC_CoreInstr_RBIT 39 #define TC_COREINSTR_RBIT_EN 1 40 // <q0> TC_CoreInstr_CLZ 41 #define TC_COREINSTR_CLZ_EN 1 42 // <q0> TC_CoreInstr_Exclusives 43 #define TC_COREINSTR_EXCLUSIVES_EN 1 44 // <q0> TC_CoreInstr_SSAT 45 #define TC_COREINSTR_SSAT_EN 1 46 // <q0> TC_CoreInstr_USAT 47 #define TC_COREINSTR_USAT_EN 1 48 49 // <q0> TC_CoreAFunc_IRQ 50 #define TC_COREAFUNC_IRQ 1 51 // <q0> TC_CoreAFunc_FaultIRQ 52 #define TC_COREAFUNC_FAULTIRQ 1 53 // <q0> TC_CoreAFunc_FPSCR 54 #define TC_COREAFUNC_FPSCR 1 55 // <q0> TC_CoreAFunc_CPSR 56 #define TC_COREAFUNC_CPSR 1 57 // <q0> TC_CoreAFunc_Mode 58 #define TC_COREAFUNC_MODE 1 59 // <q0> TC_CoreAFunc_FPEXC 60 #define TC_COREAFUNC_FPEXC 1 61 // <q0> TC_CoreAFunc_ACTLR 62 #define TC_COREAFUNC_ACTLR 1 63 // <q0> TC_CoreAFunc_CPACR 64 #define TC_COREAFUNC_CPACR 1 65 // <q0> TC_CoreAFunc_DFSR 66 #define TC_COREAFUNC_DFSR 1 67 // <q0> TC_CoreAFunc_IFSR 68 #define TC_COREAFUNC_IFSR 1 69 // <q0> TC_CoreAFunc_ISR 70 #define TC_COREAFUNC_ISR 1 71 // <q0> TC_CoreAFunc_CBAR 72 #define TC_COREAFUNC_CBAR 1 73 // <q0> TC_CoreAFunc_TTBR0 74 #define TC_COREAFUNC_TTBR0 1 75 // <q0> TC_CoreAFunc_DACR 76 #define TC_COREAFUNC_DACR 1 77 // <q0> TC_CoreAFunc_SCTLR 78 #define TC_COREAFUNC_SCTLR 1 79 // <q0> TC_CoreAFunc_MPIDR 80 #define TC_COREAFUNC_MPIDR 1 81 // <q0> TC_CoreAFunc_VBAR 82 #define TC_COREAFUNC_VBAR 1 83 // <q0> TC_CoreAFunc_MVBAR 84 #define TC_COREAFUNC_MVBAR 1 85 // <q0> TC_CoreAFunc_FPU_Enable 86 #define TC_COREAFUNC_FPU_ENABLE 1 87 88 // <q0> TC_GenTimer_CNTFRQ 89 #define TC_GENTIMER_CNTFRQ 1 90 // <q0> TC_GenTimer_CNTP_TVAL 91 #define TC_GENTIMER_CNTP_TVAL 1 92 // <q0> TC_GenTimer_CNTP_CTL 93 #define TC_GENTIMER_CNTP_CTL 1 94 // <q0> TC_GenTimer_CNTPCT 95 #define TC_GENTIMER_CNTPCT 1 96 // <q0> TC_GenTimer_CNTP_CVAL 97 #define TC_GENTIMER_CNTP_CVAL 1 98 99 // <q0> TC_CAL1Cache_EnDisable 100 #define TC_CAL1CACHE_ENDISABLE 1 101 // <q0> TC_CAL1Cache_EnDisableBTAC 102 #define TC_CAL1CACHE_ENDISABLEBTAC 1 103 // <q0> TC_CAL1Cache_log2_up 104 #define TC_CAL1CACHE_LOG2_UP 1 105 // <q0> TC_CAL1Cache_InvalidateDCacheAll 106 #define TC_CAL1CACHE_INVALIDATEDCACHEALL 1 107 // <q0> TC_CAL1Cache_CleanDCacheAll 108 #define TC_CAL1CACHE_CLEANDCACHEALL 1 109 // <q0> TC_CAL1Cache_CleanInvalidateDCacheAll 110 #define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1 111 // </h> 112 113 #endif /* __CV_CONFIG_H */ 114 115
