1 /**************************************************************************//**
2 * @file partition_ARMCM23.h
3 * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
4 * @version V5.3.1
5 * @date 09. July 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef PARTITION_ARMCM23_H
26 #define PARTITION_ARMCM23_H
27
28 /*
29 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
30 */
31
32 /*
33 // <e>Initialize Security Attribution Unit (SAU) CTRL register
34 */
35 #define SAU_INIT_CTRL 1
36
37 /*
38 // <q> Enable SAU
39 // <i> Value for SAU->CTRL register bit ENABLE
40 */
41 #define SAU_INIT_CTRL_ENABLE 1
42
43 /*
44 // <o> When SAU is disabled
45 // <0=> All Memory is Secure
46 // <1=> All Memory is Non-Secure
47 // <i> Value for SAU->CTRL register bit ALLNS
48 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
49 */
50 #define SAU_INIT_CTRL_ALLNS 0
51
52 /*
53 // </e>
54 */
55
56 /*
57 // <h>Initialize Security Attribution Unit (SAU) Address Regions
58 // <i>SAU configuration specifies regions to be one of:
59 // <i> - Secure and Non-Secure Callable
60 // <i> - Non-Secure
61 // <i>Note: All memory regions not configured by SAU are Secure
62 */
63 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
64
65 /*
66 // <e>Initialize SAU Region 0
67 // <i> Setup SAU Region 0 memory attributes
68 */
69 #define SAU_INIT_REGION0 1
70
71 /*
72 // <o>Start Address <0-0xFFFFFFE0>
73 */
74 #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
75
76 /*
77 // <o>End Address <0x1F-0xFFFFFFFF>
78 */
79 #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
80
81 /*
82 // <o>Region is
83 // <0=>Non-Secure
84 // <1=>Secure, Non-Secure Callable
85 */
86 #define SAU_INIT_NSC0 1
87 /*
88 // </e>
89 */
90
91 /*
92 // <e>Initialize SAU Region 1
93 // <i> Setup SAU Region 1 memory attributes
94 */
95 #define SAU_INIT_REGION1 1
96
97 /*
98 // <o>Start Address <0-0xFFFFFFE0>
99 */
100 #define SAU_INIT_START1 0x00200000
101
102 /*
103 // <o>End Address <0x1F-0xFFFFFFFF>
104 */
105 #define SAU_INIT_END1 0x003FFFFF
106
107 /*
108 // <o>Region is
109 // <0=>Non-Secure
110 // <1=>Secure, Non-Secure Callable
111 */
112 #define SAU_INIT_NSC1 0
113 /*
114 // </e>
115 */
116
117 /*
118 // <e>Initialize SAU Region 2
119 // <i> Setup SAU Region 2 memory attributes
120 */
121 #define SAU_INIT_REGION2 1
122
123 /*
124 // <o>Start Address <0-0xFFFFFFE0>
125 */
126 #define SAU_INIT_START2 0x20200000
127
128 /*
129 // <o>End Address <0x1F-0xFFFFFFFF>
130 */
131 #define SAU_INIT_END2 0x203FFFFF
132
133 /*
134 // <o>Region is
135 // <0=>Non-Secure
136 // <1=>Secure, Non-Secure Callable
137 */
138 #define SAU_INIT_NSC2 0
139 /*
140 // </e>
141 */
142
143 /*
144 // <e>Initialize SAU Region 3
145 // <i> Setup SAU Region 3 memory attributes
146 */
147 #define SAU_INIT_REGION3 1
148
149 /*
150 // <o>Start Address <0-0xFFFFFFE0>
151 */
152 #define SAU_INIT_START3 0x40000000
153
154 /*
155 // <o>End Address <0x1F-0xFFFFFFFF>
156 */
157 #define SAU_INIT_END3 0x40040000
158
159 /*
160 // <o>Region is
161 // <0=>Non-Secure
162 // <1=>Secure, Non-Secure Callable
163 */
164 #define SAU_INIT_NSC3 0
165 /*
166 // </e>
167 */
168
169 /*
170 // <e>Initialize SAU Region 4
171 // <i> Setup SAU Region 4 memory attributes
172 */
173 #define SAU_INIT_REGION4 0
174
175 /*
176 // <o>Start Address <0-0xFFFFFFE0>
177 */
178 #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
179
180 /*
181 // <o>End Address <0x1F-0xFFFFFFFF>
182 */
183 #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
184
185 /*
186 // <o>Region is
187 // <0=>Non-Secure
188 // <1=>Secure, Non-Secure Callable
189 */
190 #define SAU_INIT_NSC4 0
191 /*
192 // </e>
193 */
194
195 /*
196 // <e>Initialize SAU Region 5
197 // <i> Setup SAU Region 5 memory attributes
198 */
199 #define SAU_INIT_REGION5 0
200
201 /*
202 // <o>Start Address <0-0xFFFFFFE0>
203 */
204 #define SAU_INIT_START5 0x00000000
205
206 /*
207 // <o>End Address <0x1F-0xFFFFFFFF>
208 */
209 #define SAU_INIT_END5 0x00000000
210
211 /*
212 // <o>Region is
213 // <0=>Non-Secure
214 // <1=>Secure, Non-Secure Callable
215 */
216 #define SAU_INIT_NSC5 0
217 /*
218 // </e>
219 */
220
221 /*
222 // <e>Initialize SAU Region 6
223 // <i> Setup SAU Region 6 memory attributes
224 */
225 #define SAU_INIT_REGION6 0
226
227 /*
228 // <o>Start Address <0-0xFFFFFFE0>
229 */
230 #define SAU_INIT_START6 0x00000000
231
232 /*
233 // <o>End Address <0x1F-0xFFFFFFFF>
234 */
235 #define SAU_INIT_END6 0x00000000
236
237 /*
238 // <o>Region is
239 // <0=>Non-Secure
240 // <1=>Secure, Non-Secure Callable
241 */
242 #define SAU_INIT_NSC6 0
243 /*
244 // </e>
245 */
246
247 /*
248 // <e>Initialize SAU Region 7
249 // <i> Setup SAU Region 7 memory attributes
250 */
251 #define SAU_INIT_REGION7 0
252
253 /*
254 // <o>Start Address <0-0xFFFFFFE0>
255 */
256 #define SAU_INIT_START7 0x00000000
257
258 /*
259 // <o>End Address <0x1F-0xFFFFFFFF>
260 */
261 #define SAU_INIT_END7 0x00000000
262
263 /*
264 // <o>Region is
265 // <0=>Non-Secure
266 // <1=>Secure, Non-Secure Callable
267 */
268 #define SAU_INIT_NSC7 0
269 /*
270 // </e>
271 */
272
273 /*
274 // </h>
275 */
276
277 /*
278 // <e>Setup behaviour of Sleep and Exception Handling
279 */
280 #define SCB_CSR_AIRCR_INIT 1
281
282 /*
283 // <o> Deep Sleep can be enabled by
284 // <0=>Secure and Non-Secure state
285 // <1=>Secure state only
286 // <i> Value for SCB->CSR register bit DEEPSLEEPS
287 */
288 #define SCB_CSR_DEEPSLEEPS_VAL 1
289
290 /*
291 // <o>System reset request accessible from
292 // <0=> Secure and Non-Secure state
293 // <1=> Secure state only
294 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
295 */
296 #define SCB_AIRCR_SYSRESETREQS_VAL 1
297
298 /*
299 // <o>Priority of Non-Secure exceptions is
300 // <0=> Not altered
301 // <1=> Lowered to 0x80-0xFF
302 // <i> Value for SCB->AIRCR register bit PRIS
303 */
304 #define SCB_AIRCR_PRIS_VAL 1
305
306 /*
307 // <o>BusFault, HardFault, and NMI target
308 // <0=> Secure state
309 // <1=> Non-Secure state
310 // <i> Value for SCB->AIRCR register bit BFHFNMINS
311 */
312 #define SCB_AIRCR_BFHFNMINS_VAL 0
313
314 /*
315 // </e>
316 */
317
318
319 /*
320 // <e>Setup behaviour of single SysTick
321 */
322 #define SCB_ICSR_INIT 0
323
324 /*
325 // <o> in a single SysTick implementation, SysTick is
326 // <0=>Secure
327 // <1=>Non-Secure
328 // <i> Value for SCB->ICSR register bit STTNS
329 // <i> only for single SysTick implementation
330 */
331 #define SCB_ICSR_STTNS_VAL 0
332
333 /*
334 // </e>
335 */
336
337
338 /*
339 // <h>Setup Interrupt Target
340 */
341
342 /*
343 // <e>Initialize ITNS 0 (Interrupts 0..31)
344 */
345 #define NVIC_INIT_ITNS0 1
346
347 /*
348 // Interrupts 0..31
349 // <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
350 // <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
351 // <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
352 // <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
353 // <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
354 // <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
355 // <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
356 // <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
357 // <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
358 // <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
359 // <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
360 // <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
361 // <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
362 // <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
363 // <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
364 // <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
365 // <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
366 // <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
367 // <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
368 // <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
369 // <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
370 // <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
371 // <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
372 // <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
373 // <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
374 // <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
375 // <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
376 // <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
377 // <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
378 // <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
379 // <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
380 // <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
381 */
382 #define NVIC_INIT_ITNS0_VAL 0x00000000
383
384 /*
385 // </e>
386 */
387
388 /*
389 // <e>Initialize ITNS 1 (Interrupts 32..63)
390 */
391 #define NVIC_INIT_ITNS1 1
392
393 /*
394 // Interrupts 32..63
395 // <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
396 // <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
397 // <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
398 // <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
399 // <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
400 // <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
401 // <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
402 // <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
403 // <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
404 // <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
405 // <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
406 // <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
407 // <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
408 // <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
409 // <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
410 // <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
411 // <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
412 // <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
413 // <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
414 // <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
415 // <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
416 // <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
417 // <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
418 // <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
419 // <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
420 // <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
421 // <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
422 // <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
423 // <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
424 // <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
425 // <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
426 // <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
427 */
428 #define NVIC_INIT_ITNS1_VAL 0x00000000
429
430 /*
431 // </e>
432 */
433
434 /*
435 // <e>Initialize ITNS 2 (Interrupts 64..95)
436 */
437 #define NVIC_INIT_ITNS2 0
438
439 /*
440 // Interrupts 64..95
441 // <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
442 // <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
443 // <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
444 // <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
445 // <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
446 // <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
447 // <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
448 // <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
449 // <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
450 // <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
451 // <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
452 // <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
453 // <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
454 // <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
455 // <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
456 // <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
457 // <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
458 // <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
459 // <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
460 // <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
461 // <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
462 // <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
463 // <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
464 // <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
465 // <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
466 // <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
467 // <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
468 // <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
469 // <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
470 // <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
471 // <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
472 // <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
473 */
474 #define NVIC_INIT_ITNS2_VAL 0x00000000
475
476 /*
477 // </e>
478 */
479
480 /*
481 // <e>Initialize ITNS 3 (Interrupts 96..127)
482 */
483 #define NVIC_INIT_ITNS3 0
484
485 /*
486 // Interrupts 96..127
487 // <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
488 // <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
489 // <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
490 // <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
491 // <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
492 // <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
493 // <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
494 // <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
495 // <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
496 // <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
497 // <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
498 // <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
499 // <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
500 // <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
501 // <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
502 // <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
503 // <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
504 // <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
505 // <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
506 // <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
507 // <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
508 // <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
509 // <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
510 // <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
511 // <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
512 // <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
513 // <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
514 // <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
515 // <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
516 // <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
517 // <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
518 // <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
519 */
520 #define NVIC_INIT_ITNS3_VAL 0x00000000
521
522 /*
523 // </e>
524 */
525
526 /*
527 // <e>Initialize ITNS 4 (Interrupts 128..159)
528 */
529 #define NVIC_INIT_ITNS4 0
530
531 /*
532 // Interrupts 128..159
533 // <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
534 // <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
535 // <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
536 // <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
537 // <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
538 // <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
539 // <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
540 // <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
541 // <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
542 // <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
543 // <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
544 // <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
545 // <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
546 // <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
547 // <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
548 // <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
549 // <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
550 // <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
551 // <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
552 // <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
553 // <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
554 // <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
555 // <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
556 // <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
557 // <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
558 // <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
559 // <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
560 // <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
561 // <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
562 // <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
563 // <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
564 // <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
565 */
566 #define NVIC_INIT_ITNS4_VAL 0x00000000
567
568 /*
569 // </e>
570 */
571
572 /*
573 // <e>Initialize ITNS 5 (Interrupts 160..191)
574 */
575 #define NVIC_INIT_ITNS5 0
576
577 /*
578 // Interrupts 160..191
579 // <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
580 // <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
581 // <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
582 // <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
583 // <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
584 // <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
585 // <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
586 // <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
587 // <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
588 // <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
589 // <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
590 // <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
591 // <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
592 // <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
593 // <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
594 // <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
595 // <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
596 // <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
597 // <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
598 // <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
599 // <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
600 // <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
601 // <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
602 // <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
603 // <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
604 // <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
605 // <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
606 // <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
607 // <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
608 // <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
609 // <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
610 // <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
611 */
612 #define NVIC_INIT_ITNS5_VAL 0x00000000
613
614 /*
615 // </e>
616 */
617
618 /*
619 // <e>Initialize ITNS 6 (Interrupts 192..223)
620 */
621 #define NVIC_INIT_ITNS6 0
622
623 /*
624 // Interrupts 192..223
625 // <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
626 // <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
627 // <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
628 // <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
629 // <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
630 // <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
631 // <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
632 // <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
633 // <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
634 // <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
635 // <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
636 // <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
637 // <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
638 // <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
639 // <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
640 // <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
641 // <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
642 // <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
643 // <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
644 // <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
645 // <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
646 // <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
647 // <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
648 // <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
649 // <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
650 // <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
651 // <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
652 // <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
653 // <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
654 // <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
655 // <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
656 // <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
657 */
658 #define NVIC_INIT_ITNS6_VAL 0x00000000
659
660 /*
661 // </e>
662 */
663
664 /*
665 // <e>Initialize ITNS 7 (Interrupts 224..255)
666 */
667 #define NVIC_INIT_ITNS7 0
668
669 /*
670 // Interrupts 224..255
671 // <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
672 // <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
673 // <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
674 // <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
675 // <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
676 // <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
677 // <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
678 // <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
679 // <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
680 // <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
681 // <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
682 // <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
683 // <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
684 // <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
685 // <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
686 // <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
687 // <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
688 // <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
689 // <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
690 // <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
691 // <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
692 // <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
693 // <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
694 // <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
695 // <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
696 // <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
697 // <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
698 // <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
699 // <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
700 // <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
701 // <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
702 // <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
703 */
704 #define NVIC_INIT_ITNS7_VAL 0x00000000
705
706 /*
707 // </e>
708 */
709
710 /*
711 // </h>
712 */
713
714
715
716 /*
717 max 128 SAU regions.
718 SAU regions are defined in partition.h
719 */
720
721 #define SAU_INIT_REGION(n) \
722 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
723 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
724 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
725 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
726
727 /**
728 \brief Setup a SAU Region
729 \details Writes the region information contained in SAU_Region to the
730 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
731 */
TZ_SAU_Setup(void)732 __STATIC_INLINE void TZ_SAU_Setup (void)
733 {
734
735 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
736
737 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
738 SAU_INIT_REGION(0);
739 #endif
740
741 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
742 SAU_INIT_REGION(1);
743 #endif
744
745 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
746 SAU_INIT_REGION(2);
747 #endif
748
749 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
750 SAU_INIT_REGION(3);
751 #endif
752
753 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
754 SAU_INIT_REGION(4);
755 #endif
756
757 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
758 SAU_INIT_REGION(5);
759 #endif
760
761 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
762 SAU_INIT_REGION(6);
763 #endif
764
765 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
766 SAU_INIT_REGION(7);
767 #endif
768
769 /* repeat this for all possible SAU regions */
770
771 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
772
773
774 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
775 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
776 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
777 #endif
778
779 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
780 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
781 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
782
783 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
784 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
785 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
786 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
787 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
788 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
789 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
790
791 #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
792 SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
793 ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
794 #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
795
796 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
797 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
798 #endif
799
800 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
801 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
802 #endif
803
804 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
805 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
806 #endif
807
808 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
809 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
810 #endif
811
812 #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
813 NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
814 #endif
815
816 #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
817 NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
818 #endif
819
820 #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
821 NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
822 #endif
823
824 #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
825 NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
826 #endif
827
828 /* repeat this for all possible ITNS elements */
829
830 }
831
832 #endif /* PARTITION_ARMCM23_H */
833
