1 /*-----------------------------------------------------------------------------
2 * Name: CV_CoreSimd.c
3 * Purpose: CMSIS CORE validation tests implementation
4 *-----------------------------------------------------------------------------
5 * Copyright (c) 2018 Arm Limited. All rights reserved.
6 *----------------------------------------------------------------------------*/
7
8 #include "cmsis_compiler.h"
9
10 #include "CV_Framework.h"
11 #include "cmsis_cv.h"
12
13 /*-----------------------------------------------------------------------------
14 * Test implementation
15 *----------------------------------------------------------------------------*/
16
17 /*-----------------------------------------------------------------------------
18 * Test cases
19 *----------------------------------------------------------------------------*/
20
21 /**
22 \brief Test case: TC_CoreSimd_SatAddSub
23 \details
24 - Check Saturating addition and subtraction:
25 __QADD
26 __QSUB
27 */
TC_CoreSimd_SatAddSub(void)28 void TC_CoreSimd_SatAddSub (void) {
29 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
30 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
31 volatile int32_t op1_s32, op2_s32;
32 volatile int32_t res_s32;
33
34 /* --- __QADD Test ---------------------------------------------- */
35 op1_s32 = (int32_t)0x80000003;
36 op2_s32 = (int32_t)0x00000004;
37 res_s32 = __QADD(op1_s32, op2_s32);
38 ASSERT_TRUE(res_s32 == (int32_t)0x80000007);
39
40 op1_s32 = (int32_t)0x80000000;
41 op2_s32 = (int32_t)0x80000002;
42 res_s32 = __QADD(op1_s32, op2_s32);
43 ASSERT_TRUE(res_s32 == (int32_t)0x80000000);
44
45 /* --- __QSUB Test ---------------------------------------------- */
46 op1_s32 = (int32_t)0x80000003;
47 op2_s32 = (int32_t)0x00000004;
48 res_s32 = __QSUB(op1_s32, op2_s32);
49 ASSERT_TRUE(res_s32 == (int32_t)0x80000000);
50
51 op1_s32 = (int32_t)0x80000003;
52 op2_s32 = (int32_t)0x00000002;
53 res_s32 = __QSUB(op1_s32, op2_s32);
54 ASSERT_TRUE(res_s32 == (int32_t)0x80000001);
55 #endif
56 }
57
58 /**
59 \brief Test case: TC_CoreSimd_ParSat16
60 \details
61 - Check Parallel 16-bit saturation:
62 __SSAT16
63 __USAT16
64 */
TC_CoreSimd_ParSat16(void)65 void TC_CoreSimd_ParSat16 (void) {
66 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
67 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
68 volatile int32_t op1_s32;
69 volatile int32_t res_s32;
70
71 /* --- __SSAT16 Test ---------------------------------------------- */
72 op1_s32 = (int32_t)0x80030168;
73 res_s32 = __SSAT16(op1_s32, 8);
74 ASSERT_TRUE(res_s32 == (int32_t)0xFF80007F);
75
76 /* --- __USAT16 Test ---------------------------------------------- */
77 op1_s32 = 0x0030168;
78 res_s32 = __USAT16(op1_s32, 8);
79 ASSERT_TRUE(res_s32 == 0x000300FF);
80 #endif
81 }
82
83 /**
84 \brief Test case: TC_CoreSimd_PackUnpack
85 \details
86 - Check Packing and unpacking:
87 __SXTB16
88 __SXTB16_RORn
89 __SXTAB16
90 __SXTAB16__RORn
91 __UXTB16
92 __UXTAB16
93 */
TC_CoreSimd_PackUnpack(void)94 void TC_CoreSimd_PackUnpack (void) {
95 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
96 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
97 volatile int32_t op1_s32, op2_s32;
98 volatile int32_t res_s32;
99
100 /* --- __SXTB16 Test ---------------------------------------------- */
101 op1_s32 = (int32_t)0x80830168;
102 res_s32 = __SXTB16(op1_s32);
103 ASSERT_TRUE(res_s32 == (int32_t)0xFF830068);
104
105 /* --- __SXTB16_ROR8 Test ----------------------------------------- */
106 op1_s32 = (int32_t)0x80830168;
107 res_s32 = __SXTB16_RORn(op1_s32, 8);
108 ASSERT_TRUE(res_s32 == (int32_t)0xFF800001);
109
110 /* --- __SXTB16_ROR16 Test ---------------------------------------- */
111 op1_s32 = (int32_t)0x80830168;
112 res_s32 = __SXTB16_RORn(op1_s32, 16);
113 ASSERT_TRUE(res_s32 == (int32_t)0x68FF83);
114
115 /* --- __SXTB16_ROR24 Test ---------------------------------------- */
116 op1_s32 = (int32_t)0x80830168;
117 res_s32 = __SXTB16_RORn(op1_s32, 24);
118 ASSERT_TRUE(res_s32 == (int32_t)0x1FF80);
119
120 /* --- __SXTAB16 Test --------------------------------------------- */
121 op1_s32 = (int32_t)0x000D0008;
122 op2_s32 = (int32_t)0x80830168;
123 res_s32 = __SXTAB16(op1_s32, op2_s32);
124 ASSERT_TRUE(res_s32 == (int32_t)0xFF900070);
125
126 /* --- __SXTAB16__ROR8 Test --------------------------------------- */
127 op1_s32 = (int32_t)0x000A000A;
128 op2_s32 = (int32_t)0x80830168;
129 res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
130 ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B);
131
132 /* --- __SXTAB16__ROR8 Test --------------------------------------- */
133 op1_s32 = (int32_t)0xFFF6FFF6;
134 op2_s32 = (int32_t)0x80830168;
135 res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
136 ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7);
137
138 /* --- __SXTAB16__ROR16 Test -------------------------------------- */
139 op1_s32 = (int32_t)0xFFF60015;
140 op2_s32 = (int32_t)0x70880168;
141 res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16);
142 ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D);
143
144 /* --- __SXTAB16__ROR24 Test -------------------------------------- */
145 op1_s32 = (int32_t)0xFFF60015;
146 op2_s32 = (int32_t)0x70880168;
147 res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24);
148 ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085);
149
150 /* --- __UXTB16 Test ---------------------------------------------- */
151 op1_s32 = (int32_t)0x80830168;
152 res_s32 = __UXTB16(op1_s32);
153 ASSERT_TRUE(res_s32 == 0x00830068);
154
155 /* --- __UXTAB16 Test --------------------------------------------- */
156 op1_s32 = 0x000D0008;
157 op2_s32 = (int32_t)0x80830168;
158 res_s32 = __UXTAB16(op1_s32, op2_s32);
159 ASSERT_TRUE(res_s32 == 0x00900070);
160 #endif
161 }
162
163 /**
164 \brief Test case: TC_CoreSimd_ParSel
165 \details
166 - Check Parallel selection:
167 __SEL
168 */
TC_CoreSimd_ParSel(void)169 void TC_CoreSimd_ParSel (void) {
170 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
171 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
172 volatile uint32_t res_u32;
173
174 volatile int32_t op1_s32, op2_s32;
175 volatile int32_t res_s32;
176
177 APSR_Type apsr;
178 xPSR_Type xpsr;
179
180 /* --- __SEL Test ---------------------------------------------- */
181 op1_s32 = 0x33221100;
182 op2_s32 = 0x77665544;
183
184 res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */
185 res_u32 = __get_APSR();
186 apsr.w = __get_APSR();
187 ASSERT_TRUE( (res_u32 == apsr.w) );
188 xpsr.w = __get_xPSR();
189 ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
190 res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */
191 ASSERT_TRUE( res_s32 == 0x77665544);
192
193 res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */
194 res_u32 = __get_APSR();
195 apsr.w = __get_APSR();
196 ASSERT_TRUE( (res_u32 == apsr.w) );
197 xpsr.w = __get_xPSR();
198 ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
199 res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */
200 ASSERT_TRUE(res_s32 == 0x77665500);
201
202 res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */
203 res_u32 = __get_APSR();
204 apsr.w = __get_APSR();
205 ASSERT_TRUE( (res_u32 == apsr.w) );
206 xpsr.w = __get_xPSR();
207 ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
208 res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */
209 ASSERT_TRUE(res_s32 == 0x77661144);
210 #endif
211 }
212
213 /**
214 \brief Test case: TC_CoreSimd_ParAddSub8
215 \details
216 - Check Parallel 8-bit addition and subtraction:
217 __SADD8 S Signed
218 __SSUB8 Q Signed Saturating
219 __SHADD8 SH Signed Halving
220 __SHSUB8 U Unsigned
221 __QADD8 UQ Unsigned Saturating
222 __QSUB8 UH Unsigned Halving
223 __UADD8
224 __USUB8
225 __UHADD8
226 __UHSUB8
227 __UQADD8
228 __UQSUB8
229 */
TC_CoreSimd_ParAddSub8(void)230 void TC_CoreSimd_ParAddSub8 (void) {
231 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
232 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
233 volatile uint32_t op1_u32, op2_u32;
234 volatile uint32_t res_u32;
235
236 volatile int32_t op1_s32, op2_s32;
237 volatile int32_t res_s32;
238
239 /* --- __SADD8 Test ---------------------------------------------- */
240 op1_s32 = (int32_t)0x87858381;
241 op2_s32 = (int32_t)0x08060402;
242 res_s32 = __SADD8(op1_s32, op2_s32);
243 ASSERT_TRUE(res_s32 == (int32_t)0x8F8B8783);
244
245 /* --- __SSUB8 Test ---------------------------------------------- */
246 op1_s32 = (int32_t)0x8F8B8783;
247 op2_s32 = (int32_t)0x08060402;
248 res_s32 = __SSUB8(op1_s32, op2_s32);
249 ASSERT_TRUE(res_s32 == (int32_t)0x87858381);
250
251 /* --- __SHADD8 Test ---------------------------------------------- */
252 op1_s32 = 0x07050302;
253 op2_s32 = 0x08060402;
254 res_s32 = __SHADD8(op1_s32, op2_s32);
255 ASSERT_TRUE(res_s32 == 0x07050302);
256
257 /* --- __SHSUB8 Test ---------------------------------------------- */
258 op1_s32 = (int32_t)0x8F8B8783;
259 op2_s32 = 0x08060402;
260 res_s32 = __SHSUB8(op1_s32, op2_s32);
261 ASSERT_TRUE(res_s32 == (int32_t)0xC3C2C1C0);
262
263 /* --- __QADD8 Test ---------------------------------------------- */
264 op1_s32 = (int32_t)0x8085837F;
265 op2_s32 = (int32_t)0xFF060402;
266 res_s32 = __QADD8(op1_s32, op2_s32);
267 ASSERT_TRUE(res_s32 == (int32_t)0x808B877F);
268
269 /* --- __QSUB8 Test ---------------------------------------------- */
270 op1_s32 = (int32_t)0x808B8783;
271 op2_s32 = (int32_t)0x08060402;
272 res_s32 = __QSUB8(op1_s32, op2_s32);
273 ASSERT_TRUE(res_s32 == (int32_t)0x80858381);
274
275 /* --- __UADD8 Test ---------------------------------------------- */
276 op1_u32 = 0x07050301;
277 op2_u32 = 0x08060402;
278 res_u32 = __UADD8(op1_u32, op2_u32);
279 ASSERT_TRUE(res_u32 == 0x0F0B0703);
280
281 /* --- __USUB8 Test ---------------------------------------------- */
282 op1_u32 = 0x0F0B0703;
283 op2_u32 = 0x08060402;
284 res_u32 = __USUB8(op1_u32, op2_u32);
285 ASSERT_TRUE(res_u32 == 0x07050301);
286
287 /* --- __UHADD8 Test ---------------------------------------------- */
288 op1_u32 = 0x07050302;
289 op2_u32 = 0x08060402;
290 res_u32 = __UHADD8(op1_u32, op2_u32);
291 ASSERT_TRUE(res_u32 == 0x07050302);
292
293 /* --- __UHSUB8 Test ---------------------------------------------- */
294 op1_u32 = 0x0F0B0703;
295 op2_u32 = 0x08060402;
296 res_u32 = __UHSUB8(op1_u32, op2_u32);
297 ASSERT_TRUE(res_u32 == 0x03020100);
298
299 /* --- __UQADD8 Test ---------------------------------------------- */
300 op1_u32 = 0xFF050301;
301 op2_u32 = 0x08060402;
302 res_u32 = __UQADD8(op1_u32, op2_u32);
303 ASSERT_TRUE(res_u32 == 0xFF0B0703);
304
305 /* --- __UQSUB8 Test ---------------------------------------------- */
306 op1_u32 = 0x080B0702;
307 op2_u32 = 0x0F060408;
308 res_u32 = __UQSUB8(op1_u32, op2_u32);
309 ASSERT_TRUE(res_u32 == 0x00050300);
310 #endif
311 }
312
313 /**
314 \brief Test case: TC_CoreSimd_AbsDif8
315 \details
316 - Check Sum of 8-bit absolute differences:
317 __USAD8
318 __USADA8
319 */
TC_CoreSimd_AbsDif8(void)320 void TC_CoreSimd_AbsDif8 (void) {
321 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
322 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
323 volatile uint32_t op1_u32, op2_u32, op3_u32;
324 volatile uint32_t res_u32;
325
326 /* --- __USAD8 Test ---------------------------------------------- */
327 op1_u32 = 0x87858381;
328 op2_u32 = 0x08060402;
329 res_u32 = __USAD8(op1_u32, op2_u32);
330 ASSERT_TRUE(res_u32 == 0x000001FC);
331
332 /* --- __USADA8 Test ---------------------------------------------- */
333 op1_u32 = 0x87858381;
334 op2_u32 = 0x08060402;
335 op3_u32 = 0x00008000;
336 res_u32 = __USADA8(op1_u32, op2_u32, op3_u32);
337 ASSERT_TRUE(res_u32 == 0x000081FC);
338 #endif
339 }
340
341 /**
342 \brief Test case: TC_CoreSimd_ParAddSub16
343 \details
344 - Check Parallel 16-bit addition and subtraction:
345 __SADD16
346 __SSUB16
347 __SASX
348 __SSAX
349 __SHADD16
350 __SHSUB16
351 __SHASX
352 __SHSAX
353 __QADD16
354 __QSUB16
355 __QASX
356 __QSAX
357 __UADD16
358 __USUB16
359 __UASX
360 __USAX
361 __UHADD16
362 __UHSUB16
363 __UHASX
364 __UHSAX
365 __UQSUB16
366 __UQADD16
367 __UQASX
368 __UQSAX
369 */
TC_CoreSimd_ParAddSub16(void)370 void TC_CoreSimd_ParAddSub16 (void) {
371 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
372 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
373 volatile uint32_t op1_u32, op2_u32;
374 volatile uint32_t res_u32;
375
376 volatile int32_t op1_s32, op2_s32;
377 volatile int32_t res_s32;
378
379 /* --- __SADD16 Test ---------------------------------------------- */
380 op1_s32 = (int32_t)0x80038001;
381 op2_s32 = (int32_t)0x00040002;
382 res_s32 = __SADD16(op1_s32, op2_s32);
383 ASSERT_TRUE(res_s32 == (int32_t)0x80078003);
384
385 /* --- __SSUB16 Test ---------------------------------------------- */
386 op1_s32 = (int32_t)0x80078003;
387 op2_s32 = (int32_t)0x00040002;
388 res_s32 = __SSUB16(op1_s32, op2_s32);
389 ASSERT_TRUE(res_s32 == (int32_t)0x80038001);
390
391 /* --- __SASX Test ---------------------------------------------- */
392 op1_s32 = (int32_t)0x80078003;
393 op2_s32 = (int32_t)0x00040002;
394 res_s32 = __SASX(op1_s32, op2_s32);
395 ASSERT_TRUE(res_s32 == (int32_t)0x80097FFF);
396
397 /* --- __SSAX Test ---------------------------------------------- */
398 op1_s32 = (int32_t)0x80038007;
399 op2_s32 = (int32_t)0x00020004;
400 res_s32 = __SSAX(op1_s32, op2_s32);
401 ASSERT_TRUE(res_s32 == (int32_t)0x7FFF8009);
402
403 /* --- __SHADD16 Test ---------------------------------------------- */
404 op1_s32 = (int32_t)0x80038001;
405 op2_s32 = (int32_t)0x00040002;
406 res_s32 = __SHADD16(op1_s32, op2_s32);
407 ASSERT_TRUE(res_s32 == (int32_t)0xC003C001);
408
409 /* --- __SHSUB16 Test ---------------------------------------------- */
410 op1_s32 = (int32_t)0x80078003;
411 op2_s32 = (int32_t)0x00040002;
412 res_s32 = __SHSUB16(op1_s32, op2_s32);
413 ASSERT_TRUE(res_s32 == (int32_t)0xC001C000);
414
415 /* --- __SHASX Test ---------------------------------------------- */
416 op1_s32 = (int32_t)0x80078003;
417 op2_s32 = (int32_t)0x00040002;
418 res_s32 = __SHASX(op1_s32, op2_s32);
419 ASSERT_TRUE(res_s32 == (int32_t)0xC004BFFF);
420
421 /* --- __SHSAX Test ---------------------------------------------- */
422 op1_s32 = (int32_t)0x80038007;
423 op2_s32 = (int32_t)0x00020004;
424 res_s32 = __SHSAX(op1_s32, op2_s32);
425 ASSERT_TRUE(res_s32 == (int32_t)0xBFFFC004);
426
427 /* --- __QADD16 Test ---------------------------------------------- */
428 op1_s32 = (int32_t)0x80038000;
429 op2_s32 = (int32_t)0x00048002;
430 res_s32 = __QADD16(op1_s32, op2_s32);
431 ASSERT_TRUE(res_s32 == (int32_t)0x80078000);
432
433 /* --- __QSUB16 Test ---------------------------------------------- */
434 op1_s32 = (int32_t)0x80038003;
435 op2_s32 = (int32_t)0x00040002;
436 res_s32 = __QSUB16(op1_s32, op2_s32);
437 ASSERT_TRUE(res_s32 == (int32_t)0x80008001);
438
439 /* --- __QASX Test ---------------------------------------------- */
440 op1_s32 = (int32_t)0x80078003;
441 op2_s32 = (int32_t)0x00040002;
442 res_s32 = __QASX(op1_s32, op2_s32);
443 ASSERT_TRUE(res_s32 == (int32_t)0x80098000);
444
445 /* --- __QSAX Test ---------------------------------------------- */
446 op1_s32 = (int32_t)0x80038007;
447 op2_s32 = (int32_t)0x00020004;
448 res_s32 = __QSAX(op1_s32, op2_s32);
449 ASSERT_TRUE(res_s32 == (int32_t)0x80008009);
450
451 /* --- __UADD16 Test ---------------------------------------------- */
452 op1_u32 = 0x00010002;
453 op2_u32 = 0x00020004;
454 res_u32 = __UADD16(op1_u32, op2_u32);
455 ASSERT_TRUE(res_u32 == 0x00030006);
456
457 /* --- __USUB16 Test ---------------------------------------------- */
458 op1_u32 = 0x00030006;
459 op2_u32 = 0x00020004;
460 res_u32 = __USUB16(op1_u32, op2_u32);
461 ASSERT_TRUE(res_u32 == 0x00010002);
462
463 /* --- __UASX Test ---------------------------------------------- */
464 op1_u32 = 0x80078003;
465 op2_u32 = 0x00040002;
466 res_u32 = __UASX(op1_u32, op2_u32);
467 ASSERT_TRUE(res_u32 == 0x80097FFF);
468
469 /* --- __USAX Test ---------------------------------------------- */
470 op1_u32 = 0x80038007;
471 op2_u32 = 0x00020004;
472 res_u32 = __USAX(op1_u32, op2_u32);
473 ASSERT_TRUE(res_u32 == 0x7FFF8009);
474
475 /* --- __UHADD16 Test ---------------------------------------------- */
476 op1_u32 = 0x00010002;
477 op2_u32 = 0x00020004;
478 res_u32 = __UHADD16(op1_u32, op2_u32);
479 ASSERT_TRUE(res_u32 == 0x00010003);
480
481 /* --- __UHSUB16 Test ---------------------------------------------- */
482 op1_u32 = 0x00030006;
483 op2_u32 = 0x00020004;
484 res_u32 = __UHSUB16(op1_u32, op2_u32);
485 ASSERT_TRUE(res_u32 == 0x00000001);
486
487 /* --- __UHASX Test ---------------------------------------------- */
488 op1_u32 = 0x80078003;
489 op2_u32 = 0x00040002;
490 res_u32 = __UHASX(op1_u32, op2_u32);
491 ASSERT_TRUE(res_u32 == 0x40043FFF);
492
493 /* --- __UHSAX Test ---------------------------------------------- */
494 op1_u32 = 0x80038007;
495 op2_u32 = 0x00020004;
496 res_u32 = __UHSAX(op1_u32, op2_u32);
497 ASSERT_TRUE(res_u32 == 0x3FFF4004);
498
499 /* --- __UQADD16 Test ---------------------------------------------- */
500 op1_u32 = 0xFFFE0002;
501 op2_u32 = 0x00020004;
502 res_u32 = __UQADD16(op1_u32, op2_u32);
503 ASSERT_TRUE(res_u32 == 0xFFFF0006);
504
505 /* --- __UQSUB16 Test ---------------------------------------------- */
506 op1_u32 = 0x00020006;
507 op2_u32 = 0x00030004;
508 res_u32 = __UQSUB16(op1_u32, op2_u32);
509 ASSERT_TRUE(res_u32 == 0x00000002);
510
511 /* --- __UQASX Test ---------------------------------------------- */
512 op1_u32 = 0xFFF80003;
513 op2_u32 = 0x00040009;
514 res_u32 = __UQASX(op1_u32, op2_u32);
515 ASSERT_TRUE(res_u32 == 0xFFFF0000);
516
517 /* --- __UQSAX Test ---------------------------------------------- */
518 op1_u32 = 0x0003FFF8;
519 op2_u32 = 0x00090004;
520 res_u32 = __UQSAX(op1_u32, op2_u32);
521 ASSERT_TRUE(res_u32 == 0x0000FFFF);
522 #endif
523 }
524
525 /**
526 \brief Test case: TC_CoreSimd_ParMul16
527 \details
528 - Check Parallel 16-bit multiplication:
529 __SMLAD
530 __SMLADX
531 __SMLALD
532 __SMLALDX
533 __SMLSD
534 __SMLSDX
535 __SMLSLD
536 __SMLSLDX
537 __SMUAD
538 __SMUADX
539 __SMUSD
540 __SMUSDX
541 */
TC_CoreSimd_ParMul16(void)542 void TC_CoreSimd_ParMul16 (void) {
543 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
544 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
545 volatile int32_t op1_s32, op2_s32, op3_s32;
546 volatile int32_t res_s32;
547
548 volatile int64_t op1_s64;
549 volatile int64_t res_s64;
550
551 /* --- __SMLAD Test ---------------------------------------------- */
552 op1_s32 = 0x00030002;
553 op2_s32 = 0x00050004;
554 op3_s32 = 0x20000000;
555 res_s32 = __SMLAD(op1_s32, op2_s32, op3_s32);
556 ASSERT_TRUE(res_s32 == 0x20000017);
557
558 /* --- __SMLADX Test ---------------------------------------------- */
559 op1_s32 = 0x00030002;
560 op2_s32 = 0x00050004;
561 op3_s32 = 0x00000800;
562 res_s32 = __SMLADX(op1_s32, op2_s32, op3_s32);
563 ASSERT_TRUE(res_s32 == 0x00000816);
564
565 /* --- __SMLALD Test ---------------------------------------------- */
566 op1_s32 = 0x00030002;
567 op2_s32 = 0x00050004;
568 op1_s64 = 0x00000000200000000LL;
569 res_s64 = __SMLALD(op1_s32, op2_s32, op1_s64);
570 ASSERT_TRUE(res_s64 == 0x0000000200000017LL);
571
572 /* --- __SMLALDX Test ---------------------------------------------- */
573 op1_s32 = 0x00030002;
574 op2_s32 = 0x00050004;
575 op1_s64 = 0x00000000200000000LL;
576 res_s64 = __SMLALDX(op1_s32, op2_s32, op1_s64);
577 ASSERT_TRUE(res_s64 == 0x0000000200000016LL);
578
579 /* --- __SMLSD Test ---------------------------------------------- */
580 op1_s32 = 0x00030006;
581 op2_s32 = 0x00050004;
582 op3_s32 = 0x00000800;
583 res_s32 = __SMLSD(op1_s32, op2_s32, op3_s32);
584 ASSERT_TRUE(res_s32 == 0x00000809);
585
586 /* --- __SMLSDX Test ---------------------------------------------- */
587 op1_s32 = 0x00030002;
588 op2_s32 = 0x00050004;
589 op3_s32 = 0x00000800;
590 res_s32 = __SMLSDX(op1_s32, op2_s32, op3_s32);
591 ASSERT_TRUE(res_s32 == 0x000007FE);
592
593 /* --- __SMLSLD Test ---------------------------------------------- */
594 op1_s32 = 0x00030006;
595 op2_s32 = 0x00050004;
596 op1_s64 = 0x00000000200000000LL;
597 res_s64 = __SMLSLD(op1_s32, op2_s32, op1_s64);
598 ASSERT_TRUE(res_s64 == 0x0000000200000009LL);
599
600 /* --- __SMLSLDX Test ---------------------------------------------- */
601 op1_s32 = 0x00030006;
602 op2_s32 = 0x00050004;
603 op1_s64 = 0x00000000200000000LL;
604 res_s64 = __SMLSLDX(op1_s32, op2_s32, op1_s64);
605 ASSERT_TRUE(res_s64 == 0x0000000200000012LL);
606
607 /* --- __SMUAD Test ---------------------------------------------- */
608 op1_s32 = 0x00030001;
609 op2_s32 = 0x00040002;
610 res_s32 = __SMUAD(op1_s32,op2_s32);
611 ASSERT_TRUE(res_s32 == 0x0000000E);
612
613 op1_s32 = (int32_t)0xFFFDFFFF;
614 op2_s32 = (int32_t)0x00040002;
615 res_s32 = __SMUAD(op1_s32,op2_s32);
616 ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF2);
617
618 /* --- __SMUADX Test ---------------------------------------------- */
619 op1_s32 = 0x00030001;
620 op2_s32 = 0x00040002;
621 res_s32 = __SMUADX(op1_s32,op2_s32);
622 ASSERT_TRUE(res_s32 == 0x0000000A);
623
624 op1_s32 = (int32_t)0xFFFDFFFF;
625 op2_s32 = (int32_t)0x00040002;
626 res_s32 = __SMUADX(op1_s32,op2_s32);
627 ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);
628
629 /* --- __SMUSD Test ---------------------------------------------- */
630 op1_s32 = (int32_t)0x00030001;
631 op2_s32 = (int32_t)0x00040002;
632 res_s32 = __SMUSD(op1_s32,op2_s32);
633 ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);
634
635 op1_s32 = (int32_t)0xFFFDFFFF;
636 op2_s32 = (int32_t)0x00040002;
637 res_s32 = __SMUSD(op1_s32,op2_s32);
638 ASSERT_TRUE(res_s32 == 0x0000000A);
639
640 /* --- __SMUSDX Test ---------------------------------------------- */
641 op1_s32 = 0x00030001;
642 op2_s32 = 0x00040002;
643 res_s32 = __SMUSDX(op1_s32,op2_s32);
644 ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFFE);
645
646 op1_s32 = (int32_t)0xFFFDFFFF;
647 op2_s32 = (int32_t)0x00040002;
648 res_s32 = __SMUSDX(op1_s32,op2_s32);
649 ASSERT_TRUE(res_s32 == (int32_t)0x00000002);
650 #endif
651 }
652
653 /**
654 \brief Test case: TC_CoreSimd_Part9
655 \details
656 - Check Packing Halfword:
657 __PKHBT
658 __PKHTB
659 */
TC_CoreSimd_Pack16(void)660 void TC_CoreSimd_Pack16 (void) {
661 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
662 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
663 volatile uint32_t op1_u32, op2_u32;
664 volatile uint32_t res_u32;
665
666 /* --- __PKHBT Test ---------------------------------------------- */
667 op1_u32 = 0x00000111;
668 op2_u32 = 0x22200000;
669 res_u32 = __PKHBT(op1_u32, op2_u32, 0);
670 ASSERT_TRUE(res_u32 == 0x22200111);
671
672 op1_u32 = 0x00000111;
673 op2_u32 = 0x22200000;
674 res_u32 = __PKHBT(op1_u32, op2_u32, 4);
675 ASSERT_TRUE(res_u32 == 0x22000111);
676
677 /* --- __PKHTB Test ---------------------------------------------- */
678 op1_u32 = 0x11100000;
679 op2_u32 = 0x00000222;
680 res_u32 = __PKHTB(op1_u32, op2_u32, 0);
681 ASSERT_TRUE(res_u32 == 0x11100222);
682
683 op1_u32 = 0x11100000;
684 op2_u32 = 0x00000222;
685 res_u32 = __PKHTB(op1_u32, op2_u32, 4);
686 ASSERT_TRUE(res_u32 == 0x11100022);
687 #endif
688 }
689
690 /**
691 \brief Test case: TC_CoreSimd_MulAcc32
692 \details
693 - Check Signed Most Significant Word Multiply Accumulate:
694 __SMMLA
695 */
TC_CoreSimd_MulAcc32(void)696 void TC_CoreSimd_MulAcc32 (void) {
697 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
698 (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
699 volatile int32_t op1_s32, op2_s32, op3_s32;
700 volatile int32_t res_s32;
701
702 /* --- __SMMLA Test ---------------------------------------------- */
703 op1_s32 = 0x00000200;
704 op2_s32 = 0x00000004;
705 op3_s32 = 0x00000100;
706 res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);
707 ASSERT_TRUE(res_s32 == 0x00000100);
708
709 op1_s32 = 0x40000000;
710 op2_s32 = 0x00000010;
711 op3_s32 = 0x00000300;
712 res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);
713 ASSERT_TRUE(res_s32 == 0x00000304);
714 #endif
715 }
716
