1 /*-----------------------------------------------------------------------------
2  *      Name:         CV_CML1Cache.c
3  *      Purpose:      CMSIS CORE validation tests implementation
4  *-----------------------------------------------------------------------------
5  *      Copyright (c) 2020 - 2024 ARM Limited. All rights reserved.
6  *----------------------------------------------------------------------------*/
7 
8 #include "CV_Framework.h"
9 #include "cmsis_cv.h"
10 
11 /*-----------------------------------------------------------------------------
12  *      Test implementation
13  *----------------------------------------------------------------------------*/
14 
15 /*-----------------------------------------------------------------------------
16  *      Test cases
17  *----------------------------------------------------------------------------*/
18 
19 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CML1Cache_EnDisableICache(void)20 void TC_CML1Cache_EnDisableICache(void) {
21 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
22   SCB_EnableICache();
23 
24   ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == SCB_CCR_IC_Msk);
25 
26   SCB_DisableICache();
27 
28   ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == 0U);
29 #endif
30 }
31 
32 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CML1Cache_EnDisableDCache(void)33 void TC_CML1Cache_EnDisableDCache(void) {
34 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
35   SCB_EnableDCache();
36 
37   ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == SCB_CCR_DC_Msk);
38 
39   SCB_DisableDCache();
40 
41   ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);
42 #endif
43 }
44 
45 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
46 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
47 static uint32_t TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[] = { 42U, 0U, 8U, 15U };
48 #endif
49 
TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void)50 void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void) {
51 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
52   SCB_DisableDCache();
53   SCB_CleanDCache_by_Addr(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values, sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values)/sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[0]));
54   ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);
55 #endif
56 }
57