1 /*-----------------------------------------------------------------------------
2  *      Name:         CV_CAL1Cache.c
3  *      Purpose:      CMSIS CORE validation tests implementation
4  *-----------------------------------------------------------------------------
5  *      Copyright (c) 2017 ARM Limited. All rights reserved.
6  *----------------------------------------------------------------------------*/
7 
8 #include "CV_Framework.h"
9 #include "cmsis_cv.h"
10 
11 /*-----------------------------------------------------------------------------
12  *      Test implementation
13  *----------------------------------------------------------------------------*/
14 
15 /*-----------------------------------------------------------------------------
16  *      Test cases
17  *----------------------------------------------------------------------------*/
18 
19 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CAL1Cache_EnDisable(void)20 void TC_CAL1Cache_EnDisable(void) {
21 
22   uint32_t orig = __get_SCTLR();
23 
24   L1C_EnableCaches();
25 
26   uint32_t sctlr = __get_SCTLR();
27   ASSERT_TRUE((sctlr  & SCTLR_I_Msk) == SCTLR_I_Msk);
28   ASSERT_TRUE((sctlr  & SCTLR_C_Msk) == SCTLR_C_Msk);
29 
30   L1C_CleanDCacheAll();
31   L1C_DisableCaches();
32 
33   sctlr = __get_SCTLR();
34   ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U);
35   ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U);
36 
37   __set_SCTLR(orig);
38   __ISB();
39 }
40 
41 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CAL1Cache_EnDisableBTAC(void)42 void TC_CAL1Cache_EnDisableBTAC(void) {
43   uint32_t orig = __get_SCTLR();
44 
45   L1C_EnableBTAC();
46 
47   uint32_t sctlr = __get_SCTLR();
48   ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
49 
50   L1C_DisableBTAC();
51 
52   sctlr = __get_SCTLR();
53 #if __CORTEX_A == 7
54   // On Cortex-A7 SCTLR_Z is RAO/WI.
55   ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
56 #else
57   ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U);
58 #endif
59 
60   __set_SCTLR(orig);
61   __ISB();
62 }
63 
64 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CAL1Cache_log2_up(void)65 void TC_CAL1Cache_log2_up(void) {
66   uint8_t log2 = __log2_up(0U);
67   ASSERT_TRUE(log2 == 0U);
68 
69   log2 = __log2_up(1U);
70   ASSERT_TRUE(log2 == 0U);
71 
72   log2 = __log2_up(2U);
73   ASSERT_TRUE(log2 == 1U);
74 
75   log2 = __log2_up(3U);
76   ASSERT_TRUE(log2 == 2U);
77 
78   log2 = __log2_up(4U);
79   ASSERT_TRUE(log2 == 2U);
80 
81   log2 = __log2_up(0x80000000U);
82   ASSERT_TRUE(log2 == 31U);
83 
84   log2 = __log2_up(0x80000001U);
85   ASSERT_TRUE(log2 == 32U);
86 
87   log2 = __log2_up(0xFFFFFFFFU);
88   ASSERT_TRUE(log2 == 32U);
89 }
90 
91 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CAL1Cache_InvalidateDCacheAll(void)92 void TC_CAL1Cache_InvalidateDCacheAll(void) {
93 
94   /* setup */
95   uint32_t orig = __get_SCTLR();
96   volatile uint32_t value = 0x0815U;
97 
98   L1C_EnableCaches();
99 
100   L1C_CleanDCacheAll();
101 
102   /* test cached value gets lost */
103 
104   // WHEN a value is written
105   value = 0x4711U;
106 
107   // ... and the cache is invalidated
108   L1C_InvalidateDCacheAll();
109 
110   // ... and the cache is disabled
111   L1C_DisableCaches();
112 
113   // THEN the new value has been lost
114   ASSERT_TRUE(value == 0x0815U);
115 
116   /* tear down */
117   L1C_InvalidateDCacheAll();
118   __set_SCTLR(orig);
119   __ISB();
120 }
121 
122 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CAL1Cache_CleanDCacheAll(void)123 void TC_CAL1Cache_CleanDCacheAll(void) {
124   /* setup */
125   uint32_t orig = __get_SCTLR();
126   uint32_t value = 0x0815U;
127 
128   L1C_EnableCaches();
129 
130   L1C_CleanDCacheAll();
131 
132   /* test cached value is preserved */
133 
134   // WHEN a value is written
135   value = 0x4711U;
136 
137   // ... and the cache is cleaned
138   L1C_CleanDCacheAll();
139 
140   // ... and the cache is disabled
141   L1C_DisableCaches();
142 
143   // THEN the new value is preserved
144   ASSERT_TRUE(value == 0x4711U);
145 
146   /* tear down */
147   L1C_InvalidateDCacheAll();
148   __set_SCTLR(orig);
149   __ISB();
150 }
151 
152 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
TC_CAL1Cache_CleanInvalidateDCacheAll(void)153 void TC_CAL1Cache_CleanInvalidateDCacheAll(void) {
154   /* setup */
155   uint32_t orig = __get_SCTLR();
156   uint32_t value = 0x0815U;
157 
158   L1C_EnableCaches();
159 
160   L1C_CleanDCacheAll();
161 
162   /* test cached value is preserved */
163 
164   // WHEN a value is written
165   value = 0x4711U;
166 
167   // ... and the cache is cleaned/invalidated
168   L1C_CleanInvalidateDCacheAll();
169 
170   // ... and the cache is disabled
171   L1C_DisableCaches();
172 
173   // THEN the new value is preserved
174   ASSERT_TRUE(value == 0x4711U);
175 
176   /* tear down */
177   L1C_InvalidateDCacheAll();
178   __set_SCTLR(orig);
179   __ISB();
180 }
181 
182