1# -*- Python -*-
2
3import os
4
5import lit.formats
6import lit.util
7
8DEVICES = {
9    'CM0': {
10        'arch': 'thumbv6m',
11        'triple': 'thumbv6m',
12        'abi': 'eabi',
13        'mcpu': 'cortex-m0',
14        'mfpu': 'none',
15        'mpu': False,
16        'features': ['thumbv6m'],
17        'header': 'core_cm0.h',
18        'defines': {
19            '__CM0_REV': '0x0000U',
20            '__NVIC_PRIO_BITS': '2U',
21            '__Vendor_SysTickConfig': '0U'
22        }
23    },
24    'CM0plus': {
25        'arch': 'thumbv6m',
26        'triple': 'thumbv6m',
27        'abi': 'eabi',
28        'mcpu': 'cortex-m0plus',
29        'mfpu': 'none',
30        'mpu': True,
31        'features': ['thumbv6m'],
32        'header': 'core_cm0plus.h',
33        'defines': {
34            '__CM0PLUS_REV': '0x0000U',
35            '__MPU_PRESENT': '1U',
36            '__VTOR_PRESENT': '1U',
37            '__NVIC_PRIO_BITS': '2U',
38            '__Vendor_SysTickConfig': '0U'
39        }
40    },
41    'CM3': {
42        'arch': 'thumbv7m',
43        'triple': 'thumbv7-m',
44        'abi': 'eabi',
45        'mcpu': 'cortex-m3',
46        'mfpu': 'none',
47        'mpu': True,
48        'features': ['thumbv6m', 'thumbv7m', 'thumb-2', 'sat', 'ldrex', 'clz'],
49        'header': 'core_cm3.h',
50        'defines': {
51            '__CM3_REV': '0x0000U',
52            '__MPU_PRESENT': '1U',
53            '__VTOR_PRESENT': '1U',
54            '__NVIC_PRIO_BITS': '3U',
55            '__Vendor_SysTickConfig': '0U'
56        }
57    },
58    'CM4': {
59        'arch': 'thumbv7em',
60        'triple': 'thumbv7-em',
61        'abi': 'eabi',
62        'mcpu': 'cortex-m4',
63        'mfpu': 'none',
64        'mpu': True,
65        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
66        'header': 'core_cm4.h',
67        'defines': {
68            '__CM4_REV': '0x0000U',
69            '__FPU_PRESENT': '0U',
70            '__MPU_PRESENT': '1U',
71            '__VTOR_PRESENT': '1U',
72            '__NVIC_PRIO_BITS': '3U',
73            '__Vendor_SysTickConfig': '0U'
74        }
75    },
76    'CM4FP': {
77        'arch': 'thumbv7em',
78        'triple': 'thumbv7-em',
79        'abi': 'eabihf',
80        'mcpu': 'cortex-m4',
81        'mfpu': 'fpv4-sp-d16',
82        'mpu': True,
83        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
84        'header': 'core_cm4.h',
85        'defines': {
86            '__CM4_REV': '0x0000U',
87            '__FPU_PRESENT': '1U',
88            '__MPU_PRESENT': '1U',
89            '__VTOR_PRESENT': '1U',
90            '__NVIC_PRIO_BITS': '3U',
91            '__Vendor_SysTickConfig': '0U'
92        }
93    },
94    'CM7': {
95        'arch': 'thumbv7em',
96        'triple': 'thumbv7-em',
97        'abi': 'eabi',
98        'mcpu': 'cortex-m7',
99        'mfpu': 'none',
100        'mpu': True,
101        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
102        'header': 'core_cm7.h',
103        'defines': {
104            '__CM7_REV': '0x0000U',
105            '__FPU_PRESENT': '0U',
106            '__MPU_PRESENT': '1U',
107            '__ICACHE_PRESENT': '1U',
108            '__DCACHE_PRESENT': '1U',
109            '__DTCM_PRESENT': '1U',
110            '__VTOR_PRESENT': '1U',
111            '__NVIC_PRIO_BITS': '3U',
112            '__Vendor_SysTickConfig': '0U'
113        }
114    },
115    'CM7SP': {
116        'arch': 'thumbv7em',
117        'triple': 'thumbv7-em',
118        'abi': 'eabi',
119        'mcpu': 'cortex-m7',
120        'mfpu': 'fpv4-sp-d16',
121        'mpu': True,
122        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
123        'header': 'core_cm7.h',
124        'defines': {
125            '__CM7_REV': '0x0000U',
126            '__FPU_PRESENT': '1U',
127            '__MPU_PRESENT': '1U',
128            '__ICACHE_PRESENT': '1U',
129            '__DCACHE_PRESENT': '1U',
130            '__DTCM_PRESENT': '1U',
131            '__VTOR_PRESENT': '1U',
132            '__NVIC_PRIO_BITS': '3U',
133            '__Vendor_SysTickConfig': '0U'
134        }
135    },
136    'CM7DP': {
137        'arch': 'thumbv7em',
138        'triple': 'thumbv7-em',
139        'abi': 'eabihf',
140        'mcpu': 'cortex-m7',
141        'mfpu': 'fpv5-d16',
142        'mpu': True,
143        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
144        'header': 'core_cm7.h',
145        'defines': {
146            '__CM7_REV': '0x0000U',
147            '__FPU_PRESENT': '1U',
148            '__MPU_PRESENT': '1U',
149            '__ICACHE_PRESENT': '1U',
150            '__DCACHE_PRESENT': '1U',
151            '__DTCM_PRESENT': '1U',
152            '__VTOR_PRESENT': '1U',
153            '__NVIC_PRIO_BITS': '3U',
154            '__Vendor_SysTickConfig': '0U'
155        }
156    },
157    'CM23': {
158        'arch': 'thumbv8m.base',
159        'triple': 'thumbv8m',
160        'abi': 'eabi',
161        'mcpu': 'cortex-m23',
162        'mfpu': 'none',
163        'mpu': True,
164        'features': ['thumbv6m', 'thumbv7m', 'thumbv8m.base', 'ldrex'],
165        'header': 'core_cm23.h',
166        'defines': {
167            '__CM23_REV': '0x0000U',
168            '__FPU_PRESENT': '0U',
169            '__MPU_PRESENT': '1U',
170            '__SAUREGION_PRESENT': '8U',
171            '__VTOR_PRESENT': '1U',
172            '__NVIC_PRIO_BITS': '3U',
173            '__Vendor_SysTickConfig': '0U'
174        }
175    },
176    'CM23S': {
177        'arch': 'thumbv8m.base',
178        'triple': 'thumbv8m',
179        'abi': 'eabi',
180        'mcpu': 'cortex-m23',
181        'mfpu': 'none',
182        'mpu': True,
183        'features': ['thumbv6m', 'thumbv7m', 'thumbv8m.base', 'ldrex'],
184        'header': 'core_cm23.h',
185        'defines': {
186            '__CM23_REV': '0x0000U',
187            '__FPU_PRESENT': '0U',
188            '__MPU_PRESENT': '1U',
189            '__SAUREGION_PRESENT': '8U',
190            '__VTOR_PRESENT': '1U',
191            '__NVIC_PRIO_BITS': '3U',
192            '__Vendor_SysTickConfig': '0U'
193        }
194    },
195    'CM23NS': {
196        'arch': 'thumbv8m.base',
197        'triple': 'thumbv8m',
198        'abi': 'eabi',
199        'mcpu': 'cortex-m23',
200        'mfpu': 'none',
201        'mpu': True,
202        'features': ['thumbv6m', 'thumbv7m', 'thumbv8m.base', 'ldrex'],
203        'header': 'core_cm23.h',
204        'defines': {
205            '__CM23_REV': '0x0000U',
206            '__FPU_PRESENT': '0U',
207            '__MPU_PRESENT': '1U',
208            '__SAUREGION_PRESENT': '8U',
209            '__VTOR_PRESENT': '1U',
210            '__NVIC_PRIO_BITS': '3U',
211            '__Vendor_SysTickConfig': '0U'
212        }
213    },
214    'CM33': {
215        'arch': 'thumbv8m.main',
216        'triple': 'thumbv8m',
217        'abi': 'eabihf',
218        'mcpu': 'cortex-m33',
219        'mfpu': 'fpv5-d16',
220        'mpu': True,
221        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
222        'header': 'core_cm33.h',
223        'defines': {
224            '__CM33_REV': '0x0000U',
225            '__FPU_PRESENT': '1U',
226            '__MPU_PRESENT': '1U',
227            '__SAUREGION_PRESENT': '8U',
228            '__VTOR_PRESENT': '1U',
229            '__NVIC_PRIO_BITS': '3U',
230            '__Vendor_SysTickConfig': '0U'
231        }
232    },
233    'CM33S': {
234        'arch': 'thumbv8m.main',
235        'triple': 'thumbv8m',
236        'abi': 'eabihf',
237        'mcpu': 'cortex-m33',
238        'mfpu': 'fpv5-d16',
239        'mpu': True,
240        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
241        'header': 'core_cm33.h',
242        'defines': {
243            '__CM33_REV': '0x0000U',
244            '__FPU_PRESENT': '1U',
245            '__MPU_PRESENT': '1U',
246            '__SAUREGION_PRESENT': '8U',
247            '__VTOR_PRESENT': '1U',
248            '__NVIC_PRIO_BITS': '3U',
249            '__Vendor_SysTickConfig': '0U'
250        }
251    },
252    'CM33NS': {
253        'arch': 'thumbv8m.main',
254        'triple': 'thumbv8m',
255        'abi': 'eabihf',
256        'mcpu': 'cortex-m33',
257        'mfpu': 'fpv5-d16',
258        'mpu': True,
259        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
260        'header': 'core_cm33.h',
261        'defines': {
262            '__CM33_REV': '0x0000U',
263            '__FPU_PRESENT': '1U',
264            '__MPU_PRESENT': '1U',
265            '__SAUREGION_PRESENT': '8U',
266            '__VTOR_PRESENT': '1U',
267            '__NVIC_PRIO_BITS': '3U',
268            '__Vendor_SysTickConfig': '0U'
269        }
270    },
271    'CM35P': {
272        'arch': 'thumbv8m.main',
273        'triple': 'thumbv8m',
274        'abi': 'eabihf',
275        'mcpu': 'cortex-m35p',
276        'mfpu': 'fpv5-d16',
277        'mpu': True,
278        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
279        'header': 'core_cm35p.h',
280        'defines': {
281            '__CM35P_REV': '0x0000U',
282            '__FPU_PRESENT': '1U',
283            '__MPU_PRESENT': '1U',
284            '__SAUREGION_PRESENT': '8U',
285            '__VTOR_PRESENT': '1U',
286            '__NVIC_PRIO_BITS': '3U',
287            '__Vendor_SysTickConfig': '0U'
288        }
289    },
290    'CM35PS': {
291        'arch': 'thumbv8m.main',
292        'triple': 'thumbv8m',
293        'abi': 'eabihf',
294        'mcpu': 'cortex-m35p',
295        'mfpu': 'fpv5-d16',
296        'mpu': True,
297        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
298        'header': 'core_cm35p.h',
299        'defines': {
300            '__CM35P_REV': '0x0000U',
301            '__FPU_PRESENT': '1U',
302            '__MPU_PRESENT': '1U',
303            '__SAUREGION_PRESENT': '8U',
304            '__VTOR_PRESENT': '1U',
305            '__NVIC_PRIO_BITS': '3U',
306            '__Vendor_SysTickConfig': '0U'
307        }
308    },
309    'CM35PNS': {
310        'arch': 'thumbv8m.main',
311        'triple': 'thumbv8m',
312        'abi': 'eabihf',
313        'mcpu': 'cortex-m35p',
314        'mfpu': 'fpv5-d16',
315        'mpu': True,
316        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
317        'header': 'core_cm35p.h',
318        'defines': {
319            '__CM35P_REV': '0x0000U',
320            '__FPU_PRESENT': '1U',
321            '__MPU_PRESENT': '1U',
322            '__SAUREGION_PRESENT': '8U',
323            '__VTOR_PRESENT': '1U',
324            '__NVIC_PRIO_BITS': '3U',
325            '__Vendor_SysTickConfig': '0U'
326        }
327    },
328    'CM52': {
329        'arch': 'thumbv8.1m.main',
330        'triple': 'thumbv8m',
331        'abi': 'eabihf',
332        'mcpu': 'cortex-m52',
333        'mfpu': 'fpv5-d16',
334        'mpu': True,
335        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
336        'header': 'core_cm52.h',
337        'defines': {
338            '__CM52_REV': '0x0000U',
339            '__FPU_PRESENT': '1U',
340            '__FPU_DP': '1U',
341            '__MPU_PRESENT': '1U',
342            '__ICACHE_PRESENT': '1U',
343            '__DCACHE_PRESENT': '1U',
344            '__UCACHE_PRESENT': '1U',
345            '__SAUREGION_PRESENT': '8U',
346            '__DSP_PRESENT': '1U',
347            '__VTOR_PRESENT': '1U',
348            '__PMU_PRESENT': '1U',
349            '__PMU_NUM_EVENTCNT': '8U',
350            '__NVIC_PRIO_BITS': '3U',
351            '__Vendor_SysTickConfig': '0U'
352        }
353    },
354    'CM52S': {
355        'arch': 'thumbv8.1m.main',
356        'triple': 'thumbv8m',
357        'abi': 'eabihf',
358        'mcpu': 'cortex-m52',
359        'mfpu': 'fpv5-d16',
360        'mpu': True,
361        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
362        'header': 'core_cm52.h',
363        'defines': {
364            '__CM52_REV': '0x0000U',
365            '__FPU_PRESENT': '1U',
366            '__FPU_DP': '1U',
367            '__MPU_PRESENT': '1U',
368            '__ICACHE_PRESENT': '1U',
369            '__DCACHE_PRESENT': '1U',
370            '__UCACHE_PRESENT': '1U',
371            '__SAUREGION_PRESENT': '8U',
372            '__DSP_PRESENT': '1U',
373            '__VTOR_PRESENT': '1U',
374            '__PMU_PRESENT': '1U',
375            '__PMU_NUM_EVENTCNT': '8U',
376            '__NVIC_PRIO_BITS': '3U',
377            '__Vendor_SysTickConfig': '0U'
378        }
379    },
380    'CM52NS': {
381        'arch': 'thumbv8.1m.main',
382        'triple': 'thumbv8m',
383        'abi': 'eabihf',
384        'mcpu': 'cortex-m52',
385        'mfpu': 'fpv5-d16',
386        'mpu': True,
387        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
388        'header': 'core_cm52.h',
389        'defines': {
390            '__CM52_REV': '0x0000U',
391            '__FPU_PRESENT': '1U',
392            '__FPU_DP': '1U',
393            '__MPU_PRESENT': '1U',
394            '__ICACHE_PRESENT': '1U',
395            '__DCACHE_PRESENT': '1U',
396            '__UCACHE_PRESENT': '1U',
397            '__SAUREGION_PRESENT': '8U',
398            '__DSP_PRESENT': '1U',
399            '__VTOR_PRESENT': '1U',
400            '__PMU_PRESENT': '1U',
401            '__PMU_NUM_EVENTCNT': '8U',
402            '__NVIC_PRIO_BITS': '3U',
403            '__Vendor_SysTickConfig': '0U'
404        }
405    },
406    'CM55': {
407        'arch': 'thumbv8.1m.main',
408        'triple': 'thumbv8m',
409        'abi': 'eabihf',
410        'mcpu': 'cortex-m55',
411        'mfpu': 'fpv5-d16',
412        'mpu': True,
413        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
414        'header': 'core_cm55.h',
415        'defines': {
416            '__CM55_REV': '0x0000U',
417            '__FPU_PRESENT': '1U',
418            '__FPU_DP': '1U',
419            '__MPU_PRESENT': '1U',
420            '__ICACHE_PRESENT': '1U',
421            '__DCACHE_PRESENT': '1U',
422            '__SAUREGION_PRESENT': '8U',
423            '__DSP_PRESENT': '1U',
424            '__VTOR_PRESENT': '1U',
425            '__PMU_PRESENT': '1U',
426            '__PMU_NUM_EVENTCNT': '8U',
427            '__NVIC_PRIO_BITS': '3U',
428            '__Vendor_SysTickConfig': '0U'
429        }
430    },
431    'CM55S': {
432        'arch': 'thumbv8.1m.main',
433        'triple': 'thumbv8m',
434        'abi': 'eabihf',
435        'mcpu': 'cortex-m55',
436        'mfpu': 'fpv5-d16',
437        'mpu': True,
438        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
439        'header': 'core_cm55.h',
440        'defines': {
441            '__CM55_REV': '0x0000U',
442            '__FPU_PRESENT': '1U',
443            '__FPU_DP': '1U',
444            '__MPU_PRESENT': '1U',
445            '__ICACHE_PRESENT': '1U',
446            '__DCACHE_PRESENT': '1U',
447            '__SAUREGION_PRESENT': '8U',
448            '__DSP_PRESENT': '1U',
449            '__VTOR_PRESENT': '1U',
450            '__PMU_PRESENT': '1U',
451            '__PMU_NUM_EVENTCNT': '8U',
452            '__NVIC_PRIO_BITS': '3U',
453            '__Vendor_SysTickConfig': '0U'
454        }
455    },
456    'CM55NS': {
457        'arch': 'thumbv8.1m.main',
458        'triple': 'thumbv8m',
459        'abi': 'eabihf',
460        'mcpu': 'cortex-m55',
461        'mfpu': 'fpv5-d16',
462        'mpu': True,
463        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
464        'header': 'core_cm55.h',
465        'defines': {
466            '__CM55_REV': '0x0000U',
467            '__FPU_PRESENT': '1U',
468            '__FPU_DP': '1U',
469            '__MPU_PRESENT': '1U',
470            '__ICACHE_PRESENT': '1U',
471            '__DCACHE_PRESENT': '1U',
472            '__SAUREGION_PRESENT': '8U',
473            '__DSP_PRESENT': '1U',
474            '__VTOR_PRESENT': '1U',
475            '__PMU_PRESENT': '1U',
476            '__PMU_NUM_EVENTCNT': '8U',
477            '__NVIC_PRIO_BITS': '3U',
478            '__Vendor_SysTickConfig': '0U'
479        }
480    },
481    'CM85': {
482        'arch': 'thumbv8.1m.main',
483        'triple': 'thumbv8m',
484        'abi': 'eabihf',
485        'mcpu': 'cortex-m85',
486        'mfpu': 'fpv5-d16',
487        'mpu': True,
488        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
489        'header': 'core_cm85.h',
490        'defines': {
491            '__CM85_REV': '0x0000U',
492            '__FPU_PRESENT': '1U',
493            '__FPU_DP': '1U',
494            '__MPU_PRESENT': '1U',
495            '__ICACHE_PRESENT': '1U',
496            '__DCACHE_PRESENT': '1U',
497            '__SAUREGION_PRESENT': '8U',
498            '__DSP_PRESENT': '1U',
499            '__VTOR_PRESENT': '1U',
500            '__PMU_PRESENT': '1U',
501            '__PMU_NUM_EVENTCNT': '8U',
502            '__NVIC_PRIO_BITS': '3U',
503            '__Vendor_SysTickConfig': '0U'
504        }
505    },
506    'CM85S': {
507        'arch': 'thumbv8.1m.main',
508        'triple': 'thumbv8m',
509        'abi': 'eabihf',
510        'mcpu': 'cortex-m85',
511        'mfpu': 'fpv5-d16',
512        'mpu': True,
513        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
514        'header': 'core_cm85.h',
515        'defines': {
516            '__CM85_REV': '0x0000U',
517            '__FPU_PRESENT': '1U',
518            '__FPU_DP': '1U',
519            '__MPU_PRESENT': '1U',
520            '__ICACHE_PRESENT': '1U',
521            '__DCACHE_PRESENT': '1U',
522            '__SAUREGION_PRESENT': '8U',
523            '__DSP_PRESENT': '1U',
524            '__VTOR_PRESENT': '1U',
525            '__PMU_PRESENT': '1U',
526            '__PMU_NUM_EVENTCNT': '8U',
527            '__NVIC_PRIO_BITS': '3U',
528            '__Vendor_SysTickConfig': '0U'
529        }
530    },
531    'CM85NS': {
532        'arch': 'thumbv8.1m.main',
533        'triple': 'thumbv8m',
534        'abi': 'eabihf',
535        'mcpu': 'cortex-m85',
536        'mfpu': 'fpv5-d16',
537        'mpu': True,
538        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
539        'header': 'core_cm85.h',
540        'defines': {
541            '__CM85_REV': '0x0000U',
542            '__FPU_PRESENT': '1U',
543            '__FPU_DP': '1U',
544            '__MPU_PRESENT': '1U',
545            '__ICACHE_PRESENT': '1U',
546            '__DCACHE_PRESENT': '1U',
547            '__SAUREGION_PRESENT': '8U',
548            '__DSP_PRESENT': '1U',
549            '__VTOR_PRESENT': '1U',
550            '__PMU_PRESENT': '1U',
551            '__PMU_NUM_EVENTCNT': '8U',
552            '__NVIC_PRIO_BITS': '3U',
553            '__Vendor_SysTickConfig': '0U'
554        }
555    },
556    'CA5': {
557        'arch': 'armv7a',
558        'triple': 'armv7-a',
559        'abi': 'eabi',
560        'mcpu': 'cortex-a5',
561        'mfpu': 'none',
562        'mpu': True,
563        'features': ['armv7a', 'thumb-2', 'sat', 'clz'],
564        'header': 'core_ca.h',
565        'defines': {
566            '__CORTEX_A': '7',
567            '__CA_REV': '0x0000U',
568            '__FPU_PRESENT': '0U',
569            '__GIC_PRESENT': '1U',
570            '__TIM_PRESENT': '1U',
571            '__L2C_PRESENT': '1U',
572            'GIC_DISTRIBUTOR_BASE': '0x2C001000UL',
573            'GIC_INTERFACE_BASE': '0x2C000100UL',
574            'TIMER_BASE': '0x2C000600UL',
575            'L2C_310_BASE': '0x2C0F0000UL',
576            'IRQn_Type': 'int'
577        }
578    },
579    'CA5neon': {
580        'arch': 'armv7a',
581        'triple': 'armv7-a',
582        'abi': 'eabihf',
583        'mcpu': 'cortex-a5',
584        'mfpu': 'neon-vfpv4',
585        'mpu': True,
586        'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'clz'],
587        'header': 'core_ca.h',
588        'defines': {
589            '__CORTEX_A': '7',
590            '__CA_REV': '0x0000U',
591            '__FPU_PRESENT': '1U',
592            '__GIC_PRESENT': '1U',
593            '__TIM_PRESENT': '1U',
594            '__L2C_PRESENT': '1U',
595            'GIC_DISTRIBUTOR_BASE': '0x2C001000UL',
596            'GIC_INTERFACE_BASE': '0x2C000100UL',
597            'TIMER_BASE': '0x2C000600UL',
598            'L2C_310_BASE': '0x2C0F0000UL',
599            'IRQn_Type': 'int'
600        }
601    },
602    'CA7': {
603        'arch': 'armv7a',
604        'triple': 'armv7-a',
605        'abi': 'eabi',
606        'mcpu': 'cortex-a7',
607        'mfpu': 'none',
608        'mpu': True,
609        'features': ['armv7a', 'thumb-2', 'sat', 'clz'],
610        'header': 'core_ca.h',
611        'defines': {
612            '__CORTEX_A': '7',
613            '__CA_REV': '0x0000U',
614            '__FPU_PRESENT': '0U',
615            '__GIC_PRESENT': '1U',
616            '__TIM_PRESENT': '1U',
617            '__L2C_PRESENT': '1U',
618            'GIC_DISTRIBUTOR_BASE': '0x2C001000UL',
619            'GIC_INTERFACE_BASE': '0x2C000100UL',
620            'TIMER_BASE': '0x2C000600UL',
621            'L2C_310_BASE': '0x2C0F0000UL',
622            'IRQn_Type': 'int'
623        }
624    },
625    'CA7neon': {
626        'arch': 'armv7a',
627        'triple': 'armv7-a',
628        'abi': 'eabihf',
629        'mcpu': 'cortex-a7',
630        'mfpu': 'neon-vfpv4',
631        'mpu': True,
632        'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'clz'],
633        'header': 'core_ca.h',
634        'defines': {
635            '__CORTEX_A': '7',
636            '__CA_REV': '0x0000U',
637            '__FPU_PRESENT': '1U',
638            '__GIC_PRESENT': '1U',
639            '__TIM_PRESENT': '1U',
640            '__L2C_PRESENT': '1U',
641            'GIC_DISTRIBUTOR_BASE': '0x2C001000UL',
642            'GIC_INTERFACE_BASE': '0x2C000100UL',
643            'TIMER_BASE': '0x2C000600UL',
644            'L2C_310_BASE': '0x2C0F0000UL',
645            'IRQn_Type': 'int'
646        }
647    },
648    'CA9': {
649        'arch': 'armv7a',
650        'triple': 'armv7-a',
651        'abi': 'eabi',
652        'mcpu': 'cortex-a9',
653        'mfpu': 'none',
654        'mpu': True,
655        'features': ['armv7a', 'thumb-2', 'sat', 'clz'],
656        'header': 'core_ca.h',
657        'defines': {
658            '__CORTEX_A': '7',
659            '__CA_REV': '0x0000U',
660            '__FPU_PRESENT': '0U',
661            '__GIC_PRESENT': '1U',
662            '__TIM_PRESENT': '1U',
663            '__L2C_PRESENT': '1U',
664            'GIC_DISTRIBUTOR_BASE': '0x2C001000UL',
665            'GIC_INTERFACE_BASE': '0x2C000100UL',
666            'TIMER_BASE': '0x2C000600UL',
667            'L2C_310_BASE': '0x2C0F0000UL',
668            'IRQn_Type': 'int'
669        }
670    },
671    'CA9neon': {
672        'arch': 'armv7a',
673        'triple': 'armv7-a',
674        'abi': 'eabihf',
675        'mcpu': 'cortex-a9',
676        'mfpu': 'neon-vfpv3',
677        'mpu': True,
678        'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'ldrex', 'clz'],
679        'header': 'core_ca.h',
680        'defines': {
681            '__CORTEX_A': '7',
682            '__CA_REV': '0x0000U',
683            '__FPU_PRESENT': '1U',
684            '__GIC_PRESENT': '1U',
685            '__TIM_PRESENT': '1U',
686            '__L2C_PRESENT': '1U',
687            'GIC_DISTRIBUTOR_BASE': '0x2C001000UL',
688            'GIC_INTERFACE_BASE': '0x2C000100UL',
689            'TIMER_BASE': '0x2C000600UL',
690            'L2C_310_BASE': '0x2C0F0000UL',
691            'IRQn_Type': 'int'
692        }
693    }
694}
695
696# Configuration file for the 'lit' test runner.
697
698# name: The name of this test suite.
699config.name = "CMSIS-Core"
700
701# testFormat: The test format to use to interpret tests.
702#
703# For now we require '&&' between commands, until they get globally killed and
704# the test runner updated.
705config.test_format = lit.formats.ShTest()
706
707# suffixes: A list of file extensions to treat as test files.
708config.suffixes = [
709    ".c"
710]
711
712# test_source_root: The root path where tests are located.
713config.test_source_root = os.path.dirname(__file__)
714
715
716# clang_path = get_toolchain_from_env('CLANG')
717
718toolchain = lit_config.params.get("toolchain", "AC6")
719device = lit_config.params.get("device", "ARMCM3")
720optimize = lit_config.params.get("optimize", "none")
721
722class Toolchain:
723    def __init__(self, toolchain, device, optimize):
724        self._toolchain = toolchain
725        self.device = device
726        self.optimize = optimize
727
728    def get_root_from_env(self):
729        keys = sorted((k for k in os.environ.keys() if k.startswith(f'{self._toolchain}_TOOLCHAIN_')), reverse=True)
730        if not keys:
731            print(f"Toolchain '{self._toolchain}' not registered!")
732            return None
733        return os.environ.get(keys[0])
734
735    def get_root(self):
736        return self.get_root_from_env()
737
738
739class Toolchain_AC6(Toolchain):
740    OPTIMIZE = {
741        'none': '-O1',
742        'balanced': '-O3',
743        'speed': '-Os',
744        'size': '-Oz'
745    }
746
747    def __init__(self, **args):
748        super().__init__('AC6', **args)
749
750    def get_cc(self):
751        return os.path.join(self.get_root(), 'armclang')
752
753    def get_ccflags(self):
754        ccflags = [
755            '--target=arm-arm-none-eabi', f'-mcpu={DEVICES[self.device]["mcpu"]}', f'-mfpu={DEVICES[self.device]["mfpu"]}',
756            self.OPTIMIZE[self.optimize], '-I', os.path.abspath('../Include'), '-c', '-D', f'CORE_HEADER="{DEVICES[device]["header"]}"']
757        if device.endswith('S') and not device.endswith('NS'):
758            ccflags += ["-mcmse"]
759        ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ()))
760        return ccflags
761
762
763class Toolchain_GCC(Toolchain):
764    OPTIMIZE = {
765        'none': '-O1',
766        'balanced': '-O3',
767        'speed': '-Os',
768        'size': '-Oz'
769    }
770
771    def __init__(self, **args):
772        super().__init__('GCC', **args)
773
774    def get_cc(self):
775        return os.path.join(self.get_root(), 'arm-none-eabi-gcc')
776
777    def get_ccflags(self):
778        floatabi='soft'
779        if DEVICES[self.device]["mfpu"] != 'none':
780            floatabi='hard'
781        ccflags = [
782            f'-mcpu={DEVICES[self.device]["mcpu"]}', f'-mfloat-abi={floatabi}',
783            self.OPTIMIZE[self.optimize], '-I', os.path.abspath('../Include'),
784            '-D', f'CORE_HEADER="{DEVICES[device]["header"]}"', '-c']
785        if DEVICES[self.device]["mfpu"] != "none":
786            ccflags += [f'-mfpu={DEVICES[self.device]["mfpu"]}']
787        if device.endswith('S') and not device.endswith('NS'):
788            ccflags += ["-mcmse"]
789        ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ()))
790        return ccflags
791
792class Toolchain_Clang(Toolchain):
793    TARGET = {
794        'CM0': 'thumbv6m-none-unknown-eabi',
795        'CM0plus': 'thumbv6m-none-unknown-eabi',
796        'CM3': 'thumbv7m-none-unknown-eabi',
797        'CM4': 'thumbv7em-none-unknown-eabi',
798        'CM4FP': 'thumbv7em-none-unknown-eabihf',
799        'CM7': 'thumbv7em-none-unknown-eabi',
800        'CM7SP': 'thumbv7em-none-unknown-eabihf',
801        'CM7DP': 'thumbv7em-none-unknown-eabihf',
802        'CM23': 'thumbv8m.base-none-unknown-eabi',
803        'CM23S': 'thumbv8m.base-none-unknown-eabi',
804        'CM23NS': 'thumbv8m.base-none-unknown-eabi',
805        'CM33': 'thumbv8m.main-none-unknown-eabihf',
806        'CM33S': 'thumbv8m.main-none-unknown-eabihf',
807        'CM33NS': 'thumbv8m.main-none-unknown-eabihf',
808        'CM35P': 'thumbv8m.main-none-unknown-eabihf',
809        'CM35PS': 'thumbv8m.main-none-unknown-eabihf',
810        'CM35PNS': 'thumbv8m.main-none-unknown-eabihf',
811        'CM52': 'thumbv8.1m.main-none-unknown-eabihf',
812        'CM52S': 'thumbv8.1m.main-none-unknown-eabihf',
813        'CM52NS': 'thumbv8.1m.main-none-unknown-eabihf',
814        'CM55': 'thumbv8.1m.main-none-unknown-eabihf',
815        'CM55S': 'thumbv8.1m.main-none-unknown-eabihf',
816        'CM55NS': 'thumbv8.1m.main-none-unknown-eabihf',
817        'CM85': 'thumbv8.1m.main-none-unknown-eabihf',
818        'CM85S': 'thumbv8.1m.main-none-unknown-eabihf',
819        'CM85NS': 'thumbv8.1m.main-none-unknown-eabihf',
820        'CA5': 'armv7-none-unknown-eabi',
821        'CA5neon': 'armv7-none-unknown-eabihf',
822        'CA7': 'armv7-none-unknown-eabi',
823        'CA7neon': 'armv7-none-unknown-eabihf',
824        'CA9': 'armv7-none-unknown-eabi',
825        'CA9neon': 'armv7-none-unknown-eabihf'
826    }
827    OPTIMIZE = {
828        'none': '-O1',
829        'balanced': '-O3',
830        'speed': '-Os',
831        'size': '-Oz'
832    }
833    def __init__(self, **args):
834        super().__init__('CLANG', **args)
835
836    def get_cc(self):
837        return os.path.join(self.get_root(), 'clang')
838
839    def get_ccflags(self):
840        ccflags = [
841            f'--target={self.TARGET[self.device]}', self.OPTIMIZE[self.optimize],
842            f'-mcpu={DEVICES[self.device]["mcpu"]}', f'-mfpu={DEVICES[self.device]["mfpu"]}',
843            '-I', os.path.abspath('../Include'), '-c', '-D', f'CORE_HEADER="{DEVICES[device]["header"]}"']
844        if device.endswith('S') and not device.endswith('NS'):
845            ccflags += ["-mcmse"]
846        ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ()))
847
848        return ccflags
849
850tc = None
851if toolchain == 'AC6':
852    tc = Toolchain_AC6(device=device, optimize=optimize)
853elif toolchain == 'GCC':
854    tc = Toolchain_GCC(device=device, optimize=optimize)
855elif toolchain == 'Clang':
856    tc = Toolchain_Clang(device=device, optimize=optimize)
857
858prefixes = ['CHECK']
859if device.endswith('NS'):
860    prefixes += ['CHECK-NS']
861elif device.endswith('S'):
862    prefixes += ['CHECK-S']
863if DEVICES[device]['arch'].startswith('thumb'):
864    prefixes += ['CHECK-THUMB']
865elif DEVICES[device]['arch'].startswith('arm'):
866    prefixes += ['CHECK-ARM']
867
868if DEVICES[device]["mfpu"] != 'none':
869    config.available_features.add('fpu')
870for feature in DEVICES[device]['features']:
871    config.available_features.add(feature)
872
873objdump = os.path.join(Toolchain("CLANG", "none", "none").get_root(), 'llvm-objdump')
874config.substitutions.append(("llvm-objdump", objdump))
875
876config.substitutions.append(("%ccout%", "-o"))
877config.substitutions.append(("%cc%", tc.get_cc()))
878config.substitutions.append(("%ccflags%", ' '.join(tc.get_ccflags())))
879config.substitutions.append(("%prefixes%", ','.join(prefixes)))
880config.substitutions.append(("%triple%", DEVICES[device]['triple']))
881config.substitutions.append(("%mcpu%", DEVICES[device]['mcpu']))
882