1 /**************************************************************************//** 2 * @file <Device>.h 3 * @brief CMSIS-Core(M) Device Header File for Device <Device> 4 * 5 * @version V1.0.0 6 * @date 18. July 2023 7 ******************************************************************************/ 8 /* 9 * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 /* ToDo: rename this file from Device.h to '<Device>.h according to your device name */ 27 28 #ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */ 29 #define <Device>_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 36 /* ========================================================================= */ 37 /* ============ Interrupt Number Definition ============ */ 38 /* ========================================================================= */ 39 40 typedef enum IRQn 41 { 42 /* ================ Cortex-M Core Exception Numbers ================ */ 43 44 /* ToDo: add Cortex exception numbers according the used Cortex-Core */ 45 Reset_IRQn = -15, /* 1 Reset Vector 46 invoked on Power up and warm reset */ 47 NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt 48 cannot be stopped or preempted */ 49 HardFault_IRQn = -13, /* 3 Hard Fault 50 all classes of Fault */ 51 MemoryManagement_IRQn = -12, /* 4 Memory Management 52 MPU mismatch, including Access Violation and No Match */ 53 BusFault_IRQn = -11, /* 5 Bus Fault 54 Pre-Fetch-, Memory Access, other address/memory Fault */ 55 UsageFault_IRQn = -10, /* 6 Usage Fault 56 i.e. Undef Instruction, Illegal State Transition */ 57 SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ 58 SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ 59 DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ 60 PendSV_IRQn = -2, /* 14 Pendable request for system service */ 61 SysTick_IRQn = -1, /* 15 System Tick Timer */ 62 63 /* ================ <Device> Interrupt Numbers ================ */ 64 /* ToDo: Add here your device specific interrupt numbers 65 according the interrupt handlers defined in startup_Device.s 66 eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ 67 <DeviceInterrupt first>_IRQn = 0, /* first Device Interrupt*/ 68 ... 69 <DeviceInterrupt last>_IRQn = n /* last Device Interrupt */ 70 } IRQn_Type; 71 72 73 /* ========================================================================= */ 74 /* ============ Processor and Core Peripheral Section ============ */ 75 /* ========================================================================= */ 76 77 /* ================ Start of section using anonymous unions ================ */ 78 #if defined (__CC_ARM) 79 #pragma push 80 #pragma anon_unions 81 #elif defined (__ICCARM__) 82 #pragma language=extended 83 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 84 #pragma clang diagnostic push 85 #pragma clang diagnostic ignored "-Wc11-extensions" 86 #pragma clang diagnostic ignored "-Wreserved-id-macro" 87 #elif defined (__GNUC__) 88 /* anonymous unions are enabled by default */ 89 #elif defined (__TMS470__) 90 /* anonymous unions are enabled by default */ 91 #elif defined (__TASKING__) 92 #pragma warning 586 93 #elif defined (__CSMC__) 94 /* anonymous unions are enabled by default */ 95 #else 96 #warning Not supported compiler type 97 #endif 98 99 100 /* -------- Configuration of Core Peripherals ----------------------------------- */ 101 /* ToDo: set the defines according your Device */ 102 /* ToDo: define the correct core revision 103 valid CMSIS core revision macro names are: 104 __CM0_REV, __CM0PLUS_REV, __CM1_REV, __CM3_REV, __CM4_REV, __CM7_REV 105 __CM23_REV, __CM33_REV, __CM35P_REV, __CM55_REV 106 __SC000_REV, __SC300_REV */ 107 #define __CM#_REV 0x0201U /* Core Revision r2p1 */ 108 /* ToDo: define the correct core features for the <Device> */ 109 #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ 110 #define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ 111 #define __VTOR_PRESENT 1U /* Set to 1 if VTOR is present */ 112 #define __MPU_PRESENT 1U /* Set to 1 if MPU is present */ 113 #define __FPU_PRESENT 0U /* Set to 1 if FPU is present */ 114 #define __FPU_DP 0U /* Set to 1 if FPU is double precision FPU (default is single precision FPU) */ 115 #define __DSP_PRESENT 1U /* Set to 1 if DSP extension are present */ 116 #define __SAUREGION_PRESENT 1U /* Set to 1 if SAU regions are present */ 117 #define __PMU_PRESENT 1U /* Set to 1 if PMU is present */ 118 #define __PMU_NUM_EVENTCNT 8U /* Set number of PMU Event Counters */ 119 #define __ICACHE_PRESENT 0U /* Set to 1 if I-Cache is present */ 120 #define __DCACHE_PRESENT 0U /* Set to 1 if D-Cache is present */ 121 #define __DTCM_PRESENT 0U /* Set to 1 if DTCM is present */ 122 123 124 /* ToDo: include the CMSIS core header file according your device. 125 valid CMSIS core header files are: 126 core_cm0.h, core_cm0plus.h, core_cm1.h, core_cm3.h, core_cm4.h, core_cm7.h 127 core_cm23.h, core_cm33.h, core_cm35p.h, core_cm55.h 128 core_sc000.h, core_sc300.h */ 129 #include <core_cm#.h> /* Processor and core peripherals */ 130 /* ToDo: include your system_<Device>.h file 131 replace '<Device>' with your device name */ 132 #include "system_<Device>.h" /* System Header */ 133 134 135 136 /* ========================================================================= */ 137 /* ============ Device Specific Peripheral Section ============ */ 138 /* ========================================================================= */ 139 140 141 /* ToDo: add here your device specific peripheral access structure typedefs 142 including bit definitions for Pos/Msk macros 143 following is an example for a timer */ 144 145 /* ========================================================================= */ 146 /* ============ TMR ============ */ 147 /* ========================================================================= */ 148 149 typedef struct 150 { 151 __IOM uint32_t LOAD; /* Offset: 0x000 (R/W) Load Register */ 152 __IM uint32_t VALUE; /* Offset: 0x004 (R/ ) Value Register */ 153 __IOM uint32_t CONTROL; /* Offset: 0x008 (R/W) Control Register */ 154 __OM uint32_t INTCLR; /* Offset: 0x00C ( /W) Clear Interrupt Register */ 155 __IM uint32_t RIS; /* Offset: 0x010 (R/ ) Raw Interrupt Status Register */ 156 __IM uint32_t MIS; /* Offset: 0x014 (R/ ) Interrupt Status Register */ 157 __IOM uint32_t BGLOAD; /* Offset: 0x018 (R/W) Background Load Register */ 158 } <DeviceAbbreviation>_TMR_TypeDef; 159 160 /* <DeviceAbbreviation>_TMR LOAD Register Definitions */ 161 #define <DeviceAbbreviation>_TMR_LOAD_Pos 0 162 #define <DeviceAbbreviation>_TMR_LOAD_Msk (0xFFFFFFFFUL /*<< <DeviceAbbreviation>_TMR_LOAD_Pos*/) 163 164 /* <DeviceAbbreviation>_TMR VALUE Register Definitions */ 165 #define <DeviceAbbreviation>_TMR_VALUE_Pos 0 166 #define <DeviceAbbreviation>_TMR_VALUE_Msk (0xFFFFFFFFUL /*<< <DeviceAbbreviation>_TMR_VALUE_Pos*/) 167 168 /* <DeviceAbbreviation>_TMR CONTROL Register Definitions */ 169 #define <DeviceAbbreviation>_TMR_CONTROL_SIZE_Pos 1 170 #define <DeviceAbbreviation>_TMR_CONTROL_SIZE_Msk (1UL << <DeviceAbbreviation>_TMR_CONTROL_SIZE_Pos) 171 172 #define <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Pos 0 173 #define <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Msk (1UL /*<< <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Pos*/) 174 175 176 177 /* -------- End of section using anonymous unions and disabling warnings -------- */ 178 #if defined (__CC_ARM) 179 #pragma pop 180 #elif defined (__ICCARM__) 181 /* leave anonymous unions enabled */ 182 #elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 183 #pragma clang diagnostic pop 184 #elif defined (__GNUC__) 185 /* anonymous unions are enabled by default */ 186 #elif defined (__TMS470__) 187 /* anonymous unions are enabled by default */ 188 #elif defined (__TASKING__) 189 #pragma warning restore 190 #elif defined (__CSMC__) 191 /* anonymous unions are enabled by default */ 192 #else 193 #warning Not supported compiler type 194 #endif 195 196 197 /* ========================================================================= */ 198 /* ============ Device Specific Peripheral Address Map ============ */ 199 /* ========================================================================= */ 200 201 202 /* ToDo: add here your device peripherals base addresses 203 following is an example for timer */ 204 205 /* Peripheral and SRAM base address */ 206 #define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /* (FLASH ) Base Address */ 207 #define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /* (SRAM ) Base Address */ 208 #define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /* (Peripheral) Base Address */ 209 210 /* Peripheral memory map */ 211 #define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /* (Timer0 ) Base Address */ 212 #define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /* (Timer1 ) Base Address */ 213 #define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /* (Timer2 ) Base Address */ 214 215 216 /* ========================================================================= */ 217 /* ============ Peripheral declaration ============ */ 218 /* ========================================================================= */ 219 220 221 /* ToDo: Add here your device peripherals pointer definitions 222 following is an example for timer */ 223 224 #define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) 225 #define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) 226 #define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) 227 228 #ifdef __cplusplus 229 } 230 #endif 231 232 #endif /* <Device>_H */ 233
