1 /*
2 * Copyright (c) 2023-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS-Core(M) Compiler TIARMClang Header File
21 */
22
23 #ifndef __CMSIS_TIARMCLANG_M_H
24 #define __CMSIS_TIARMCLANG_M_H
25
26 #pragma clang system_header /* treat file as system include file */
27
28 #if (__ARM_ACLE >= 200)
29 #include <arm_acle.h>
30 #else
31 #error Compiler must support ACLE V2.0
32 #endif /* (__ARM_ACLE >= 200) */
33
34 /* CMSIS compiler specific defines */
35 #ifndef __ASM
36 #define __ASM __asm
37 #endif
38 #ifndef __INLINE
39 #define __INLINE __inline
40 #endif
41 #ifndef __STATIC_INLINE
42 #define __STATIC_INLINE static __inline
43 #endif
44 #ifndef __STATIC_FORCEINLINE
45 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
46 #endif
47 #ifndef __NO_RETURN
48 #define __NO_RETURN __attribute__((__noreturn__))
49 #endif
50 #ifndef __USED
51 #define __USED __attribute__((used))
52 #endif
53 #ifndef __WEAK
54 #define __WEAK __attribute__((weak))
55 #endif
56 #ifndef __PACKED
57 #define __PACKED __attribute__((packed, aligned(1)))
58 #endif
59 #ifndef __PACKED_STRUCT
60 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
61 #endif
62 #ifndef __PACKED_UNION
63 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
64 #endif
65 #ifndef __UNALIGNED_UINT16_WRITE
66 #pragma clang diagnostic push
67 #pragma clang diagnostic ignored "-Wpacked"
68 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
69 #pragma clang diagnostic pop
70 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
71 #endif
72 #ifndef __UNALIGNED_UINT16_READ
73 #pragma clang diagnostic push
74 #pragma clang diagnostic ignored "-Wpacked"
75 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
76 #pragma clang diagnostic pop
77 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
78 #endif
79 #ifndef __UNALIGNED_UINT32_WRITE
80 #pragma clang diagnostic push
81 #pragma clang diagnostic ignored "-Wpacked"
82 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
83 #pragma clang diagnostic pop
84 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
85 #endif
86 #ifndef __UNALIGNED_UINT32_READ
87 #pragma clang diagnostic push
88 #pragma clang diagnostic ignored "-Wpacked"
89 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
90 #pragma clang diagnostic pop
91 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
92 #endif
93 #ifndef __ALIGNED
94 #define __ALIGNED(x) __attribute__((aligned(x)))
95 #endif
96 #ifndef __RESTRICT
97 #define __RESTRICT __restrict
98 #endif
99 #ifndef __COMPILER_BARRIER
100 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
101 #endif
102 #ifndef __NO_INIT
103 #define __NO_INIT __attribute__ ((section (".noinit")))
104 #endif
105 #ifndef __ALIAS
106 #define __ALIAS(x) __attribute__ ((alias(x)))
107 #endif
108
109
110 /* ######################### Startup and Lowlevel Init ######################## */
111 #ifndef __PROGRAM_START
112 #define __PROGRAM_START _c_int00
113 #endif
114
115 #ifndef __INITIAL_SP
116 #define __INITIAL_SP __STACK_END
117 #endif
118
119 #ifndef __STACK_LIMIT
120 #define __STACK_LIMIT __STACK_SIZE
121 #endif
122
123 #ifndef __VECTOR_TABLE
124 #define __VECTOR_TABLE __Vectors
125 #endif
126
127 #ifndef __VECTOR_TABLE_ATTRIBUTE
128 #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs")))
129 #endif
130
131 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
132 #ifndef __STACK_SEAL
133 #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
134 #endif
135
136 #ifndef __TZ_STACK_SEAL_SIZE
137 #define __TZ_STACK_SEAL_SIZE 8U
138 #endif
139
140 #ifndef __TZ_STACK_SEAL_VALUE
141 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
142 #endif
143
__TZ_set_STACKSEAL_S(uint32_t * stackTop)144 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
145 {
146 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
147 }
148 #endif
149
150
151 /* ########################## Core Instruction Access ######################### */
152 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
153 Access to dedicated instructions
154 @{
155 */
156
157 /* Define macros for porting to both thumb1 and thumb2.
158 * For thumb1, use low register (r0-r7), specified by constraint "l"
159 * Otherwise, use general registers, specified by constraint "r" */
160 #if defined (__thumb__) && !defined (__thumb2__)
161 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
162 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
163 #define __CMSIS_GCC_USE_REG(r) "l" (r)
164 #else
165 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
166 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
167 #define __CMSIS_GCC_USE_REG(r) "r" (r)
168 #endif
169
170 /**
171 \brief No Operation
172 \details No Operation does nothing. This instruction can be used for code alignment purposes.
173 */
174 #define __NOP() __nop()
175
176
177 /**
178 \brief Wait For Interrupt
179 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
180 */
181 #define __WFI() __wfi()
182
183
184 /**
185 \brief Wait For Event
186 \details Wait For Event is a hint instruction that permits the processor to enter
187 a low-power state until one of a number of events occurs.
188 */
189 #define __WFE() __wfe()
190
191
192 /**
193 \brief Send Event
194 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
195 */
196 #define __SEV() __sev()
197
198
199 /**
200 \brief Instruction Synchronization Barrier
201 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
202 so that all instructions following the ISB are fetched from cache or memory,
203 after the instruction has been completed.
204 */
205 #define __ISB() __isb(0xF)
206
207
208 /**
209 \brief Data Synchronization Barrier
210 \details Acts as a special kind of Data Memory Barrier.
211 It completes when all explicit memory accesses before this instruction complete.
212 */
213 #define __DSB() __dsb(0xF)
214
215
216 /**
217 \brief Data Memory Barrier
218 \details Ensures the apparent order of the explicit memory operations before
219 and after the instruction, without ensuring their completion.
220 */
221 #define __DMB() __dmb(0xF)
222
223
224 /**
225 \brief Reverse byte order (32 bit)
226 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
227 \param [in] value Value to reverse
228 \return Reversed value
229 */
230 #define __REV(value) __rev(value)
231
232
233 /**
234 \brief Reverse byte order (16 bit)
235 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
236 \param [in] value Value to reverse
237 \return Reversed value
238 */
239 #define __REV16(value) __rev16(value)
240
241
242 /**
243 \brief Reverse byte order (16 bit)
244 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
245 \param [in] value Value to reverse
246 \return Reversed value
247 */
248 #define __REVSH(value) __revsh(value)
249
250
251 /**
252 \brief Rotate Right in unsigned value (32 bit)
253 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
254 \param [in] op1 Value to rotate
255 \param [in] op2 Number of Bits to rotate
256 \return Rotated value
257 */
258 #define __ROR(op1, op2) __ror(op1, op2)
259
260
261 /**
262 \brief Breakpoint
263 \details Causes the processor to enter Debug state.
264 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
265 \param [in] value is ignored by the processor.
266 If required, a debugger can use it to store additional information about the breakpoint.
267 */
268 #define __BKPT(value) __ASM volatile ("bkpt "#value)
269
270
271 /**
272 \brief Reverse bit order of value
273 \details Reverses the bit order of the given value.
274 \param [in] value Value to reverse
275 \return Reversed value
276 */
277 #define __RBIT(value) __rbit(value)
278
279
280 /**
281 \brief Count leading zeros
282 \details Counts the number of leading zeros of a data value.
283 \param [in] value Value to count the leading zeros
284 \return number of leading zeros in value
285 */
286 #define __CLZ(value) __clz(value)
287
288
289 /* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */
290 #if ((__ARM_FEATURE_SAT >= 1) && \
291 (__ARM_ARCH_ISA_THUMB >= 2) )
292 /**
293 \brief Signed Saturate
294 \details Saturates a signed value.
295 \param [in] value Value to be saturated
296 \param [in] sat Bit position to saturate to (1..32)
297 \return Saturated value
298 */
299 #define __SSAT(value, sat) __ssat(value, sat)
300
301
302 /**
303 \brief Unsigned Saturate
304 \details Saturates an unsigned value.
305 \param [in] value Value to be saturated
306 \param [in] sat Bit position to saturate to (0..31)
307 \return Saturated value
308 */
309 #define __USAT(value, sat) __usat(value, sat)
310
311 #else /* (__ARM_FEATURE_SAT >= 1) */
312 /**
313 \brief Signed Saturate
314 \details Saturates a signed value.
315 \param [in] value Value to be saturated
316 \param [in] sat Bit position to saturate to (1..32)
317 \return Saturated value
318 */
__SSAT(int32_t val,uint32_t sat)319 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
320 {
321 if ((sat >= 1U) && (sat <= 32U))
322 {
323 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
324 const int32_t min = -1 - max ;
325 if (val > max)
326 {
327 return (max);
328 }
329 else if (val < min)
330 {
331 return (min);
332 }
333 }
334 return (val);
335 }
336
337
338 /**
339 \brief Unsigned Saturate
340 \details Saturates an unsigned value.
341 \param [in] value Value to be saturated
342 \param [in] sat Bit position to saturate to (0..31)
343 \return Saturated value
344 */
__USAT(int32_t val,uint32_t sat)345 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
346 {
347 if (sat <= 31U)
348 {
349 const uint32_t max = ((1U << sat) - 1U);
350 if (val > (int32_t)max)
351 {
352 return (max);
353 }
354 else if (val < 0)
355 {
356 return (0U);
357 }
358 }
359 return ((uint32_t)val);
360 }
361 #endif /* (__ARM_FEATURE_SAT >= 1) */
362
363
364 #if (__ARM_FEATURE_LDREX >= 1)
365 /**
366 \brief Remove the exclusive lock
367 \details Removes the exclusive lock which is created by LDREX.
368 */
369 #define __CLREX __builtin_arm_clrex
370
371
372 /**
373 \brief LDR Exclusive (8 bit)
374 \details Executes a exclusive LDR instruction for 8 bit value.
375 \param [in] ptr Pointer to data
376 \return value of type uint8_t at (*ptr)
377 */
378 #define __LDREXB (uint8_t)__builtin_arm_ldrex
379
380
381 /**
382 \brief STR Exclusive (8 bit)
383 \details Executes a exclusive STR instruction for 8 bit values.
384 \param [in] value Value to store
385 \param [in] ptr Pointer to location
386 \return 0 Function succeeded
387 \return 1 Function failed
388 */
389 #define __STREXB (uint32_t)__builtin_arm_strex
390 #endif /* (__ARM_FEATURE_LDREX >= 1) */
391
392
393 #if (__ARM_FEATURE_LDREX >= 2)
394 /**
395 \brief LDR Exclusive (16 bit)
396 \details Executes a exclusive LDR instruction for 16 bit values.
397 \param [in] ptr Pointer to data
398 \return value of type uint16_t at (*ptr)
399 */
400 #define __LDREXH (uint16_t)__builtin_arm_ldrex
401
402
403 /**
404 \brief STR Exclusive (16 bit)
405 \details Executes a exclusive STR instruction for 16 bit values.
406 \param [in] value Value to store
407 \param [in] ptr Pointer to location
408 \return 0 Function succeeded
409 \return 1 Function failed
410 */
411 #define __STREXH (uint32_t)__builtin_arm_strex
412 #endif /* (__ARM_FEATURE_LDREX >= 2) */
413
414
415 #if (__ARM_FEATURE_LDREX >= 4)
416 /**
417 \brief LDR Exclusive (32 bit)
418 \details Executes a exclusive LDR instruction for 32 bit values.
419 \param [in] ptr Pointer to data
420 \return value of type uint32_t at (*ptr)
421 */
422 #define __LDREXW (uint32_t)__builtin_arm_ldrex
423
424
425 /**
426 \brief STR Exclusive (32 bit)
427 \details Executes a exclusive STR instruction for 32 bit values.
428 \param [in] value Value to store
429 \param [in] ptr Pointer to location
430 \return 0 Function succeeded
431 \return 1 Function failed
432 */
433 #define __STREXW (uint32_t)__builtin_arm_strex
434 #endif /* (__ARM_FEATURE_LDREX >= 4) */
435
436
437 #if (__ARM_ARCH_ISA_THUMB >= 2)
438 /**
439 \brief Rotate Right with Extend (32 bit)
440 \details Moves each bit of a bitstring right by one bit.
441 The carry input is shifted in at the left end of the bitstring.
442 \param [in] value Value to rotate
443 \return Rotated value
444 */
__RRX(uint32_t value)445 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
446 {
447 uint32_t result;
448
449 __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
450 return (result);
451 }
452
453
454 /**
455 \brief LDRT Unprivileged (8 bit)
456 \details Executes a Unprivileged LDRT instruction for 8 bit value.
457 \param [in] ptr Pointer to data
458 \return value of type uint8_t at (*ptr)
459 */
__LDRBT(volatile uint8_t * ptr)460 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
461 {
462 uint32_t result;
463
464 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
465 return ((uint8_t)result); /* Add explicit type cast here */
466 }
467
468
469 /**
470 \brief LDRT Unprivileged (16 bit)
471 \details Executes a Unprivileged LDRT instruction for 16 bit values.
472 \param [in] ptr Pointer to data
473 \return value of type uint16_t at (*ptr)
474 */
__LDRHT(volatile uint16_t * ptr)475 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
476 {
477 uint32_t result;
478
479 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
480 return ((uint16_t)result); /* Add explicit type cast here */
481 }
482
483
484 /**
485 \brief LDRT Unprivileged (32 bit)
486 \details Executes a Unprivileged LDRT instruction for 32 bit values.
487 \param [in] ptr Pointer to data
488 \return value of type uint32_t at (*ptr)
489 */
__LDRT(volatile uint32_t * ptr)490 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
491 {
492 uint32_t result;
493
494 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
495 return (result);
496 }
497
498
499 /**
500 \brief STRT Unprivileged (8 bit)
501 \details Executes a Unprivileged STRT instruction for 8 bit values.
502 \param [in] value Value to store
503 \param [in] ptr Pointer to location
504 */
__STRBT(uint8_t value,volatile uint8_t * ptr)505 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
506 {
507 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
508 }
509
510
511 /**
512 \brief STRT Unprivileged (16 bit)
513 \details Executes a Unprivileged STRT instruction for 16 bit values.
514 \param [in] value Value to store
515 \param [in] ptr Pointer to location
516 */
__STRHT(uint16_t value,volatile uint16_t * ptr)517 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
518 {
519 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
520 }
521
522
523 /**
524 \brief STRT Unprivileged (32 bit)
525 \details Executes a Unprivileged STRT instruction for 32 bit values.
526 \param [in] value Value to store
527 \param [in] ptr Pointer to location
528 */
__STRT(uint32_t value,volatile uint32_t * ptr)529 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
530 {
531 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
532 }
533 #endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
534
535
536 #if (__ARM_ARCH >= 8)
537 /**
538 \brief Load-Acquire (8 bit)
539 \details Executes a LDAB instruction for 8 bit value.
540 \param [in] ptr Pointer to data
541 \return value of type uint8_t at (*ptr)
542 */
__LDAB(volatile uint8_t * ptr)543 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
544 {
545 uint32_t result;
546
547 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
548 return ((uint8_t)result); /* Add explicit type cast here */
549 }
550
551
552 /**
553 \brief Load-Acquire (16 bit)
554 \details Executes a LDAH instruction for 16 bit values.
555 \param [in] ptr Pointer to data
556 \return value of type uint16_t at (*ptr)
557 */
__LDAH(volatile uint16_t * ptr)558 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
559 {
560 uint32_t result;
561
562 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
563 return ((uint16_t)result); /* Add explicit type cast here */
564 }
565
566
567 /**
568 \brief Load-Acquire (32 bit)
569 \details Executes a LDA instruction for 32 bit values.
570 \param [in] ptr Pointer to data
571 \return value of type uint32_t at (*ptr)
572 */
__LDA(volatile uint32_t * ptr)573 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
574 {
575 uint32_t result;
576
577 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
578 return (result);
579 }
580
581
582 /**
583 \brief Store-Release (8 bit)
584 \details Executes a STLB instruction for 8 bit values.
585 \param [in] value Value to store
586 \param [in] ptr Pointer to location
587 */
__STLB(uint8_t value,volatile uint8_t * ptr)588 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
589 {
590 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
591 }
592
593
594 /**
595 \brief Store-Release (16 bit)
596 \details Executes a STLH instruction for 16 bit values.
597 \param [in] value Value to store
598 \param [in] ptr Pointer to location
599 */
__STLH(uint16_t value,volatile uint16_t * ptr)600 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
601 {
602 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
603 }
604
605
606 /**
607 \brief Store-Release (32 bit)
608 \details Executes a STL instruction for 32 bit values.
609 \param [in] value Value to store
610 \param [in] ptr Pointer to location
611 */
__STL(uint32_t value,volatile uint32_t * ptr)612 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
613 {
614 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
615 }
616
617
618 /**
619 \brief Load-Acquire Exclusive (8 bit)
620 \details Executes a LDAB exclusive instruction for 8 bit value.
621 \param [in] ptr Pointer to data
622 \return value of type uint8_t at (*ptr)
623 */
624 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
625
626
627 /**
628 \brief Load-Acquire Exclusive (16 bit)
629 \details Executes a LDAH exclusive instruction for 16 bit values.
630 \param [in] ptr Pointer to data
631 \return value of type uint16_t at (*ptr)
632 */
633 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
634
635
636 /**
637 \brief Load-Acquire Exclusive (32 bit)
638 \details Executes a LDA exclusive instruction for 32 bit values.
639 \param [in] ptr Pointer to data
640 \return value of type uint32_t at (*ptr)
641 */
642 #define __LDAEX (uint32_t)__builtin_arm_ldaex
643
644
645 /**
646 \brief Store-Release Exclusive (8 bit)
647 \details Executes a STLB exclusive instruction for 8 bit values.
648 \param [in] value Value to store
649 \param [in] ptr Pointer to location
650 \return 0 Function succeeded
651 \return 1 Function failed
652 */
653 #define __STLEXB (uint32_t)__builtin_arm_stlex
654
655
656 /**
657 \brief Store-Release Exclusive (16 bit)
658 \details Executes a STLH exclusive instruction for 16 bit values.
659 \param [in] value Value to store
660 \param [in] ptr Pointer to location
661 \return 0 Function succeeded
662 \return 1 Function failed
663 */
664 #define __STLEXH (uint32_t)__builtin_arm_stlex
665
666
667 /**
668 \brief Store-Release Exclusive (32 bit)
669 \details Executes a STL exclusive instruction for 32 bit values.
670 \param [in] value Value to store
671 \param [in] ptr Pointer to location
672 \return 0 Function succeeded
673 \return 1 Function failed
674 */
675 #define __STLEX (uint32_t)__builtin_arm_stlex
676
677 #endif /* (__ARM_ARCH >= 8) */
678
679 /** @}*/ /* end of group CMSIS_Core_InstructionInterface */
680
681
682 /* ########################### Core Function Access ########################### */
683 /** \ingroup CMSIS_Core_FunctionInterface
684 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
685 @{
686 */
687
688 /**
689 \brief Enable IRQ Interrupts
690 \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
691 Can only be executed in Privileged modes.
692 */
693 #ifndef __ARM_COMPAT_H
__enable_irq(void)694 __STATIC_FORCEINLINE void __enable_irq(void)
695 {
696 __ASM volatile ("cpsie i" : : : "memory");
697 }
698 #endif
699
700
701 /**
702 \brief Disable IRQ Interrupts
703 \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
704 Can only be executed in Privileged modes.
705 */
706 #ifndef __ARM_COMPAT_H
__disable_irq(void)707 __STATIC_FORCEINLINE void __disable_irq(void)
708 {
709 __ASM volatile ("cpsid i" : : : "memory");
710 }
711 #endif
712
713
714 /**
715 \brief Get Control Register
716 \details Returns the content of the Control Register.
717 \return Control Register value
718 */
__get_CONTROL(void)719 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
720 {
721 uint32_t result;
722
723 __ASM volatile ("MRS %0, control" : "=r" (result) );
724 return (result);
725 }
726
727
728 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
729 /**
730 \brief Get Control Register (non-secure)
731 \details Returns the content of the non-secure Control Register when in secure mode.
732 \return non-secure Control Register value
733 */
__TZ_get_CONTROL_NS(void)734 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
735 {
736 uint32_t result;
737
738 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
739 return (result);
740 }
741 #endif
742
743
744 /**
745 \brief Set Control Register
746 \details Writes the given value to the Control Register.
747 \param [in] control Control Register value to set
748 */
__set_CONTROL(uint32_t control)749 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
750 {
751 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
752 __ISB();
753 }
754
755
756 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
757 /**
758 \brief Set Control Register (non-secure)
759 \details Writes the given value to the non-secure Control Register when in secure state.
760 \param [in] control Control Register value to set
761 */
__TZ_set_CONTROL_NS(uint32_t control)762 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
763 {
764 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
765 __ISB();
766 }
767 #endif
768
769
770 /**
771 \brief Get IPSR Register
772 \details Returns the content of the IPSR Register.
773 \return IPSR Register value
774 */
__get_IPSR(void)775 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
776 {
777 uint32_t result;
778
779 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
780 return (result);
781 }
782
783
784 /**
785 \brief Get APSR Register
786 \details Returns the content of the APSR Register.
787 \return APSR Register value
788 */
__get_APSR(void)789 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
790 {
791 uint32_t result;
792
793 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
794 return (result);
795 }
796
797
798 /**
799 \brief Get xPSR Register
800 \details Returns the content of the xPSR Register.
801 \return xPSR Register value
802 */
__get_xPSR(void)803 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
804 {
805 uint32_t result;
806
807 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
808 return (result);
809 }
810
811
812 /**
813 \brief Get Process Stack Pointer
814 \details Returns the current value of the Process Stack Pointer (PSP).
815 \return PSP Register value
816 */
__get_PSP(void)817 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
818 {
819 uint32_t result;
820
821 __ASM volatile ("MRS %0, psp" : "=r" (result) );
822 return (result);
823 }
824
825
826 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
827 /**
828 \brief Get Process Stack Pointer (non-secure)
829 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
830 \return PSP Register value
831 */
__TZ_get_PSP_NS(void)832 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
833 {
834 uint32_t result;
835
836 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
837 return (result);
838 }
839 #endif
840
841
842 /**
843 \brief Set Process Stack Pointer
844 \details Assigns the given value to the Process Stack Pointer (PSP).
845 \param [in] topOfProcStack Process Stack Pointer value to set
846 */
__set_PSP(uint32_t topOfProcStack)847 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
848 {
849 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
850 }
851
852
853 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
854 /**
855 \brief Set Process Stack Pointer (non-secure)
856 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
857 \param [in] topOfProcStack Process Stack Pointer value to set
858 */
__TZ_set_PSP_NS(uint32_t topOfProcStack)859 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
860 {
861 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
862 }
863 #endif
864
865
866 /**
867 \brief Get Main Stack Pointer
868 \details Returns the current value of the Main Stack Pointer (MSP).
869 \return MSP Register value
870 */
__get_MSP(void)871 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
872 {
873 uint32_t result;
874
875 __ASM volatile ("MRS %0, msp" : "=r" (result) );
876 return (result);
877 }
878
879
880 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
881 /**
882 \brief Get Main Stack Pointer (non-secure)
883 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
884 \return MSP Register value
885 */
__TZ_get_MSP_NS(void)886 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
887 {
888 uint32_t result;
889
890 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
891 return (result);
892 }
893 #endif
894
895
896 /**
897 \brief Set Main Stack Pointer
898 \details Assigns the given value to the Main Stack Pointer (MSP).
899 \param [in] topOfMainStack Main Stack Pointer value to set
900 */
__set_MSP(uint32_t topOfMainStack)901 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
902 {
903 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
904 }
905
906
907 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
908 /**
909 \brief Set Main Stack Pointer (non-secure)
910 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
911 \param [in] topOfMainStack Main Stack Pointer value to set
912 */
__TZ_set_MSP_NS(uint32_t topOfMainStack)913 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
914 {
915 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
916 }
917 #endif
918
919
920 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
921 /**
922 \brief Get Stack Pointer (non-secure)
923 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
924 \return SP Register value
925 */
__TZ_get_SP_NS(void)926 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
927 {
928 uint32_t result;
929
930 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
931 return (result);
932 }
933
934
935 /**
936 \brief Set Stack Pointer (non-secure)
937 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
938 \param [in] topOfStack Stack Pointer value to set
939 */
__TZ_set_SP_NS(uint32_t topOfStack)940 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
941 {
942 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
943 }
944 #endif
945
946
947 /**
948 \brief Get Priority Mask
949 \details Returns the current state of the priority mask bit from the Priority Mask Register.
950 \return Priority Mask value
951 */
__get_PRIMASK(void)952 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
953 {
954 uint32_t result;
955
956 __ASM volatile ("MRS %0, primask" : "=r" (result) );
957 return (result);
958 }
959
960
961 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
962 /**
963 \brief Get Priority Mask (non-secure)
964 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
965 \return Priority Mask value
966 */
__TZ_get_PRIMASK_NS(void)967 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
968 {
969 uint32_t result;
970
971 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
972 return (result);
973 }
974 #endif
975
976
977 /**
978 \brief Set Priority Mask
979 \details Assigns the given value to the Priority Mask Register.
980 \param [in] priMask Priority Mask
981 */
__set_PRIMASK(uint32_t priMask)982 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
983 {
984 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
985 }
986
987
988 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
989 /**
990 \brief Set Priority Mask (non-secure)
991 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
992 \param [in] priMask Priority Mask
993 */
__TZ_set_PRIMASK_NS(uint32_t priMask)994 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
995 {
996 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
997 }
998 #endif
999
1000
1001 #if (__ARM_ARCH_ISA_THUMB >= 2)
1002 /**
1003 \brief Enable FIQ
1004 \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1005 Can only be executed in Privileged modes.
1006 */
__enable_fault_irq(void)1007 __STATIC_FORCEINLINE void __enable_fault_irq(void)
1008 {
1009 __ASM volatile ("cpsie f" : : : "memory");
1010 }
1011
1012
1013 /**
1014 \brief Disable FIQ
1015 \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1016 Can only be executed in Privileged modes.
1017 */
__disable_fault_irq(void)1018 __STATIC_FORCEINLINE void __disable_fault_irq(void)
1019 {
1020 __ASM volatile ("cpsid f" : : : "memory");
1021 }
1022
1023
1024 /**
1025 \brief Get Base Priority
1026 \details Returns the current value of the Base Priority register.
1027 \return Base Priority register value
1028 */
__get_BASEPRI(void)1029 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1030 {
1031 uint32_t result;
1032
1033 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1034 return (result);
1035 }
1036
1037
1038 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1039 /**
1040 \brief Get Base Priority (non-secure)
1041 \details Returns the current value of the non-secure Base Priority register when in secure state.
1042 \return Base Priority register value
1043 */
__TZ_get_BASEPRI_NS(void)1044 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1045 {
1046 uint32_t result;
1047
1048 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1049 return (result);
1050 }
1051 #endif
1052
1053
1054 /**
1055 \brief Set Base Priority
1056 \details Assigns the given value to the Base Priority register.
1057 \param [in] basePri Base Priority value to set
1058 */
__set_BASEPRI(uint32_t basePri)1059 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1060 {
1061 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1062 }
1063
1064
1065 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1066 /**
1067 \brief Set Base Priority (non-secure)
1068 \details Assigns the given value to the non-secure Base Priority register when in secure state.
1069 \param [in] basePri Base Priority value to set
1070 */
__TZ_set_BASEPRI_NS(uint32_t basePri)1071 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1072 {
1073 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1074 }
1075 #endif
1076
1077
1078 /**
1079 \brief Set Base Priority with condition
1080 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1081 or the new value increases the BASEPRI priority level.
1082 \param [in] basePri Base Priority value to set
1083 */
__set_BASEPRI_MAX(uint32_t basePri)1084 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1085 {
1086 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1087 }
1088
1089
1090 /**
1091 \brief Get Fault Mask
1092 \details Returns the current value of the Fault Mask register.
1093 \return Fault Mask register value
1094 */
__get_FAULTMASK(void)1095 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1096 {
1097 uint32_t result;
1098
1099 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1100 return (result);
1101 }
1102
1103
1104 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1105 /**
1106 \brief Get Fault Mask (non-secure)
1107 \details Returns the current value of the non-secure Fault Mask register when in secure state.
1108 \return Fault Mask register value
1109 */
__TZ_get_FAULTMASK_NS(void)1110 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1111 {
1112 uint32_t result;
1113
1114 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1115 return (result);
1116 }
1117 #endif
1118
1119
1120 /**
1121 \brief Set Fault Mask
1122 \details Assigns the given value to the Fault Mask register.
1123 \param [in] faultMask Fault Mask value to set
1124 */
__set_FAULTMASK(uint32_t faultMask)1125 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1126 {
1127 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1128 }
1129
1130
1131 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1132 /**
1133 \brief Set Fault Mask (non-secure)
1134 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1135 \param [in] faultMask Fault Mask value to set
1136 */
__TZ_set_FAULTMASK_NS(uint32_t faultMask)1137 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1138 {
1139 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1140 }
1141 #endif
1142
1143 #endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
1144
1145
1146 #if (__ARM_ARCH >= 8)
1147 /**
1148 \brief Get Process Stack Pointer Limit
1149 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1150 Stack Pointer Limit register hence zero is returned always in non-secure
1151 mode.
1152
1153 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1154 \return PSPLIM Register value
1155 */
__get_PSPLIM(void)1156 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1157 {
1158 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1159 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
1160 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
1161 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
1162 return (0U);
1163 #else
1164 uint32_t result;
1165 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
1166 return (result);
1167 #endif
1168 }
1169
1170 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1171 /**
1172 \brief Get Process Stack Pointer Limit (non-secure)
1173 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1174 Stack Pointer Limit register hence zero is returned always.
1175
1176 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1177 \return PSPLIM Register value
1178 */
__TZ_get_PSPLIM_NS(void)1179 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1180 {
1181 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1182 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
1183 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
1184 return (0U);
1185 #else
1186 uint32_t result;
1187 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
1188 return (result);
1189 #endif
1190 }
1191 #endif
1192
1193
1194 /**
1195 \brief Set Process Stack Pointer Limit
1196 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1197 Stack Pointer Limit register hence the write is silently ignored in non-secure
1198 mode.
1199
1200 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1201 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1202 */
__set_PSPLIM(uint32_t ProcStackPtrLimit)1203 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1204 {
1205 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1206 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
1207 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
1208 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
1209 (void)ProcStackPtrLimit;
1210 #else
1211 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1212 #endif
1213 }
1214
1215
1216 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1217 /**
1218 \brief Set Process Stack Pointer (non-secure)
1219 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1220 Stack Pointer Limit register hence the write is silently ignored.
1221
1222 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1223 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1224 */
__TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)1225 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1226 {
1227 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1228 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
1229 /* without main extensions, the non-secure PSPLIM is RAZ/WI */
1230 (void)ProcStackPtrLimit;
1231 #else
1232 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1233 #endif
1234 }
1235 #endif
1236
1237
1238 /**
1239 \brief Get Main Stack Pointer Limit
1240 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1241 Stack Pointer Limit register hence zero is returned always.
1242
1243 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1244 \return MSPLIM Register value
1245 */
__get_MSPLIM(void)1246 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1247 {
1248 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1249 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
1250 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
1251 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
1252 return (0U);
1253 #else
1254 uint32_t result;
1255 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1256 return (result);
1257 #endif
1258 }
1259
1260
1261 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1262 /**
1263 \brief Get Main Stack Pointer Limit (non-secure)
1264 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1265 Stack Pointer Limit register hence zero is returned always.
1266
1267 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1268 \return MSPLIM Register value
1269 */
__TZ_get_MSPLIM_NS(void)1270 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1271 {
1272 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1273 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
1274 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
1275 return (0U);
1276 #else
1277 uint32_t result;
1278 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1279 return (result);
1280 #endif
1281 }
1282 #endif
1283
1284
1285 /**
1286 \brief Set Main Stack Pointer Limit
1287 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1288 Stack Pointer Limit register hence the write is silently ignored.
1289
1290 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1291 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
1292 */
__set_MSPLIM(uint32_t MainStackPtrLimit)1293 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1294 {
1295 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1296 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
1297 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
1298 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
1299 (void)MainStackPtrLimit;
1300 #else
1301 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1302 #endif
1303 }
1304
1305
1306 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
1307 /**
1308 \brief Set Main Stack Pointer Limit (non-secure)
1309 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1310 Stack Pointer Limit register hence the write is silently ignored.
1311
1312 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1313 \param [in] MainStackPtrLimit Main Stack Pointer value to set
1314 */
__TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)1315 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1316 {
1317 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1318 !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)))
1319 /* without main extensions, the non-secure MSPLIM is RAZ/WI */
1320 (void)MainStackPtrLimit;
1321 #else
1322 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1323 #endif
1324 }
1325 #endif
1326
1327 #endif /* (__ARM_ARCH >= 8) */
1328
1329
1330 /**
1331 \brief Get FPSCR
1332 \details Returns the current value of the Floating Point Status/Control register.
1333 \return Floating Point Status/Control register value
1334 */
__get_FPSCR(void)1335 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
1336 {
1337 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
1338 return (__builtin_arm_get_fpscr());
1339 #else
1340 return (0U);
1341 #endif
1342 }
1343
1344
1345 /**
1346 \brief Set FPSCR
1347 \details Assigns the given value to the Floating Point Status/Control register.
1348 \param [in] fpscr Floating Point Status/Control value to set
1349 */
__set_FPSCR(uint32_t fpscr)1350 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
1351 {
1352 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
1353 __builtin_arm_set_fpscr(fpscr);
1354 #else
1355 (void)fpscr;
1356 #endif
1357 }
1358
1359
1360 /** @} end of CMSIS_Core_RegAccFunctions */
1361
1362
1363 /* ################### Compiler specific Intrinsics ########################### */
1364 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1365 Access to dedicated SIMD instructions
1366 @{
1367 */
1368
1369 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1370 #define __SADD8 __sadd8
1371 #define __QADD8 __qadd8
1372 #define __SHADD8 __shadd8
1373 #define __UADD8 __uadd8
1374 #define __UQADD8 __uqadd8
1375 #define __UHADD8 __uhadd8
1376 #define __SSUB8 __ssub8
1377 #define __QSUB8 __qsub8
1378 #define __SHSUB8 __shsub8
1379 #define __USUB8 __usub8
1380 #define __UQSUB8 __uqsub8
1381 #define __UHSUB8 __uhsub8
1382 #define __SADD16 __sadd16
1383 #define __QADD16 __qadd16
1384 #define __SHADD16 __shadd16
1385 #define __UADD16 __uadd16
1386 #define __UQADD16 __uqadd16
1387 #define __UHADD16 __uhadd16
1388 #define __SSUB16 __ssub16
1389 #define __QSUB16 __qsub16
1390 #define __SHSUB16 __shsub16
1391 #define __USUB16 __usub16
1392 #define __UQSUB16 __uqsub16
1393 #define __UHSUB16 __uhsub16
1394 #define __SASX __sasx
1395 #define __QASX __qasx
1396 #define __SHASX __shasx
1397 #define __UASX __uasx
1398 #define __UQASX __uqasx
1399 #define __UHASX __uhasx
1400 #define __SSAX __ssax
1401 #define __QSAX __qsax
1402 #define __SHSAX __shsax
1403 #define __USAX __usax
1404 #define __UQSAX __uqsax
1405 #define __UHSAX __uhsax
1406 #define __USAD8 __usad8
1407 #define __USADA8 __usada8
1408 #define __SSAT16 __ssat16
1409 #define __USAT16 __usat16
1410 #define __UXTB16 __uxtb16
1411 #define __UXTAB16 __uxtab16
1412 #define __SXTB16 __sxtb16
1413 #define __SXTAB16 __sxtab16
1414 #define __SMUAD __smuad
1415 #define __SMUADX __smuadx
1416 #define __SMLAD __smlad
1417 #define __SMLADX __smladx
1418 #define __SMLALD __smlald
1419 #define __SMLALDX __smlaldx
1420 #define __SMUSD __smusd
1421 #define __SMUSDX __smusdx
1422 #define __SMLSD __smlsd
1423 #define __SMLSDX __smlsdx
1424 #define __SMLSLD __smlsld
1425 #define __SMLSLDX __smlsldx
1426 #define __SEL __sel
1427 #define __QADD __qadd
1428 #define __QSUB __qsub
1429
1430 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1431 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1432
1433 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1434 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1435
1436 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1437
1438 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1439
__SMMLA(int32_t op1,int32_t op2,int32_t op3)1440 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1441 {
1442 int32_t result;
1443
1444 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1445 return (result);
1446 }
1447 #endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
1448 /** @} end of group CMSIS_SIMD_intrinsics */
1449
1450
1451 #endif /* __CMSIS_TIARMCLANG_M_H */
1452
