1 /**************************************************************************//**
2 * @file cmsis_gcc.h
3 * @brief CMSIS compiler specific macros, functions, instructions
4 * @version V1.3.2
5 * @date 24. March 2022
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #ifndef __CMSIS_GCC_H
26 #define __CMSIS_GCC_H
27
28 /* ignore some GCC warnings */
29 #pragma GCC diagnostic push
30 #pragma GCC diagnostic ignored "-Wsign-conversion"
31 #pragma GCC diagnostic ignored "-Wconversion"
32 #pragma GCC diagnostic ignored "-Wunused-parameter"
33
34 /* Fallback for __has_builtin */
35 #ifndef __has_builtin
36 #define __has_builtin(x) (0)
37 #endif
38
39 /* CMSIS compiler specific defines */
40 #ifndef __ASM
41 #define __ASM __asm
42 #endif
43 #ifndef __INLINE
44 #define __INLINE inline
45 #endif
46 #ifndef __FORCEINLINE
47 #define __FORCEINLINE __attribute__((always_inline))
48 #endif
49 #ifndef __STATIC_INLINE
50 #define __STATIC_INLINE static inline
51 #endif
52 #ifndef __STATIC_FORCEINLINE
53 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
54 #endif
55 #ifndef __NO_RETURN
56 #define __NO_RETURN __attribute__((__noreturn__))
57 #endif
58 #ifndef CMSIS_DEPRECATED
59 #define CMSIS_DEPRECATED __attribute__((deprecated))
60 #endif
61 #ifndef __USED
62 #define __USED __attribute__((used))
63 #endif
64 #ifndef __WEAK
65 #define __WEAK __attribute__((weak))
66 #endif
67 #ifndef __PACKED
68 #define __PACKED __attribute__((packed, aligned(1)))
69 #endif
70 #ifndef __PACKED_STRUCT
71 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
72 #endif
73 #ifndef __UNALIGNED_UINT16_WRITE
74 #pragma GCC diagnostic push
75 #pragma GCC diagnostic ignored "-Wpacked"
76 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
77 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
78 #pragma GCC diagnostic pop
79 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
80 #endif
81 #ifndef __UNALIGNED_UINT16_READ
82 #pragma GCC diagnostic push
83 #pragma GCC diagnostic ignored "-Wpacked"
84 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
85 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
86 #pragma GCC diagnostic pop
87 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
88 #endif
89 #ifndef __UNALIGNED_UINT32_WRITE
90 #pragma GCC diagnostic push
91 #pragma GCC diagnostic ignored "-Wpacked"
92 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
93 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
94 #pragma GCC diagnostic pop
95 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
96 #endif
97 #ifndef __UNALIGNED_UINT32_READ
98 #pragma GCC diagnostic push
99 #pragma GCC diagnostic ignored "-Wpacked"
100 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
101 #pragma GCC diagnostic pop
102 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
103 #endif
104 #ifndef __ALIGNED
105 #define __ALIGNED(x) __attribute__((aligned(x)))
106 #endif
107 #ifndef __COMPILER_BARRIER
108 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
109 #endif
110
111
__QSUB16(uint32_t op1,uint32_t op2)112 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
113 {
114 uint32_t result;
115
116 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
117 return(result);
118 }
119
120
__QSUB8(uint32_t op1,uint32_t op2)121 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
122 {
123 uint32_t result;
124
125 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
126 return(result);
127 }
128
129
__QADD16(uint32_t op1,uint32_t op2)130 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
131 {
132 uint32_t result;
133
134 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
135 return(result);
136 }
137
__QADD8(uint32_t op1,uint32_t op2)138 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
139 {
140 uint32_t result;
141
142 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
143 return(result);
144 }
145
__QADD(int32_t op1,int32_t op2)146 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
147 {
148 int32_t result;
149
150 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
151 return(result);
152 }
153
__QSAX(uint32_t op1,uint32_t op2)154 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
155 {
156 uint32_t result;
157
158 __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
159 return(result);
160 }
161
__SHSAX(uint32_t op1,uint32_t op2)162 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
163 {
164 uint32_t result;
165
166 __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
167 return(result);
168 }
169
__SMLALD(uint32_t op1,uint32_t op2,uint64_t acc)170 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
171 {
172 union llreg_u{
173 uint32_t w32[2];
174 uint64_t w64;
175 } llr;
176 llr.w64 = acc;
177
178 #ifndef __ARMEB__ /* Little endian */
179 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
180 #else /* Big endian */
181 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
182 #endif
183
184 return(llr.w64);
185 }
186
__QSUB(int32_t op1,int32_t op2)187 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
188 {
189 int32_t result;
190
191 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
192 return(result);
193 }
194
__SXTB16(uint32_t op1)195 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
196 {
197 uint32_t result;
198
199 __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
200 return(result);
201 }
202
203
__SMUAD(uint32_t op1,uint32_t op2)204 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
205 {
206 uint32_t result;
207
208 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
209 return(result);
210 }
211
212
213
214 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
215 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
216
217 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
218 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
219
__SMLAD(uint32_t op1,uint32_t op2,uint32_t op3)220 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
221 {
222 uint32_t result;
223
224 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
225 return(result);
226 }
227
__SMUADX(uint32_t op1,uint32_t op2)228 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
229 {
230 uint32_t result;
231
232 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
233 return(result);
234 }
235
__SMLADX(uint32_t op1,uint32_t op2,uint32_t op3)236 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
237 {
238 uint32_t result;
239
240 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
241 return(result);
242 }
243
__SMLALDX(uint32_t op1,uint32_t op2,uint64_t acc)244 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
245 {
246 union llreg_u{
247 uint32_t w32[2];
248 uint64_t w64;
249 } llr;
250 llr.w64 = acc;
251
252 #ifndef __ARMEB__ /* Little endian */
253 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
254 #else /* Big endian */
255 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
256 #endif
257
258 return(llr.w64);
259 }
260
__SMMLA(int32_t op1,int32_t op2,int32_t op3)261 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
262 {
263 int32_t result;
264
265 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
266 return(result);
267 }
268
__SMUSD(uint32_t op1,uint32_t op2)269 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
270 {
271 uint32_t result;
272
273 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
274 return(result);
275 }
276
__SMUSDX(uint32_t op1,uint32_t op2)277 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
278 {
279 uint32_t result;
280
281 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
282 return(result);
283 }
284
__QASX(uint32_t op1,uint32_t op2)285 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
286 {
287 uint32_t result;
288
289 __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
290 return(result);
291 }
292
__SHADD16(uint32_t op1,uint32_t op2)293 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
294 {
295 uint32_t result;
296
297 __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
298 return(result);
299 }
300
__SHSUB16(uint32_t op1,uint32_t op2)301 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
302 {
303 uint32_t result;
304
305 __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
306 return(result);
307 }
308
__SHASX(uint32_t op1,uint32_t op2)309 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
310 {
311 uint32_t result;
312
313 __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
314 return(result);
315 }
316
__SMLSDX(uint32_t op1,uint32_t op2,uint32_t op3)317 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
318 {
319 uint32_t result;
320
321 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
322 return(result);
323 }
324
325
326 /* ########################## Core Instruction Access ######################### */
327 /**
328 \brief No Operation
329 */
330 #define __NOP() __ASM volatile ("nop")
331
332 /**
333 \brief Wait For Interrupt
334 */
335 #define __WFI() __ASM volatile ("wfi":::"memory")
336
337 /**
338 \brief Wait For Event
339 */
340 #define __WFE() __ASM volatile ("wfe":::"memory")
341
342 /**
343 \brief Send Event
344 */
345 #define __SEV() __ASM volatile ("sev")
346
347 /**
348 \brief Instruction Synchronization Barrier
349 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
350 so that all instructions following the ISB are fetched from cache or memory,
351 after the instruction has been completed.
352 */
__ISB(void)353 __STATIC_FORCEINLINE void __ISB(void)
354 {
355 __ASM volatile ("isb 0xF":::"memory");
356 }
357
358
359 /**
360 \brief Data Synchronization Barrier
361 \details Acts as a special kind of Data Memory Barrier.
362 It completes when all explicit memory accesses before this instruction complete.
363 */
__DSB(void)364 __STATIC_FORCEINLINE void __DSB(void)
365 {
366 __ASM volatile ("dsb 0xF":::"memory");
367 }
368
369 /**
370 \brief Data Memory Barrier
371 \details Ensures the apparent order of the explicit memory operations before
372 and after the instruction, without ensuring their completion.
373 */
__DMB(void)374 __STATIC_FORCEINLINE void __DMB(void)
375 {
376 __ASM volatile ("dmb 0xF":::"memory");
377 }
378
379 /**
380 \brief Reverse byte order (32 bit)
381 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
382 \param [in] value Value to reverse
383 \return Reversed value
384 */
__REV(uint32_t value)385 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
386 {
387 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
388 return __builtin_bswap32(value);
389 #else
390 uint32_t result;
391
392 __ASM ("rev %0, %1" : "=r" (result) : "r" (value) );
393 return result;
394 #endif
395 }
396
397 /**
398 \brief Reverse byte order (16 bit)
399 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
400 \param [in] value Value to reverse
401 \return Reversed value
402 */
__REV16(uint32_t value)403 __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
404 {
405 uint32_t result;
406 __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value));
407 return result;
408 }
409
410 /**
411 \brief Reverse byte order (16 bit)
412 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
413 \param [in] value Value to reverse
414 \return Reversed value
415 */
__REVSH(int16_t value)416 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
417 {
418 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
419 return (int16_t)__builtin_bswap16(value);
420 #else
421 int16_t result;
422
423 __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) );
424 return result;
425 #endif
426 }
427
428 /**
429 \brief Rotate Right in unsigned value (32 bit)
430 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
431 \param [in] op1 Value to rotate
432 \param [in] op2 Number of Bits to rotate
433 \return Rotated value
434 */
__ROR(uint32_t op1,uint32_t op2)435 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
436 {
437 op2 %= 32U;
438 if (op2 == 0U)
439 {
440 return op1;
441 }
442 return (op1 >> op2) | (op1 << (32U - op2));
443 }
444
445
446 /**
447 \brief Breakpoint
448 \param [in] value is ignored by the processor.
449 If required, a debugger can use it to store additional information about the breakpoint.
450 */
451 #define __BKPT(value) __ASM volatile ("bkpt "#value)
452
453 /**
454 \brief Reverse bit order of value
455 \details Reverses the bit order of the given value.
456 \param [in] value Value to reverse
457 \return Reversed value
458 */
__RBIT(uint32_t value)459 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
460 {
461 uint32_t result;
462 __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
463 return result;
464 }
465
466 /**
467 \brief Count leading zeros
468 \param [in] value Value to count the leading zeros
469 \return number of leading zeros in value
470 */
__CLZ(uint32_t value)471 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
472 {
473 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
474 __builtin_clz(0) is undefined behaviour, so handle this case specially.
475 This guarantees ARM-compatible results if happening to compile on a non-ARM
476 target, and ensures the compiler doesn't decide to activate any
477 optimisations using the logic "value was passed to __builtin_clz, so it
478 is non-zero".
479 ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
480 single CLZ instruction.
481 */
482 if (value == 0U)
483 {
484 return 32U;
485 }
486 return __builtin_clz(value);
487 }
488
489 /**
490 \brief LDR Exclusive (8 bit)
491 \details Executes a exclusive LDR instruction for 8 bit value.
492 \param [in] ptr Pointer to data
493 \return value of type uint8_t at (*ptr)
494 */
__LDREXB(volatile uint8_t * addr)495 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
496 {
497 uint32_t result;
498
499 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
500 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
501 #else
502 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
503 accepted by assembler. So has to use following less efficient pattern.
504 */
505 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
506 #endif
507 return ((uint8_t) result); /* Add explicit type cast here */
508 }
509
510
511 /**
512 \brief LDR Exclusive (16 bit)
513 \details Executes a exclusive LDR instruction for 16 bit values.
514 \param [in] ptr Pointer to data
515 \return value of type uint16_t at (*ptr)
516 */
__LDREXH(volatile uint16_t * addr)517 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
518 {
519 uint32_t result;
520
521 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
522 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
523 #else
524 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
525 accepted by assembler. So has to use following less efficient pattern.
526 */
527 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
528 #endif
529 return ((uint16_t) result); /* Add explicit type cast here */
530 }
531
532
533 /**
534 \brief LDR Exclusive (32 bit)
535 \details Executes a exclusive LDR instruction for 32 bit values.
536 \param [in] ptr Pointer to data
537 \return value of type uint32_t at (*ptr)
538 */
__LDREXW(volatile uint32_t * addr)539 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
540 {
541 uint32_t result;
542
543 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
544 return(result);
545 }
546
547
548 /**
549 \brief STR Exclusive (8 bit)
550 \details Executes a exclusive STR instruction for 8 bit values.
551 \param [in] value Value to store
552 \param [in] ptr Pointer to location
553 \return 0 Function succeeded
554 \return 1 Function failed
555 */
__STREXB(uint8_t value,volatile uint8_t * addr)556 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
557 {
558 uint32_t result;
559
560 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
561 return(result);
562 }
563
564
565 /**
566 \brief STR Exclusive (16 bit)
567 \details Executes a exclusive STR instruction for 16 bit values.
568 \param [in] value Value to store
569 \param [in] ptr Pointer to location
570 \return 0 Function succeeded
571 \return 1 Function failed
572 */
__STREXH(uint16_t value,volatile uint16_t * addr)573 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
574 {
575 uint32_t result;
576
577 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
578 return(result);
579 }
580
581
582 /**
583 \brief STR Exclusive (32 bit)
584 \details Executes a exclusive STR instruction for 32 bit values.
585 \param [in] value Value to store
586 \param [in] ptr Pointer to location
587 \return 0 Function succeeded
588 \return 1 Function failed
589 */
__STREXW(uint32_t value,volatile uint32_t * addr)590 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
591 {
592 uint32_t result;
593
594 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
595 return(result);
596 }
597
598
599 /**
600 \brief Remove the exclusive lock
601 \details Removes the exclusive lock which is created by LDREX.
602 */
__CLREX(void)603 __STATIC_FORCEINLINE void __CLREX(void)
604 {
605 __ASM volatile ("clrex" ::: "memory");
606 }
607
608 /**
609 \brief Signed Saturate
610 \details Saturates a signed value.
611 \param [in] value Value to be saturated
612 \param [in] sat Bit position to saturate to (1..32)
613 \return Saturated value
614 */
615 #define __SSAT(ARG1, ARG2) \
616 __extension__ \
617 ({ \
618 int32_t __RES, __ARG1 = (ARG1); \
619 __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
620 __RES; \
621 })
622
623
624 /**
625 \brief Unsigned Saturate
626 \details Saturates an unsigned value.
627 \param [in] value Value to be saturated
628 \param [in] sat Bit position to saturate to (0..31)
629 \return Saturated value
630 */
631 #define __USAT(ARG1, ARG2) \
632 __extension__ \
633 ({ \
634 uint32_t __RES, __ARG1 = (ARG1); \
635 __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
636 __RES; \
637 })
638
639 /* ########################### Core Function Access ########################### */
640
641 /**
642 \brief Enable IRQ Interrupts
643 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
644 Can only be executed in Privileged modes.
645 */
__enable_irq(void)646 __STATIC_FORCEINLINE void __enable_irq(void)
647 {
648 __ASM volatile ("cpsie i" : : : "memory");
649 }
650
651 /**
652 \brief Disable IRQ Interrupts
653 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
654 Can only be executed in Privileged modes.
655 */
__disable_irq(void)656 __STATIC_FORCEINLINE void __disable_irq(void)
657 {
658 __ASM volatile ("cpsid i" : : : "memory");
659 }
660
661 /**
662 \brief Enable FIQ
663 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
664 Can only be executed in Privileged modes.
665 */
__enable_fault_irq(void)666 __STATIC_FORCEINLINE void __enable_fault_irq(void)
667 {
668 __ASM volatile ("cpsie f" : : : "memory");
669 }
670
671 /**
672 \brief Disable FIQ
673 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
674 Can only be executed in Privileged modes.
675 */
__disable_fault_irq(void)676 __STATIC_FORCEINLINE void __disable_fault_irq(void)
677 {
678 __ASM volatile ("cpsid f" : : : "memory");
679 }
680
681 /**
682 \brief Get FPSCR
683 \details Returns the current value of the Floating Point Status/Control register.
684 \return Floating Point Status/Control register value
685 */
__get_FPSCR(void)686 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
687 {
688 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
689 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
690 #if __has_builtin(__builtin_arm_get_fpscr)
691 // Re-enable using built-in when GCC has been fixed
692 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
693 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
694 return __builtin_arm_get_fpscr();
695 #else
696 uint32_t result;
697
698 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
699 return(result);
700 #endif
701 #else
702 return(0U);
703 #endif
704 }
705
706 /**
707 \brief Set FPSCR
708 \details Assigns the given value to the Floating Point Status/Control register.
709 \param [in] fpscr Floating Point Status/Control value to set
710 */
__set_FPSCR(uint32_t fpscr)711 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
712 {
713 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
714 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
715 #if __has_builtin(__builtin_arm_set_fpscr)
716 // Re-enable using built-in when GCC has been fixed
717 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
718 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
719 __builtin_arm_set_fpscr(fpscr);
720 #else
721 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
722 #endif
723 #else
724 (void)fpscr;
725 #endif
726 }
727
728 /** \brief Get CPSR Register
729 \return CPSR Register value
730 */
__get_CPSR(void)731 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
732 {
733 uint32_t result;
734 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
735 return(result);
736 }
737
738 /** \brief Set CPSR Register
739 \param [in] cpsr CPSR value to set
740 */
__set_CPSR(uint32_t cpsr)741 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
742 {
743 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
744 }
745
746 /** \brief Get Mode
747 \return Processor Mode
748 */
__get_mode(void)749 __STATIC_FORCEINLINE uint32_t __get_mode(void)
750 {
751 return (__get_CPSR() & 0x1FU);
752 }
753
754 /** \brief Set Mode
755 \param [in] mode Mode value to set
756 */
__set_mode(uint32_t mode)757 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
758 {
759 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
760 }
761
762 /** \brief Get Stack Pointer
763 \return Stack Pointer value
764 */
__get_SP(void)765 __STATIC_FORCEINLINE uint32_t __get_SP(void)
766 {
767 uint32_t result;
768 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
769 return result;
770 }
771
772 /** \brief Set Stack Pointer
773 \param [in] stack Stack Pointer value to set
774 */
__set_SP(uint32_t stack)775 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
776 {
777 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
778 }
779
780 /** \brief Get USR/SYS Stack Pointer
781 \return USR/SYS Stack Pointer value
782 */
__get_SP_usr(void)783 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
784 {
785 uint32_t cpsr = __get_CPSR();
786 uint32_t result;
787 __ASM volatile(
788 "CPS #0x1F \n"
789 "MOV %0, sp " : "=r"(result) : : "memory"
790 );
791 __set_CPSR(cpsr);
792 __ISB();
793 return result;
794 }
795
796 /** \brief Set USR/SYS Stack Pointer
797 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
798 */
__set_SP_usr(uint32_t topOfProcStack)799 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
800 {
801 uint32_t cpsr = __get_CPSR();
802 __ASM volatile(
803 "CPS #0x1F \n"
804 "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
805 );
806 __set_CPSR(cpsr);
807 __ISB();
808 }
809
810 /** \brief Get FPEXC
811 \return Floating Point Exception Control register value
812 */
__get_FPEXC(void)813 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
814 {
815 #if (__FPU_PRESENT == 1)
816 uint32_t result;
817 __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
818 return(result);
819 #else
820 return(0);
821 #endif
822 }
823
824 /** \brief Set FPEXC
825 \param [in] fpexc Floating Point Exception Control value to set
826 */
__set_FPEXC(uint32_t fpexc)827 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
828 {
829 #if (__FPU_PRESENT == 1)
830 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
831 #endif
832 }
833
834 /*
835 * Include common core functions to access Coprocessor 15 registers
836 */
837
838 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
839 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
840 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
841 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
842
843 #include "cmsis_cp15.h"
844
845 /** \brief Enable Floating Point Unit
846
847 Critical section, called from undef handler, so systick is disabled
848 */
__FPU_Enable(void)849 __STATIC_INLINE void __FPU_Enable(void)
850 {
851 __ASM volatile(
852 //Permit access to VFP/NEON, registers by modifying CPACR
853 " MRC p15,0,R1,c1,c0,2 \n"
854 " ORR R1,R1,#0x00F00000 \n"
855 " MCR p15,0,R1,c1,c0,2 \n"
856
857 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
858 " ISB \n"
859
860 //Enable VFP/NEON
861 " VMRS R1,FPEXC \n"
862 " ORR R1,R1,#0x40000000 \n"
863 " VMSR FPEXC,R1 \n"
864
865 //Initialise VFP/NEON registers to 0
866 " MOV R2,#0 \n"
867
868 //Initialise D16 registers to 0
869 " VMOV D0, R2,R2 \n"
870 " VMOV D1, R2,R2 \n"
871 " VMOV D2, R2,R2 \n"
872 " VMOV D3, R2,R2 \n"
873 " VMOV D4, R2,R2 \n"
874 " VMOV D5, R2,R2 \n"
875 " VMOV D6, R2,R2 \n"
876 " VMOV D7, R2,R2 \n"
877 " VMOV D8, R2,R2 \n"
878 " VMOV D9, R2,R2 \n"
879 " VMOV D10,R2,R2 \n"
880 " VMOV D11,R2,R2 \n"
881 " VMOV D12,R2,R2 \n"
882 " VMOV D13,R2,R2 \n"
883 " VMOV D14,R2,R2 \n"
884 " VMOV D15,R2,R2 \n"
885
886 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
887 //Initialise D32 registers to 0
888 " VMOV D16,R2,R2 \n"
889 " VMOV D17,R2,R2 \n"
890 " VMOV D18,R2,R2 \n"
891 " VMOV D19,R2,R2 \n"
892 " VMOV D20,R2,R2 \n"
893 " VMOV D21,R2,R2 \n"
894 " VMOV D22,R2,R2 \n"
895 " VMOV D23,R2,R2 \n"
896 " VMOV D24,R2,R2 \n"
897 " VMOV D25,R2,R2 \n"
898 " VMOV D26,R2,R2 \n"
899 " VMOV D27,R2,R2 \n"
900 " VMOV D28,R2,R2 \n"
901 " VMOV D29,R2,R2 \n"
902 " VMOV D30,R2,R2 \n"
903 " VMOV D31,R2,R2 \n"
904 #endif
905
906 //Initialise FPSCR to a known state
907 " VMRS R1,FPSCR \n"
908 " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
909 " AND R1,R1,R2 \n"
910 " VMSR FPSCR,R1 "
911 : : : "cc", "r1", "r2"
912 );
913 }
914
915 #pragma GCC diagnostic pop
916
917 #endif /* __CMSIS_GCC_H */
918
