1 /**************************************************************************//**
2 * @file cmsis_iccarm.h
3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4 * @version V5.3.0
5 * @date 14. April 2021
6 ******************************************************************************/
7
8 //------------------------------------------------------------------------------
9 //
10 // Copyright (c) 2017-2021 IAR Systems
11 // Copyright (c) 2017-2021 Arm Limited. All rights reserved.
12 //
13 // SPDX-License-Identifier: Apache-2.0
14 //
15 // Licensed under the Apache License, Version 2.0 (the "License")
16 // you may not use this file except in compliance with the License.
17 // You may obtain a copy of the License at
18 // http://www.apache.org/licenses/LICENSE-2.0
19 //
20 // Unless required by applicable law or agreed to in writing, software
21 // distributed under the License is distributed on an "AS IS" BASIS,
22 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 // See the License for the specific language governing permissions and
24 // limitations under the License.
25 //
26 //------------------------------------------------------------------------------
27
28
29 #ifndef __CMSIS_ICCARM_H__
30 #define __CMSIS_ICCARM_H__
31
32 #ifndef __ICCARM__
33 #error This file should only be compiled by ICCARM
34 #endif
35
36 #pragma system_include
37
38 #define __IAR_FT _Pragma("inline=forced") __intrinsic
39
40 #if (__VER__ >= 8000000)
41 #define __ICCARM_V8 1
42 #else
43 #define __ICCARM_V8 0
44 #endif
45
46 #ifndef __ALIGNED
47 #if __ICCARM_V8
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #elif (__VER__ >= 7080000)
50 /* Needs IAR language extensions */
51 #define __ALIGNED(x) __attribute__((aligned(x)))
52 #else
53 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
54 #define __ALIGNED(x)
55 #endif
56 #endif
57
58
59 /* Define compiler macros for CPU architecture, used in CMSIS 5.
60 */
61 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
62 /* Macros already defined */
63 #else
64 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
65 #define __ARM_ARCH_8M_MAIN__ 1
66 #elif defined(__ARM8M_BASELINE__)
67 #define __ARM_ARCH_8M_BASE__ 1
68 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
69 #if __ARM_ARCH == 6
70 #define __ARM_ARCH_6M__ 1
71 #elif __ARM_ARCH == 7
72 #if __ARM_FEATURE_DSP
73 #define __ARM_ARCH_7EM__ 1
74 #else
75 #define __ARM_ARCH_7M__ 1
76 #endif
77 #endif /* __ARM_ARCH */
78 #endif /* __ARM_ARCH_PROFILE == 'M' */
79 #endif
80
81 /* Alternativ core deduction for older ICCARM's */
82 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85 #define __ARM_ARCH_6M__ 1
86 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87 #define __ARM_ARCH_7M__ 1
88 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89 #define __ARM_ARCH_7EM__ 1
90 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91 #define __ARM_ARCH_8M_BASE__ 1
92 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93 #define __ARM_ARCH_8M_MAIN__ 1
94 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95 #define __ARM_ARCH_8M_MAIN__ 1
96 #else
97 #error "Unknown target."
98 #endif
99 #endif
100
101
102
103 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104 #define __IAR_M0_FAMILY 1
105 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106 #define __IAR_M0_FAMILY 1
107 #else
108 #define __IAR_M0_FAMILY 0
109 #endif
110
111
112 #ifndef __ASM
113 #define __ASM __asm
114 #endif
115
116 #ifndef __COMPILER_BARRIER
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118 #endif
119
120 #ifndef __INLINE
121 #define __INLINE inline
122 #endif
123
124 #ifndef __NO_RETURN
125 #if __ICCARM_V8
126 #define __NO_RETURN __attribute__((__noreturn__))
127 #else
128 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
129 #endif
130 #endif
131
132 #ifndef __PACKED
133 #if __ICCARM_V8
134 #define __PACKED __attribute__((packed, aligned(1)))
135 #else
136 /* Needs IAR language extensions */
137 #define __PACKED __packed
138 #endif
139 #endif
140
141 #ifndef __PACKED_STRUCT
142 #if __ICCARM_V8
143 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
144 #else
145 /* Needs IAR language extensions */
146 #define __PACKED_STRUCT __packed struct
147 #endif
148 #endif
149
150 #ifndef __PACKED_UNION
151 #if __ICCARM_V8
152 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
153 #else
154 /* Needs IAR language extensions */
155 #define __PACKED_UNION __packed union
156 #endif
157 #endif
158
159 #ifndef __RESTRICT
160 #if __ICCARM_V8
161 #define __RESTRICT __restrict
162 #else
163 /* Needs IAR language extensions */
164 #define __RESTRICT restrict
165 #endif
166 #endif
167
168 #ifndef __STATIC_INLINE
169 #define __STATIC_INLINE static inline
170 #endif
171
172 #ifndef __FORCEINLINE
173 #define __FORCEINLINE _Pragma("inline=forced")
174 #endif
175
176 #ifndef __STATIC_FORCEINLINE
177 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
178 #endif
179
180 #ifndef __UNALIGNED_UINT16_READ
181 #pragma language=save
182 #pragma language=extended
__iar_uint16_read(void const * ptr)183 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
184 {
185 return *(__packed uint16_t*)(ptr);
186 }
187 #pragma language=restore
188 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
189 #endif
190
191
192 #ifndef __UNALIGNED_UINT16_WRITE
193 #pragma language=save
194 #pragma language=extended
__iar_uint16_write(void const * ptr,uint16_t val)195 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
196 {
197 *(__packed uint16_t*)(ptr) = val;;
198 }
199 #pragma language=restore
200 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
201 #endif
202
203 #ifndef __UNALIGNED_UINT32_READ
204 #pragma language=save
205 #pragma language=extended
__iar_uint32_read(void const * ptr)206 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
207 {
208 return *(__packed uint32_t*)(ptr);
209 }
210 #pragma language=restore
211 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
212 #endif
213
214 #ifndef __UNALIGNED_UINT32_WRITE
215 #pragma language=save
216 #pragma language=extended
__iar_uint32_write(void const * ptr,uint32_t val)217 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
218 {
219 *(__packed uint32_t*)(ptr) = val;;
220 }
221 #pragma language=restore
222 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
223 #endif
224
225 #ifndef __UNALIGNED_UINT32 /* deprecated */
226 #pragma language=save
227 #pragma language=extended
228 __packed struct __iar_u32 { uint32_t v; };
229 #pragma language=restore
230 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
231 #endif
232
233 #ifndef __USED
234 #if __ICCARM_V8
235 #define __USED __attribute__((used))
236 #else
237 #define __USED _Pragma("__root")
238 #endif
239 #endif
240
241 #undef __WEAK /* undo the definition from DLib_Defaults.h */
242 #ifndef __WEAK
243 #if __ICCARM_V8
244 #define __WEAK __attribute__((weak))
245 #else
246 #define __WEAK _Pragma("__weak")
247 #endif
248 #endif
249
250 #ifndef __PROGRAM_START
251 #define __PROGRAM_START __iar_program_start
252 #endif
253
254 #ifndef __INITIAL_SP
255 #define __INITIAL_SP CSTACK$$Limit
256 #endif
257
258 #ifndef __STACK_LIMIT
259 #define __STACK_LIMIT CSTACK$$Base
260 #endif
261
262 #ifndef __VECTOR_TABLE
263 #define __VECTOR_TABLE __vector_table
264 #endif
265
266 #ifndef __VECTOR_TABLE_ATTRIBUTE
267 #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
268 #endif
269
270 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
271 #ifndef __STACK_SEAL
272 #define __STACK_SEAL STACKSEAL$$Base
273 #endif
274
275 #ifndef __TZ_STACK_SEAL_SIZE
276 #define __TZ_STACK_SEAL_SIZE 8U
277 #endif
278
279 #ifndef __TZ_STACK_SEAL_VALUE
280 #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
281 #endif
282
__TZ_set_STACKSEAL_S(uint32_t * stackTop)283 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
284 *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
285 }
286 #endif
287
288 #ifndef __ICCARM_INTRINSICS_VERSION__
289 #define __ICCARM_INTRINSICS_VERSION__ 0
290 #endif
291
292 #if __ICCARM_INTRINSICS_VERSION__ == 2
293
294 #if defined(__CLZ)
295 #undef __CLZ
296 #endif
297 #if defined(__REVSH)
298 #undef __REVSH
299 #endif
300 #if defined(__RBIT)
301 #undef __RBIT
302 #endif
303 #if defined(__SSAT)
304 #undef __SSAT
305 #endif
306 #if defined(__USAT)
307 #undef __USAT
308 #endif
309
310 #include "iccarm_builtin.h"
311
312 #define __disable_irq __iar_builtin_disable_interrupt
313 #define __enable_irq __iar_builtin_enable_interrupt
314 #define __arm_rsr __iar_builtin_rsr
315 #define __arm_wsr __iar_builtin_wsr
316
317 #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2)
__disable_fault_irq()318 __IAR_FT void __disable_fault_irq()
319 {
320 __ASM volatile ("CPSID F" ::: "memory");
321 }
322
__enable_fault_irq()323 __IAR_FT void __enable_fault_irq()
324 {
325 __ASM volatile ("CPSIE F" ::: "memory");
326 }
327 #endif
328
329 #define __get_APSR() (__arm_rsr("APSR"))
330 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
331 #define __get_CONTROL() (__arm_rsr("CONTROL"))
332 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
333
334 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
335 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
336 #define __get_FPSCR() (__arm_rsr("FPSCR"))
337 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
338 #else
339 #define __get_FPSCR() ( 0 )
340 #define __set_FPSCR(VALUE) ((void)VALUE)
341 #endif
342
343 #define __get_IPSR() (__arm_rsr("IPSR"))
344 #define __get_MSP() (__arm_rsr("MSP"))
345 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
346 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
347 // without main extensions, the non-secure MSPLIM is RAZ/WI
348 #define __get_MSPLIM() (0U)
349 #else
350 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
351 #endif
352 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
353 #define __get_PSP() (__arm_rsr("PSP"))
354
355 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
356 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
357 // without main extensions, the non-secure PSPLIM is RAZ/WI
358 #define __get_PSPLIM() (0U)
359 #else
360 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
361 #endif
362
363 #define __get_xPSR() (__arm_rsr("xPSR"))
364
365 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
366 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
367
__set_CONTROL(uint32_t control)368 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
369 {
370 __arm_wsr("CONTROL", control);
371 __iar_builtin_ISB();
372 }
373
374 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
375 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
376
377 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
378 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
379 // without main extensions, the non-secure MSPLIM is RAZ/WI
380 #define __set_MSPLIM(VALUE) ((void)(VALUE))
381 #else
382 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
383 #endif
384 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
385 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
386 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
387 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
388 // without main extensions, the non-secure PSPLIM is RAZ/WI
389 #define __set_PSPLIM(VALUE) ((void)(VALUE))
390 #else
391 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
392 #endif
393
394 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
395
__TZ_set_CONTROL_NS(uint32_t control)396 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
397 {
398 __arm_wsr("CONTROL_NS", control);
399 __iar_builtin_ISB();
400 }
401
402 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
403 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
404 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
405 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
406 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
407 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
408 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
409 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
410 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
411 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
412 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
413 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
414
415 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
416 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
417 // without main extensions, the non-secure PSPLIM is RAZ/WI
418 #define __TZ_get_PSPLIM_NS() (0U)
419 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
420 #else
421 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
422 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
423 #endif
424
425 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
426 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
427
428 #define __NOP __iar_builtin_no_operation
429
430 #define __CLZ __iar_builtin_CLZ
431 #define __CLREX __iar_builtin_CLREX
432
433 #define __DMB __iar_builtin_DMB
434 #define __DSB __iar_builtin_DSB
435 #define __ISB __iar_builtin_ISB
436
437 #define __LDREXB __iar_builtin_LDREXB
438 #define __LDREXH __iar_builtin_LDREXH
439 #define __LDREXW __iar_builtin_LDREX
440
441 #define __RBIT __iar_builtin_RBIT
442 #define __REV __iar_builtin_REV
443 #define __REV16 __iar_builtin_REV16
444
__REVSH(int16_t val)445 __IAR_FT int16_t __REVSH(int16_t val)
446 {
447 return (int16_t) __iar_builtin_REVSH(val);
448 }
449
450 #define __ROR __iar_builtin_ROR
451 #define __RRX __iar_builtin_RRX
452
453 #define __SEV __iar_builtin_SEV
454
455 #if !__IAR_M0_FAMILY
456 #define __SSAT __iar_builtin_SSAT
457 #endif
458
459 #define __STREXB __iar_builtin_STREXB
460 #define __STREXH __iar_builtin_STREXH
461 #define __STREXW __iar_builtin_STREX
462
463 #if !__IAR_M0_FAMILY
464 #define __USAT __iar_builtin_USAT
465 #endif
466
467 #define __WFE __iar_builtin_WFE
468 #define __WFI __iar_builtin_WFI
469
470 #if __ARM_MEDIA__
471 #define __SADD8 __iar_builtin_SADD8
472 #define __QADD8 __iar_builtin_QADD8
473 #define __SHADD8 __iar_builtin_SHADD8
474 #define __UADD8 __iar_builtin_UADD8
475 #define __UQADD8 __iar_builtin_UQADD8
476 #define __UHADD8 __iar_builtin_UHADD8
477 #define __SSUB8 __iar_builtin_SSUB8
478 #define __QSUB8 __iar_builtin_QSUB8
479 #define __SHSUB8 __iar_builtin_SHSUB8
480 #define __USUB8 __iar_builtin_USUB8
481 #define __UQSUB8 __iar_builtin_UQSUB8
482 #define __UHSUB8 __iar_builtin_UHSUB8
483 #define __SADD16 __iar_builtin_SADD16
484 #define __QADD16 __iar_builtin_QADD16
485 #define __SHADD16 __iar_builtin_SHADD16
486 #define __UADD16 __iar_builtin_UADD16
487 #define __UQADD16 __iar_builtin_UQADD16
488 #define __UHADD16 __iar_builtin_UHADD16
489 #define __SSUB16 __iar_builtin_SSUB16
490 #define __QSUB16 __iar_builtin_QSUB16
491 #define __SHSUB16 __iar_builtin_SHSUB16
492 #define __USUB16 __iar_builtin_USUB16
493 #define __UQSUB16 __iar_builtin_UQSUB16
494 #define __UHSUB16 __iar_builtin_UHSUB16
495 #define __SASX __iar_builtin_SASX
496 #define __QASX __iar_builtin_QASX
497 #define __SHASX __iar_builtin_SHASX
498 #define __UASX __iar_builtin_UASX
499 #define __UQASX __iar_builtin_UQASX
500 #define __UHASX __iar_builtin_UHASX
501 #define __SSAX __iar_builtin_SSAX
502 #define __QSAX __iar_builtin_QSAX
503 #define __SHSAX __iar_builtin_SHSAX
504 #define __USAX __iar_builtin_USAX
505 #define __UQSAX __iar_builtin_UQSAX
506 #define __UHSAX __iar_builtin_UHSAX
507 #define __USAD8 __iar_builtin_USAD8
508 #define __USADA8 __iar_builtin_USADA8
509 #define __SSAT16 __iar_builtin_SSAT16
510 #define __USAT16 __iar_builtin_USAT16
511 #define __UXTB16 __iar_builtin_UXTB16
512 #define __UXTAB16 __iar_builtin_UXTAB16
513 #define __SXTB16 __iar_builtin_SXTB16
514 #define __SXTAB16 __iar_builtin_SXTAB16
515 #define __SMUAD __iar_builtin_SMUAD
516 #define __SMUADX __iar_builtin_SMUADX
517 #define __SMMLA __iar_builtin_SMMLA
518 #define __SMLAD __iar_builtin_SMLAD
519 #define __SMLADX __iar_builtin_SMLADX
520 #define __SMLALD __iar_builtin_SMLALD
521 #define __SMLALDX __iar_builtin_SMLALDX
522 #define __SMUSD __iar_builtin_SMUSD
523 #define __SMUSDX __iar_builtin_SMUSDX
524 #define __SMLSD __iar_builtin_SMLSD
525 #define __SMLSDX __iar_builtin_SMLSDX
526 #define __SMLSLD __iar_builtin_SMLSLD
527 #define __SMLSLDX __iar_builtin_SMLSLDX
528 #define __SEL __iar_builtin_SEL
529 #define __QADD __iar_builtin_QADD
530 #define __QSUB __iar_builtin_QSUB
531 #define __PKHBT __iar_builtin_PKHBT
532 #define __PKHTB __iar_builtin_PKHTB
533 #endif
534
535 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
536
537 #if __IAR_M0_FAMILY
538 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
539 #define __CLZ __cmsis_iar_clz_not_active
540 #define __SSAT __cmsis_iar_ssat_not_active
541 #define __USAT __cmsis_iar_usat_not_active
542 #define __RBIT __cmsis_iar_rbit_not_active
543 #define __get_APSR __cmsis_iar_get_APSR_not_active
544 #endif
545
546
547 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
548 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
549 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
550 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
551 #endif
552
553 #ifdef __INTRINSICS_INCLUDED
554 #error intrinsics.h is already included previously!
555 #endif
556
557 #include <intrinsics.h>
558
559 #if __IAR_M0_FAMILY
560 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
561 #undef __CLZ
562 #undef __SSAT
563 #undef __USAT
564 #undef __RBIT
565 #undef __get_APSR
566
__CLZ(uint32_t data)567 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
568 {
569 if (data == 0U) { return 32U; }
570
571 uint32_t count = 0U;
572 uint32_t mask = 0x80000000U;
573
574 while ((data & mask) == 0U)
575 {
576 count += 1U;
577 mask = mask >> 1U;
578 }
579 return count;
580 }
581
__RBIT(uint32_t v)582 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
583 {
584 uint8_t sc = 31U;
585 uint32_t r = v;
586 for (v >>= 1U; v; v >>= 1U)
587 {
588 r <<= 1U;
589 r |= v & 1U;
590 sc--;
591 }
592 return (r << sc);
593 }
594
__get_APSR(void)595 __STATIC_INLINE uint32_t __get_APSR(void)
596 {
597 uint32_t res;
598 __asm("MRS %0,APSR" : "=r" (res));
599 return res;
600 }
601
602 #endif
603
604 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
605 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
606 #undef __get_FPSCR
607 #undef __set_FPSCR
608 #define __get_FPSCR() (0)
609 #define __set_FPSCR(VALUE) ((void)VALUE)
610 #endif
611
612 #pragma diag_suppress=Pe940
613 #pragma diag_suppress=Pe177
614
615 #define __enable_irq __enable_interrupt
616 #define __disable_irq __disable_interrupt
617 #define __NOP __no_operation
618
619 #define __get_xPSR __get_PSR
620
621 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
622
__LDREXW(uint32_t volatile * ptr)623 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
624 {
625 return __LDREX((unsigned long *)ptr);
626 }
627
__STREXW(uint32_t value,uint32_t volatile * ptr)628 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
629 {
630 return __STREX(value, (unsigned long *)ptr);
631 }
632 #endif
633
634
635 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
636 #if (__CORTEX_M >= 0x03)
637
__RRX(uint32_t value)638 __IAR_FT uint32_t __RRX(uint32_t value)
639 {
640 uint32_t result;
641 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
642 return(result);
643 }
644
__set_BASEPRI_MAX(uint32_t value)645 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
646 {
647 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
648 }
649
650
__disable_fault_irq()651 __IAR_FT void __disable_fault_irq()
652 {
653 __ASM volatile ("CPSID F" ::: "memory");
654 }
655
__enable_fault_irq()656 __IAR_FT void __enable_fault_irq()
657 {
658 __ASM volatile ("CPSIE F" ::: "memory");
659 }
660
661 #endif /* (__CORTEX_M >= 0x03) */
662
__ROR(uint32_t op1,uint32_t op2)663 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
664 {
665 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
666 }
667
668 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
669 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
670
__get_MSPLIM(void)671 __IAR_FT uint32_t __get_MSPLIM(void)
672 {
673 uint32_t res;
674 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
675 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
676 // without main extensions, the non-secure MSPLIM is RAZ/WI
677 res = 0U;
678 #else
679 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
680 #endif
681 return res;
682 }
683
__set_MSPLIM(uint32_t value)684 __IAR_FT void __set_MSPLIM(uint32_t value)
685 {
686 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
687 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
688 // without main extensions, the non-secure MSPLIM is RAZ/WI
689 (void)value;
690 #else
691 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
692 #endif
693 }
694
__get_PSPLIM(void)695 __IAR_FT uint32_t __get_PSPLIM(void)
696 {
697 uint32_t res;
698 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
699 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
700 // without main extensions, the non-secure PSPLIM is RAZ/WI
701 res = 0U;
702 #else
703 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
704 #endif
705 return res;
706 }
707
__set_PSPLIM(uint32_t value)708 __IAR_FT void __set_PSPLIM(uint32_t value)
709 {
710 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
711 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
712 // without main extensions, the non-secure PSPLIM is RAZ/WI
713 (void)value;
714 #else
715 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
716 #endif
717 }
718
__TZ_get_CONTROL_NS(void)719 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
720 {
721 uint32_t res;
722 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
723 return res;
724 }
725
__TZ_set_CONTROL_NS(uint32_t value)726 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
727 {
728 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
729 __iar_builtin_ISB();
730 }
731
__TZ_get_PSP_NS(void)732 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
733 {
734 uint32_t res;
735 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
736 return res;
737 }
738
__TZ_set_PSP_NS(uint32_t value)739 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
740 {
741 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
742 }
743
__TZ_get_MSP_NS(void)744 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
745 {
746 uint32_t res;
747 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
748 return res;
749 }
750
__TZ_set_MSP_NS(uint32_t value)751 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
752 {
753 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
754 }
755
__TZ_get_SP_NS(void)756 __IAR_FT uint32_t __TZ_get_SP_NS(void)
757 {
758 uint32_t res;
759 __asm volatile("MRS %0,SP_NS" : "=r" (res));
760 return res;
761 }
__TZ_set_SP_NS(uint32_t value)762 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
763 {
764 __asm volatile("MSR SP_NS,%0" :: "r" (value));
765 }
766
__TZ_get_PRIMASK_NS(void)767 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
768 {
769 uint32_t res;
770 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
771 return res;
772 }
773
__TZ_set_PRIMASK_NS(uint32_t value)774 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
775 {
776 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
777 }
778
__TZ_get_BASEPRI_NS(void)779 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
780 {
781 uint32_t res;
782 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
783 return res;
784 }
785
__TZ_set_BASEPRI_NS(uint32_t value)786 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
787 {
788 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
789 }
790
__TZ_get_FAULTMASK_NS(void)791 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
792 {
793 uint32_t res;
794 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
795 return res;
796 }
797
__TZ_set_FAULTMASK_NS(uint32_t value)798 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
799 {
800 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
801 }
802
__TZ_get_PSPLIM_NS(void)803 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
804 {
805 uint32_t res;
806 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
807 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
808 // without main extensions, the non-secure PSPLIM is RAZ/WI
809 res = 0U;
810 #else
811 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
812 #endif
813 return res;
814 }
815
__TZ_set_PSPLIM_NS(uint32_t value)816 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
817 {
818 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
819 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
820 // without main extensions, the non-secure PSPLIM is RAZ/WI
821 (void)value;
822 #else
823 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
824 #endif
825 }
826
__TZ_get_MSPLIM_NS(void)827 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
828 {
829 uint32_t res;
830 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
831 return res;
832 }
833
__TZ_set_MSPLIM_NS(uint32_t value)834 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
835 {
836 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
837 }
838
839 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
840
841 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
842
843 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
844
845 #if __IAR_M0_FAMILY
__SSAT(int32_t val,uint32_t sat)846 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
847 {
848 if ((sat >= 1U) && (sat <= 32U))
849 {
850 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
851 const int32_t min = -1 - max ;
852 if (val > max)
853 {
854 return max;
855 }
856 else if (val < min)
857 {
858 return min;
859 }
860 }
861 return val;
862 }
863
__USAT(int32_t val,uint32_t sat)864 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
865 {
866 if (sat <= 31U)
867 {
868 const uint32_t max = ((1U << sat) - 1U);
869 if (val > (int32_t)max)
870 {
871 return max;
872 }
873 else if (val < 0)
874 {
875 return 0U;
876 }
877 }
878 return (uint32_t)val;
879 }
880 #endif
881
882 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
883
__LDRBT(volatile uint8_t * addr)884 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
885 {
886 uint32_t res;
887 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
888 return ((uint8_t)res);
889 }
890
__LDRHT(volatile uint16_t * addr)891 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
892 {
893 uint32_t res;
894 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
895 return ((uint16_t)res);
896 }
897
__LDRT(volatile uint32_t * addr)898 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
899 {
900 uint32_t res;
901 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
902 return res;
903 }
904
__STRBT(uint8_t value,volatile uint8_t * addr)905 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
906 {
907 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
908 }
909
__STRHT(uint16_t value,volatile uint16_t * addr)910 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
911 {
912 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
913 }
914
__STRT(uint32_t value,volatile uint32_t * addr)915 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
916 {
917 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
918 }
919
920 #endif /* (__CORTEX_M >= 0x03) */
921
922 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
923 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
924
925
__LDAB(volatile uint8_t * ptr)926 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
927 {
928 uint32_t res;
929 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
930 return ((uint8_t)res);
931 }
932
__LDAH(volatile uint16_t * ptr)933 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
934 {
935 uint32_t res;
936 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
937 return ((uint16_t)res);
938 }
939
__LDA(volatile uint32_t * ptr)940 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
941 {
942 uint32_t res;
943 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
944 return res;
945 }
946
__STLB(uint8_t value,volatile uint8_t * ptr)947 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
948 {
949 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
950 }
951
__STLH(uint16_t value,volatile uint16_t * ptr)952 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
953 {
954 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
955 }
956
__STL(uint32_t value,volatile uint32_t * ptr)957 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
958 {
959 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
960 }
961
__LDAEXB(volatile uint8_t * ptr)962 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
963 {
964 uint32_t res;
965 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
966 return ((uint8_t)res);
967 }
968
__LDAEXH(volatile uint16_t * ptr)969 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
970 {
971 uint32_t res;
972 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
973 return ((uint16_t)res);
974 }
975
__LDAEX(volatile uint32_t * ptr)976 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
977 {
978 uint32_t res;
979 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
980 return res;
981 }
982
__STLEXB(uint8_t value,volatile uint8_t * ptr)983 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
984 {
985 uint32_t res;
986 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
987 return res;
988 }
989
__STLEXH(uint16_t value,volatile uint16_t * ptr)990 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
991 {
992 uint32_t res;
993 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
994 return res;
995 }
996
__STLEX(uint32_t value,volatile uint32_t * ptr)997 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
998 {
999 uint32_t res;
1000 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
1001 return res;
1002 }
1003
1004 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
1005
1006 #undef __IAR_FT
1007 #undef __IAR_M0_FAMILY
1008 #undef __ICCARM_V8
1009
1010 #pragma diag_default=Pe940
1011 #pragma diag_default=Pe177
1012
1013 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1014
1015 #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1016
1017 #endif /* __CMSIS_ICCARM_H__ */
1018
