1/*
2 * Copyright (c) 2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19/* ----------------------------------------------------------------------------
20  Stack seal size definition
21 *----------------------------------------------------------------------------*/
22#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
23#define __STACKSEAL_SIZE   ( 8 )
24#else
25#define __STACKSEAL_SIZE   ( 0 )
26#endif
27
28/* ----------------------------------------------------------------------------
29  Memory definition
30 *----------------------------------------------------------------------------*/
31MEMORY
32{
33  ROM0  (rx)  : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE
34#if __ROM1_SIZE > 0
35  ROM1  (rx)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
36#endif
37#if __ROM2_SIZE > 0
38  ROM2  (rx)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
39#endif
40#if __ROM3_SIZE > 0
41  ROM3  (rx)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
42#endif
43
44  RAM0  (rwx) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE
45#if __RAM1_SIZE > 0
46  RAM1  (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
47#endif
48#if __RAM2_SIZE > 0
49  RAM2  (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
50#endif
51#if __RAM3_SIZE > 0
52  RAM3  (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
53#endif
54}
55
56/* Linker script to place sections and symbol values. Should be used together
57 * with other linker script that defines memory regions FLASH and RAM.
58 * It references following symbols, which must be defined in code:
59 *   Reset_Handler : Entry of reset handler
60 *
61 * It defines following symbols, which code can use without definition:
62 *   __exidx_start
63 *   __exidx_end
64 *   __copy_table_start__
65 *   __copy_table_end__
66 *   __zero_table_start__
67 *   __zero_table_end__
68 *   __etext          (deprecated)
69 *   __data_start__
70 *   __preinit_array_start
71 *   __preinit_array_end
72 *   __init_array_start
73 *   __init_array_end
74 *   __fini_array_start
75 *   __fini_array_end
76 *   __data_end__
77 *   __bss_start__
78 *   __bss_end__
79 *   __end__
80 *   end
81 *   __HeapLimit
82 *   __StackLimit
83 *   __StackTop
84 *   __stack
85 */
86ENTRY(Reset_Handler)
87
88SECTIONS
89{
90  .text :
91  {
92    KEEP(*(.vectors))
93    *(.text*)
94
95    KEEP(*(.init))
96    KEEP(*(.fini))
97
98    /* .ctors */
99    *crtbegin.o(.ctors)
100    *crtbegin?.o(.ctors)
101    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
102    *(SORT(.ctors.*))
103    *(.ctors)
104
105    /* .dtors */
106    *crtbegin.o(.dtors)
107    *crtbegin?.o(.dtors)
108    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
109    *(SORT(.dtors.*))
110    *(.dtors)
111
112    /* *(.rodata*) */
113
114    KEEP(*(.eh_frame*))
115  } > ROM0
116
117#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
118  .gnu.sgstubs :
119  {
120    . = ALIGN(32);
121  } > ROM0
122#endif
123
124  .ARM.extab :
125  {
126    *(.ARM.extab* .gnu.linkonce.armextab.*)
127  } > ROM0
128
129  __exidx_start = .;
130  .ARM.exidx :
131  {
132    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
133  } > ROM0
134  __exidx_end = .;
135
136  .copy.table :
137  {
138    . = ALIGN(4);
139    __copy_table_start__ = .;
140
141    LONG (LOADADDR(.data))
142    LONG (ADDR(.data))
143    LONG (SIZEOF(.data) / 4)
144
145    /* Add each additional data section here */
146/*
147    LONG (LOADADDR(.data2))
148    LONG (ADDR(.data2))
149    LONG (SIZEOF(.data2) / 4)
150*/
151    __copy_table_end__ = .;
152  } > ROM0
153
154  .zero.table :
155  {
156    . = ALIGN(4);
157    __zero_table_start__ = .;
158
159/*  .bss initialization to zero is already done during C Run-Time Startup.
160    LONG (ADDR(.bss))
161    LONG (SIZEOF(.bss) / 4)
162*/
163
164    /* Add each additional bss section here */
165/*
166    LONG (ADDR(.bss2))
167    LONG (SIZEOF(.bss2) / 4)
168*/
169    __zero_table_end__ = .;
170  } > ROM0
171
172  /*
173   * This __etext variable is kept for backward compatibility with older,
174   * ASM based startup files.
175   */
176  PROVIDE(__etext = LOADADDR(.data));
177
178  .data : ALIGN(4)
179  {
180    __data_start__ = .;
181    *(vtable)
182    *(.data)
183    *(.data.*)
184    *(.rodata*)
185
186    . = ALIGN(4);
187    /* preinit data */
188    PROVIDE_HIDDEN (__preinit_array_start = .);
189    KEEP(*(.preinit_array))
190    PROVIDE_HIDDEN (__preinit_array_end = .);
191
192    . = ALIGN(4);
193    /* init data */
194    PROVIDE_HIDDEN (__init_array_start = .);
195    KEEP(*(SORT(.init_array.*)))
196    KEEP(*(.init_array))
197    PROVIDE_HIDDEN (__init_array_end = .);
198
199    . = ALIGN(4);
200    /* finit data */
201    PROVIDE_HIDDEN (__fini_array_start = .);
202    KEEP(*(SORT(.fini_array.*)))
203    KEEP(*(.fini_array))
204    PROVIDE_HIDDEN (__fini_array_end = .);
205
206    KEEP(*(.jcr*))
207    . = ALIGN(4);
208    /* All data end */
209    __data_end__ = .;
210
211  } > RAM0 AT > ROM0
212
213  /*
214   * Secondary data section, optional
215   *
216   * Remember to add each additional data section
217   * to the .copy.table above to assure proper
218   * initialization during startup.
219   */
220/*
221  .data2 : ALIGN(4)
222  {
223    . = ALIGN(4);
224    __data2_start__ = .;
225    *(.data2)
226    *(.data2.*)
227    . = ALIGN(4);
228    __data2_end__ = .;
229
230  } > RAM1 AT > ROM0
231*/
232
233  .bss :
234  {
235    . = ALIGN(4);
236    __bss_start__ = .;
237    *(.bss)
238    *(.bss.*)
239    *(COMMON)
240    . = ALIGN(4);
241    __bss_end__ = .;
242  } > RAM0 AT > RAM0
243
244  /*
245   * Secondary bss section, optional
246   *
247   * Remember to add each additional bss section
248   * to the .zero.table above to assure proper
249   * initialization during startup.
250   */
251/*
252  .bss2 :
253  {
254    . = ALIGN(4);
255    __bss2_start__ = .;
256    *(.bss2)
257    *(.bss2.*)
258    . = ALIGN(4);
259    __bss2_end__ = .;
260  } > RAM1 AT > RAM1
261*/
262
263  .heap (NOLOAD) :
264  {
265    . = ALIGN(8);
266    __end__ = .;
267    PROVIDE(end = .);
268    . = . + HEAP_SIZE;
269    . = ALIGN(8);
270    __HeapLimit = .;
271  } > RAM0
272
273  .stack (ORIGIN(RAM0) + LENGTH(RAM0) - STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) :
274  {
275    . = ALIGN(8);
276    __StackLimit = .;
277    . = . + STACK_SIZE;
278    . = ALIGN(8);
279    __StackTop = .;
280  } > RAM0
281  PROVIDE(__stack = __StackTop);
282
283#if __STACKSEAL_SIZE > 0
284  .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) :
285  {
286    . = ALIGN(8);
287    __StackSeal = .;
288    . = . + 8;
289    . = ALIGN(8);
290  } > RAM0
291#endif
292
293  /* Check if data + heap + stack exceeds RAM limit */
294  ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
295}
296