1 /*
2 * Copyright (c) 2022-2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c
21 * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c
22 */
23
24 #include "SSE300MPS3.h"
25
26 /*----------------------------------------------------------------------------
27 External References
28 *----------------------------------------------------------------------------*/
29 extern uint32_t __INITIAL_SP;
30 extern uint32_t __STACK_LIMIT;
31 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
32 extern uint64_t __STACK_SEAL;
33 #endif
34
35 extern void __PROGRAM_START(void) __NO_RETURN;
36
37 /*----------------------------------------------------------------------------
38 Internal References
39 *----------------------------------------------------------------------------*/
40 void Reset_Handler (void) __NO_RETURN;
41
42 /*----------------------------------------------------------------------------
43 Exception / Interrupt Handler
44 *----------------------------------------------------------------------------*/
45 #define DEFAULT_IRQ_HANDLER(handler_name) \
46 void __WEAK handler_name(void) __NO_RETURN; \
47 void handler_name(void) { \
48 while(1); \
49 }
50
51 /* Exceptions */
52 DEFAULT_IRQ_HANDLER(NMI_Handler)
53 DEFAULT_IRQ_HANDLER(HardFault_Handler)
54 DEFAULT_IRQ_HANDLER(MemManage_Handler)
55 DEFAULT_IRQ_HANDLER(BusFault_Handler)
56 DEFAULT_IRQ_HANDLER(UsageFault_Handler)
57 DEFAULT_IRQ_HANDLER(SecureFault_Handler)
58 DEFAULT_IRQ_HANDLER(SVC_Handler)
59 DEFAULT_IRQ_HANDLER(DebugMon_Handler)
60 DEFAULT_IRQ_HANDLER(PendSV_Handler)
61 DEFAULT_IRQ_HANDLER(SysTick_Handler)
62
63 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler)
64 DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
65 DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
66 DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
67 DEFAULT_IRQ_HANDLER(TIMER1_Handler)
68 DEFAULT_IRQ_HANDLER(TIMER2_Handler)
69 DEFAULT_IRQ_HANDLER(MPC_Handler)
70 DEFAULT_IRQ_HANDLER(PPC_Handler)
71 DEFAULT_IRQ_HANDLER(MSC_Handler)
72 DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
73 DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
74 DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
75 DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
76 DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
77 DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler)
78 DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler)
79 DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler)
80
81 DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
82 DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
83 DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
84 DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
85 DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
86 DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
87 DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
88 DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
89 DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
90 DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
91 DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
92 DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
93 DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
94 DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
95 DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
96 DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
97 DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
98 DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
99 DEFAULT_IRQ_HANDLER(I2S_Handler)
100 DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
101 DEFAULT_IRQ_HANDLER(USB_Handler)
102 DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
103 DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
104 DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
105 DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
106 #ifdef CORSTONE300_AN547
107 DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler)
108 DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler)
109 DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler)
110 DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler)
111 DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler)
112 DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler)
113 DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler)
114 DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler)
115 DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler)
116 #endif
117 DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
118 DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
119 DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
120 DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
121 DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
122 DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
123 DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
124 DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
125 DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
126 DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
127 DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
128 DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
129 DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
130 DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
131 DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
132 DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
133 DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
134 DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
135 DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
136 DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
137 DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
138 DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
139 DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
140 DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
141 DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
142 DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
143 DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
144 DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
145 DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
146 DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
147 DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
148 DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
149 DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
150 DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
151 DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
152 DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
153 DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
154 DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
155 DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
156 DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
157 DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
158 DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
159 DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
160 DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
161 DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
162 DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
163 DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
164 DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
165 DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
166 DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
167 DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
168 DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
169 DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
170 DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
171 DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
172 DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
173 DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
174 DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
175 DEFAULT_IRQ_HANDLER(UART5_Handler)
176
177 /*----------------------------------------------------------------------------
178 Exception / Interrupt Vector table
179 *----------------------------------------------------------------------------*/
180
181 #if defined ( __GNUC__ )
182 #pragma GCC diagnostic push
183 #pragma GCC diagnostic ignored "-Wpedantic"
184 #endif
185
186 extern const VECTOR_TABLE_Type __VECTOR_TABLE[];
187 const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = {
188 (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
189 Reset_Handler, /* Reset Handler */
190 NMI_Handler, /* -14: NMI Handler */
191 HardFault_Handler, /* -13: Hard Fault Handler */
192 MemManage_Handler, /* -12: MPU Fault Handler */
193 BusFault_Handler, /* -11: Bus Fault Handler */
194 UsageFault_Handler, /* -10: Usage Fault Handler */
195 SecureFault_Handler, /* -9: Secure Fault Handler */
196 0, /* Reserved */
197 0, /* Reserved */
198 0, /* Reserved */
199 SVC_Handler, /* -5: SVCall Handler */
200 DebugMon_Handler, /* -4: Debug Monitor Handler */
201 0, /* Reserved */
202 PendSV_Handler, /* -2: PendSV Handler */
203 SysTick_Handler, /* -1: SysTick Handler */
204
205 NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
206 NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
207 SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
208 TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
209 TIMER1_Handler, /* 4: TIMER 1 Handler */
210 TIMER2_Handler, /* 5: TIMER 2 Handler */
211 0, /* 6: Reserved */
212 0, /* 7: Reserved */
213 0, /* 8: Reserved */
214 MPC_Handler, /* 9: MPC Combined (Secure) Handler */
215 PPC_Handler, /* 10: PPC Combined (Secure) Handler */
216 MSC_Handler, /* 11: MSC Combined (Secure) Handler */
217 BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
218 0, /* 13: Reserved */
219 MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
220 SYS_PPU_Handler, /* 15: SYS PPU Handler */
221 CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
222 0, /* 17: Reserved */
223 0, /* 18: Reserved */
224 0, /* 19: Reserved */
225 0, /* 20: Reserved */
226 0, /* 21: Reserved */
227 0, /* 22: Reserved */
228 0, /* 23: Reserved */
229 0, /* 24: Reserved */
230 0, /* 25: Reserved */
231 DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
232 TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */
233 CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */
234 CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */
235 0, /* 30: Reserved */
236 0, /* 31: Reserved */
237
238 /* External interrupts */
239 System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
240 UARTRX0_Handler, /* 33: UART 0 RX Handler */
241 UARTTX0_Handler, /* 34: UART 0 TX Handler */
242 UARTRX1_Handler, /* 35: UART 1 RX Handler */
243 UARTTX1_Handler, /* 36: UART 1 TX Handler */
244 UARTRX2_Handler, /* 37: UART 2 RX Handler */
245 UARTTX2_Handler, /* 38: UART 2 TX Handler */
246 UARTRX3_Handler, /* 39: UART 3 RX Handler */
247 UARTTX3_Handler, /* 40: UART 3 TX Handler */
248 UARTRX4_Handler, /* 41: UART 4 RX Handler */
249 UARTTX4_Handler, /* 42: UART 4 TX Handler */
250 UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
251 UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
252 UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
253 UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
254 UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
255 UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
256 ETHERNET_Handler, /* 49: Ethernet Handler */
257 I2S_Handler, /* 50: Audio I2S Handler */
258 TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
259 USB_Handler, /* 52: USB Handler */
260 SPI_ADC_Handler, /* 53: SPI ADC Handler */
261 SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
262 SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
263 ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
264 #ifdef CORSTONE300_AN547
265 0, /* 57: Reserved */
266 0, /* 58: Reserved */
267 0, /* 59: Reserved */
268 DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */
269 DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */
270 DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */
271 DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */
272 DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */
273 DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */
274 DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */
275 DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */
276 DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */
277 #else
278 0, /* 57: Reserved */
279 0, /* 58: Reserved */
280 0, /* 59: Reserved */
281 0, /* 60: Reserved */
282 0, /* 61: Reserved */
283 0, /* 62: Reserved */
284 0, /* 63: Reserved */
285 0, /* 64: Reserved */
286 0, /* 65: Reserved */
287 0, /* 66: Reserved */
288 0, /* 67: Reserved */
289 0, /* 68: Reserved */
290 #endif
291 GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
292 GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
293 GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
294 GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
295 GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
296 GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
297 GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
298 GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
299 GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
300 GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
301 GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
302 GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
303 GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
304 GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
305 GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
306 GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
307 GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
308 GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
309 GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
310 GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
311 GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
312 GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
313 GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
314 GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
315 GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
316 GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
317 GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
318 GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
319 GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
320 GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
321 GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
322 GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
323 GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
324 GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
325 GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
326 GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
327 GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
328 GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
329 GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
330 GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
331 GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
332 GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
333 GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
334 GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
335 GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
336 GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
337 GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
338 GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
339 GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
340 GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
341 GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
342 GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
343 GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
344 GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
345 GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
346 GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
347 UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
348 UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
349 UART5_Handler, /* 127: UART 5 combined Interrupt */
350 0, /* 128: Reserved */
351 0, /* 129: Reserved */
352 0, /* 130: Reserved */
353 };
354
355 #if defined ( __GNUC__ )
356 #pragma GCC diagnostic pop
357 #endif
358
359 /*----------------------------------------------------------------------------
360 Reset Handler called on controller reset
361 *----------------------------------------------------------------------------*/
Reset_Handler(void)362 void Reset_Handler(void)
363 {
364 __set_PSP((uint32_t)(&__INITIAL_SP));
365
366 __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
367 __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
368
369 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
370 __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
371 #endif
372
373 SystemInit(); /* CMSIS System Initialization */
374 __PROGRAM_START(); /* Enter PreMain (C library entry point) */
375 }
376
