1#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc
2
3;/*
4; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
5; *
6; * Licensed under the Apache License, Version 2.0 (the "License");
7; * you may not use this file except in compliance with the License.
8; * You may obtain a copy of the License at
9; *
10; *     http://www.apache.org/licenses/LICENSE-2.0
11; *
12; * Unless required by applicable law or agreed to in writing, software
13; * distributed under the License is distributed on an "AS IS" BASIS,
14; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15; * See the License for the specific language governing permissions and
16; * limitations under the License.
17; *
18; */
19
20#include "region_defs.h"
21
22LR_CODE S_DDR4_START {
23    ER_CODE S_DDR4_START {
24        *.o (RESET +First)
25        .ANY (+RO)
26    }
27
28    /*
29     * Place the CMSE Veneers (containing the SG instruction) after the code, in
30     * a separate 32 bytes aligned region so that the SAU can programmed to just
31     * set this region as Non-Secure Callable. The maximum size of this
32     * executable region makes it only used the space left over by the ER_CODE
33     * region so that you can rely on code+veneer size combined will not exceed
34     * the S_CODE_SIZE value. We also substract from the available space the
35     * area used to align this section on 32 bytes boundary (for SAU conf).
36     */
37    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
38        *(Veneer$$CMSE)
39    }
40    /*
41     * This dummy region ensures that the next one will be aligned on a 32 bytes
42     * boundary, so that the following region will not be mistakenly configured
43     * as Non-Secure Callable by the SAU.
44     */
45    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}
46
47    /* This empty, zero long execution region is here to mark the limit address
48     * of the last execution region that is allocated in SRAM.
49     */
50    CODE_WATERMARK +0 EMPTY 0x0 {
51    }
52    /* Make sure that the sections allocated in the SRAM does not exceed the
53     * size of the SRAM available.
54     */
55    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_DDR4_START + S_DDR4_SIZE)
56
57    ER_DATA +0 ALIGN 32 {
58        .ANY (+ZI +RW)
59    }
60
61    #if HEAP_SIZE > 0
62    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
63    }
64    #endif
65
66    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
67    }
68
69    /* This empty, zero long execution region is here to mark the limit address
70     * of the last execution region that is allocated in SRAM.
71     */
72    SRAM_WATERMARK +0 EMPTY 0x0 {
73    }
74    /* Make sure that the sections allocated in the SRAM does not exceed the
75     * size of the SRAM available.
76     */
77    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DDR4_START + S_DDR4_SIZE)
78}
79