1/****************************************************************************** 2 * @file gcc_arm.ld 3 * @brief GNU Linker Script for Cortex-M based device 4 * @version V2.1.0 5 * @date 04. August 2020 6 ******************************************************************************/ 7/* 8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25/* 26 *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 27 */ 28 29/*---------------------- Flash Configuration ---------------------------------- 30 <h> Flash Configuration 31 <o0> Flash Base Address <0x0-0xFFFFFFFF:8> 32 <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 33 </h> 34 -----------------------------------------------------------------------------*/ 35__ROM_BASE = 0x00000000; 36__ROM_SIZE = 0x00100000; 37 38/*--------------------- Embedded RAM Configuration ---------------------------- 39 <h> RAM Configuration 40 <o0> RAM Base Address <0x0-0xFFFFFFFF:8> 41 <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 42 </h> 43 -----------------------------------------------------------------------------*/ 44__RAM_BASE = 0x20000000; 45__RAM_SIZE = 0x00300000; 46 47/*--------------------- Stack / Heap Configuration ---------------------------- 48 <h> Stack / Heap Configuration 49 <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 50 <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 51 </h> 52 -----------------------------------------------------------------------------*/ 53__STACK_SIZE = 0x00002000; 54__HEAP_SIZE = 0x00100000; 55 56/* 57 *-------------------- <<< end of configuration section >>> ------------------- 58 */ 59 60MEMORY 61{ 62 FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE 63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE 64} 65 66/* Linker script to place sections and symbol values. Should be used together 67 * with other linker script that defines memory regions FLASH and RAM. 68 * It references following symbols, which must be defined in code: 69 * Reset_Handler : Entry of reset handler 70 * 71 * It defines following symbols, which code can use without definition: 72 * __exidx_start 73 * __exidx_end 74 * __copy_table_start__ 75 * __copy_table_end__ 76 * __zero_table_start__ 77 * __zero_table_end__ 78 * __etext 79 * __data_start__ 80 * __preinit_array_start 81 * __preinit_array_end 82 * __init_array_start 83 * __init_array_end 84 * __fini_array_start 85 * __fini_array_end 86 * __data_end__ 87 * __bss_start__ 88 * __bss_end__ 89 * __end__ 90 * end 91 * __HeapLimit 92 * __StackLimit 93 * __StackTop 94 * __stack 95 */ 96ENTRY(Reset_Handler) 97 98SECTIONS 99{ 100 .text : 101 { 102 KEEP(*(.vectors)) 103 *(.text*) 104 105 KEEP(*(.init)) 106 KEEP(*(.fini)) 107 108 /* .ctors */ 109 *crtbegin.o(.ctors) 110 *crtbegin?.o(.ctors) 111 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) 112 *(SORT(.ctors.*)) 113 *(.ctors) 114 115 /* .dtors */ 116 *crtbegin.o(.dtors) 117 *crtbegin?.o(.dtors) 118 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) 119 *(SORT(.dtors.*)) 120 *(.dtors) 121 122 *(.rodata*) 123 124 KEEP(*(.eh_frame*)) 125 } > FLASH 126 127 /* 128 * SG veneers: 129 * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address 130 * must be set, either with the command line option �--section-start� or in a linker script, 131 * to indicate where to place these veneers in memory. 132 */ 133/* 134 .gnu.sgstubs : 135 { 136 . = ALIGN(32); 137 } > FLASH 138*/ 139 .ARM.extab : 140 { 141 *(.ARM.extab* .gnu.linkonce.armextab.*) 142 } > FLASH 143 144 __exidx_start = .; 145 .ARM.exidx : 146 { 147 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 148 } > FLASH 149 __exidx_end = .; 150 151 .copy.table : 152 { 153 . = ALIGN(4); 154 __copy_table_start__ = .; 155 156 LONG (__etext) 157 LONG (__data_start__) 158 LONG ((__data_end__ - __data_start__) / 4) 159 160 /* Add each additional data section here */ 161/* 162 LONG (__etext2) 163 LONG (__data2_start__) 164 LONG ((__data2_end__ - __data2_start__) / 4) 165*/ 166 __copy_table_end__ = .; 167 } > FLASH 168 169 .zero.table : 170 { 171 . = ALIGN(4); 172 __zero_table_start__ = .; 173 /* Add each additional bss section here */ 174/* 175 LONG (__bss2_start__) 176 LONG ((__bss2_end__ - __bss2_start__) / 4) 177*/ 178 __zero_table_end__ = .; 179 } > FLASH 180 181 /** 182 * Location counter can end up 2byte aligned with narrow Thumb code but 183 * __etext is assumed by startup code to be the LMA of a section in RAM 184 * which must be 4byte aligned 185 */ 186 __etext = ALIGN (4); 187 188 .data : AT (__etext) 189 { 190 __data_start__ = .; 191 *(vtable) 192 *(.data) 193 *(.data.*) 194 195 . = ALIGN(4); 196 /* preinit data */ 197 PROVIDE_HIDDEN (__preinit_array_start = .); 198 KEEP(*(.preinit_array)) 199 PROVIDE_HIDDEN (__preinit_array_end = .); 200 201 . = ALIGN(4); 202 /* init data */ 203 PROVIDE_HIDDEN (__init_array_start = .); 204 KEEP(*(SORT(.init_array.*))) 205 KEEP(*(.init_array)) 206 PROVIDE_HIDDEN (__init_array_end = .); 207 208 . = ALIGN(4); 209 /* finit data */ 210 PROVIDE_HIDDEN (__fini_array_start = .); 211 KEEP(*(SORT(.fini_array.*))) 212 KEEP(*(.fini_array)) 213 PROVIDE_HIDDEN (__fini_array_end = .); 214 215 KEEP(*(.jcr*)) 216 . = ALIGN(4); 217 /* All data end */ 218 __data_end__ = .; 219 220 } > RAM 221 222 /* 223 * Secondary data section, optional 224 * 225 * Remember to add each additional data section 226 * to the .copy.table above to asure proper 227 * initialization during startup. 228 */ 229/* 230 __etext2 = ALIGN (4); 231 232 .data2 : AT (__etext2) 233 { 234 . = ALIGN(4); 235 __data2_start__ = .; 236 *(.data2) 237 *(.data2.*) 238 . = ALIGN(4); 239 __data2_end__ = .; 240 241 } > RAM2 242*/ 243 244 .bss : 245 { 246 . = ALIGN(4); 247 __bss_start__ = .; 248 *(.bss) 249 *(.bss.*) 250 *(COMMON) 251 . = ALIGN(4); 252 __bss_end__ = .; 253 } > RAM AT > RAM 254 255 /* 256 * Secondary bss section, optional 257 * 258 * Remember to add each additional bss section 259 * to the .zero.table above to asure proper 260 * initialization during startup. 261 */ 262/* 263 .bss2 : 264 { 265 . = ALIGN(4); 266 __bss2_start__ = .; 267 *(.bss2) 268 *(.bss2.*) 269 . = ALIGN(4); 270 __bss2_end__ = .; 271 } > RAM2 AT > RAM2 272*/ 273 274 .heap (COPY) : 275 { 276 . = ALIGN(8); 277 __end__ = .; 278 PROVIDE(end = .); 279 . = . + __HEAP_SIZE; 280 . = ALIGN(8); 281 __HeapLimit = .; 282 } > RAM 283 284 .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : 285 { 286 . = ALIGN(8); 287 __StackLimit = .; 288 . = . + __STACK_SIZE; 289 . = ALIGN(8); 290 __StackTop = .; 291 } > RAM 292 PROVIDE(__stack = __StackTop); 293 294 /* Check if data + heap + stack exceeds RAM limit */ 295 ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") 296} 297