1#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc
2; command above MUST be in first line (no comment above!)
3
4;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
5;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse
6
7
8/*
9;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
10*/
11
12/*--------------------- Flash Configuration ----------------------------------
13; <h> Flash Configuration
14;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
15;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
16; </h>
17 *----------------------------------------------------------------------------*/
18#define __ROM_BASE      0x00000000
19#define __ROM_SIZE      0x00100000
20
21/*--------------------- Embedded RAM Configuration ---------------------------
22; <h> RAM Configuration
23;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
24;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
25; </h>
26 *----------------------------------------------------------------------------*/
27#define __RAM_BASE      0x20000000
28#define __RAM_SIZE      0x00300000
29
30/*--------------------- Stack / Heap Configuration ---------------------------
31; <h> Stack / Heap Configuration
32;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
33;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
34; </h>
35 *----------------------------------------------------------------------------*/
36#define __STACK_SIZE    0x00002000
37#define __HEAP_SIZE     0x00100000
38
39/*--------------------- CMSE Veneer Configuration ---------------------------
40; <h> CMSE Veneer Configuration
41;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
42; </h>
43 *----------------------------------------------------------------------------*/
44#define __CMSEVENEER_SIZE    0x200
45
46/*
47;------------- <<< end of configuration section >>> ---------------------------
48*/
49
50
51/*----------------------------------------------------------------------------
52  User Stack & Heap boundary definition
53 *----------------------------------------------------------------------------*/
54#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
55#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */
56
57/* ----------------------------------------------------------------------------
58  Stack seal size definition
59 *----------------------------------------------------------------------------*/
60#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
61#define __STACKSEAL_SIZE   ( 8 )
62#else
63#define __STACKSEAL_SIZE   ( 0 )
64#endif
65
66
67/*----------------------------------------------------------------------------
68  Region base & size definition
69 *----------------------------------------------------------------------------*/
70#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
71#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
72#define __CV_SIZE          ( __CMSEVENEER_SIZE )
73#else
74#define __CV_SIZE          ( 0 )
75#endif
76
77#define __RO_BASE          ( __ROM_BASE )
78#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )
79
80#define __RW_BASE          ( __RAM_BASE )
81#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
82
83
84/*----------------------------------------------------------------------------
85  Scatter Region definition
86 *----------------------------------------------------------------------------*/
87LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
88  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
89   *.o (RESET, +First)
90   *(InRoot$$Sections)
91   .ANY (+RO)
92   .ANY (+XO)
93  }
94
95  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data
96   .ANY (+RW +ZI)
97  }
98
99#if __HEAP_SIZE > 0
100  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
101  }
102#endif
103
104  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
105  }
106
107#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
108  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack
109  }
110#endif
111}
112
113#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
114LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
115  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
116   *(Veneer$$CMSE)
117  }
118}
119#endif
120