1 /**************************************************************************//**
2 * @file mmu_ARMCA9.c
3 * @brief MMU Configuration for Arm Cortex-A9 Device Series
4 * @version V1.2.0
5 * @date 15. May 2019
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /*
11 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the License); you may
16 * not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
23 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 */
27
28 /* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
29
30 Memory Type
31 0xffffffff |--------------------------| ------------
32 | FLAG SYNC | Device Memory
33 0xfffff000 |--------------------------| ------------
34 | Fault | Fault
35 0xfff00000 |--------------------------| ------------
36 | | Normal
37 | |
38 | Daughterboard |
39 | memory |
40 | |
41 0x80505000 |--------------------------| ------------
42 |TTB (L2 Sync Flags ) 4k | Normal
43 0x80504C00 |--------------------------| ------------
44 |TTB (L2 Peripherals-B) 16k| Normal
45 0x80504800 |--------------------------| ------------
46 |TTB (L2 Peripherals-A) 16k| Normal
47 0x80504400 |--------------------------| ------------
48 |TTB (L2 Priv Periphs) 4k | Normal
49 0x80504000 |--------------------------| ------------
50 | TTB (L1 Descriptors) | Normal
51 0x80500000 |--------------------------| ------------
52 | Stack | Normal
53 |--------------------------| ------------
54 | Heap | Normal
55 0x80400000 |--------------------------| ------------
56 | ZI Data | Normal
57 0x80300000 |--------------------------| ------------
58 | RW Data | Normal
59 0x80200000 |--------------------------| ------------
60 | RO Data | Normal
61 |--------------------------| ------------
62 | RO Code | USH Normal
63 0x80000000 |--------------------------| ------------
64 | Daughterboard | Fault
65 | HSB AXI buses |
66 0x40000000 |--------------------------| ------------
67 | Daughterboard | Fault
68 | test chips peripherals |
69 0x2c002000 |--------------------------| ------------
70 | Private Address | Device Memory
71 0x2c000000 |--------------------------| ------------
72 | Daughterboard | Fault
73 | test chips peripherals |
74 0x20000000 |--------------------------| ------------
75 | Peripherals | Device Memory RW/RO
76 | | & Fault
77 0x00000000 |--------------------------|
78 */
79
80 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
81 // Write-Through support *not* available
82 // Write-Back support available.
83 // Read allocation support available.
84 // Write allocation support available.
85
86 //Note: You should use the Shareable attribute carefully.
87 //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
88 //Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
89 //Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
90
91 //Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
92 //When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
93 //When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
94
95
96 //Following MMU configuration is expected
97 //SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
98 //SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
99 //Domain 0 is always the Client domain
100 //Descriptors should place all memory in domain 0
101
102 #include "ARMCA9.h"
103 #include "mem_ARMCA9.h"
104
105 // TTB base address
106 #define TTB_BASE ((uint32_t*)__TTB_BASE)
107
108 // L2 table pointers
109 //----------------------------------------
110 #define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
111 // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
112 // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
113
114 #define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
115 #define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
116 #define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
117 #define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
118
119 //--------------------- PERIPHERALS -------------------
120 #define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
121 #define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
122
123 //--------------------- SYNC FLAGS --------------------
124 #define FLAG_SYNC 0xFFFFF000
125 #define F_SYNC_BASE 0xFFF00000 //1M aligned
126
127 static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
128 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
129 static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
130 static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
131 static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
132 static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
133
134 /* Define global descriptors */
135 static uint32_t Page_L1_4k = 0x0; //generic
136 static uint32_t Page_L1_64k = 0x0; //generic
137 static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
138 static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
139
MMU_CreateTranslationTable(void)140 void MMU_CreateTranslationTable(void)
141 {
142 mmu_region_attributes_Type region;
143
144 //Create 4GB of faulting entries
145 MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
146
147 /*
148 * Generate descriptors. Refer to core_ca.h to get information about attributes
149 *
150 */
151 //Create descriptors for Vectors, RO, RW, ZI sections
152 section_normal(Sect_Normal, region);
153 section_normal_cod(Sect_Normal_Cod, region);
154 section_normal_ro(Sect_Normal_RO, region);
155 section_normal_rw(Sect_Normal_RW, region);
156 //Create descriptors for peripherals
157 section_device_ro(Sect_Device_RO, region);
158 section_device_rw(Sect_Device_RW, region);
159 //Create descriptors for 64k pages
160 page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
161 //Create descriptors for 4k pages
162 page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
163
164
165 /*
166 * Define MMU flat-map regions and attributes
167 *
168 */
169
170 //Define Image
171 MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
172 MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
173
174 //--------------------- PERIPHERALS -------------------
175 MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
176 MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
177 MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
178 MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
179 MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);
180 MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE , 16, Sect_Device_RW);
181
182 // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
183 MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
184 // Define peripheral range 0x1C000000-0x1C00FFFF
185 MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
186 MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
187 MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
188 MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
189 MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
190 MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
191 MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
192 MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
193
194 // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
195 MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
196 // Define peripheral range 0x1C100000-0x1C10FFFF
197 MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
198 MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
199 MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
200 MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
201 MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
202
203 // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
204 MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
205 // Define private address space entry.
206 MMU_TTPage4k (TTB_BASE, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
207 // Define L2CC entry. Uncomment if PL310 is present
208 // MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
209
210 // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
211 MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
212 // Define synchronization space entry.
213 MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
214
215 /* Set location of level 1 page table
216 ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
217 ; 13:7 - 0x0
218 ; 6 - IRGN[0] 0x1 (Inner WB WA)
219 ; 5 - NOS 0x0 (Non-shared)
220 ; 4:3 - RGN 0x01 (Outer WB WA)
221 ; 2 - IMP 0x0 (Implementation Defined)
222 ; 1 - S 0x0 (Non-shared)
223 ; 0 - IRGN[1] 0x0 (Inner WB WA) */
224 __set_TTBR0(__TTB_BASE | 0x48);
225 __ISB();
226
227 /* Set up domain access control register
228 ; We set domain 0 to Client and all other domains to No Access.
229 ; All translation table entries specify domain 0 */
230 __set_DACR(1);
231 __ISB();
232 }
233
