1 /* ----------------------------------------------------------------------
2 * Project: CMSIS DSP Library
3 * Title: arm_and_u32.c
4 * Description: uint32_t bitwise AND
5 *
6 * $Date: 23 April 2021
7 * $Revision: V1.9.0
8 *
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
11 /*
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
13 *
14 * SPDX-License-Identifier: Apache-2.0
15 *
16 * Licensed under the Apache License, Version 2.0 (the License); you may
17 * not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
19 *
20 * www.apache.org/licenses/LICENSE-2.0
21 *
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
27 */
28
29 #include "dsp/basic_math_functions.h"
30
31 /**
32 @ingroup groupMath
33 */
34
35 /**
36 @addtogroup And
37 @{
38 */
39
40 /**
41 @brief Compute the logical bitwise AND of two fixed-point vectors.
42 @param[in] pSrcA points to input vector A
43 @param[in] pSrcB points to input vector B
44 @param[out] pDst points to output vector
45 @param[in] blockSize number of samples in each vector
46 */
47
arm_and_u32(const uint32_t * pSrcA,const uint32_t * pSrcB,uint32_t * pDst,uint32_t blockSize)48 void arm_and_u32(
49 const uint32_t * pSrcA,
50 const uint32_t * pSrcB,
51 uint32_t * pDst,
52 uint32_t blockSize)
53 {
54 uint32_t blkCnt; /* Loop counter */
55
56 #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
57 uint32x4_t vecSrcA, vecSrcB;
58
59 /* Compute 4 outputs at a time */
60 blkCnt = blockSize >> 2;
61
62 while (blkCnt > 0U)
63 {
64 vecSrcA = vld1q(pSrcA);
65 vecSrcB = vld1q(pSrcB);
66
67 vst1q(pDst, vandq_u32(vecSrcA, vecSrcB) );
68
69 pSrcA += 4;
70 pSrcB += 4;
71 pDst += 4;
72
73 /* Decrement the loop counter */
74 blkCnt--;
75 }
76
77 /* Tail */
78 blkCnt = blockSize & 3;
79
80 if (blkCnt > 0U)
81 {
82 mve_pred16_t p0 = vctp32q(blkCnt);
83 vecSrcA = vld1q(pSrcA);
84 vecSrcB = vld1q(pSrcB);
85 vstrwq_p(pDst, vandq_u32(vecSrcA, vecSrcB), p0);
86 }
87 #else
88 #if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
89 uint32x4_t vecA, vecB;
90
91 /* Compute 4 outputs at a time */
92 blkCnt = blockSize >> 2U;
93
94 while (blkCnt > 0U)
95 {
96 vecA = vld1q_u32(pSrcA);
97 vecB = vld1q_u32(pSrcB);
98
99 vst1q_u32(pDst, vandq_u32(vecA, vecB) );
100
101 pSrcA += 4;
102 pSrcB += 4;
103 pDst += 4;
104
105 /* Decrement the loop counter */
106 blkCnt--;
107 }
108
109 /* Tail */
110 blkCnt = blockSize & 3;
111 #else
112 /* Initialize blkCnt with number of samples */
113 blkCnt = blockSize;
114 #endif
115
116 while (blkCnt > 0U)
117 {
118 *pDst++ = (*pSrcA++)&(*pSrcB++);
119
120 /* Decrement the loop counter */
121 blkCnt--;
122 }
123 #endif /* if defined(ARM_MATH_MVEI) */
124 }
125
126 /**
127 @} end of And group
128 */
129
