1 /* 2 * Copyright (c) 2019-2022 Arm Limited 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file platform_base_address.h 19 * \brief This file defines all the peripheral base addresses for Corstone-310. 20 */ 21 22 #ifndef __PLATFORM_BASE_ADDRESS_H__ 23 #define __PLATFORM_BASE_ADDRESS_H__ 24 25 /* ======= Defines peripherals memory map addresses ======= */ 26 /* Non-secure memory map addresses */ 27 #define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ 28 #define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ 29 #define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ 30 #define DTCM1_BASE_NS 0x20002000 /* Data TCM block 1 Non-Secure base address */ 31 #define DTCM2_BASE_NS 0x20004000 /* Data TCM block 2 Non-Secure base address */ 32 #define DTCM3_BASE_NS 0x20006000 /* Data TCM block 3 Non-Secure base address */ 33 #define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ 34 #define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ 35 #define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ 36 /* Non-Secure Subsystem peripheral region */ 37 #define DMA_350_BASE_NS 0x40002000 /* DMA350 register block Non-Secure base address */ 38 #define ETHOS_U55_APB_BASE_NS 0x40004000 /* Ethos-U55 APB Non-Secure base address */ 39 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ 40 #define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ 41 #define CORSTONE310_NSACFG_BASE_NS 0x40080000 /* Corstone-310 Non-Secure Access Configuration Register Block Non-Secure base address */ 42 /* Non-Secure MSTEXPPILL Peripheral region */ 43 #define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ 44 #define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ 45 #define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ 46 #define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ 47 #define AHB_USER_0_BASE_NS 0x41104000 /* AHB USER 0 Non-Secure base address */ 48 #define AHB_USER_1_BASE_NS 0x41105000 /* AHB USER 1 Non-Secure base address */ 49 #define AHB_USER_2_BASE_NS 0x41106000 /* AHB USER 2 Non-Secure base address */ 50 #define AHB_USER_3_BASE_NS 0x41107000 /* AHB USER 3 Non-Secure base address */ 51 #define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ 52 #define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ 53 #define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ 54 #define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ 55 #define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ 56 #define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ 57 #define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ 58 #define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ 59 /* Non-Secure Subsystem peripheral region */ 60 #define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ 61 #define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ 62 #define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ 63 #define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ 64 #define CORSTONE310_SYSINFO_BASE_NS 0x48020000 /* Corstone-310 System info Block Non-Secure base address */ 65 #define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ 66 #define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ 67 #define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ 68 #define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ 69 /* Non-Secure MSTEXPPIHL Peripheral region */ 70 #define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ 71 #define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ 72 #define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ 73 #define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ 74 #define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ 75 #define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ 76 #define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ 77 #define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ 78 #define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ 79 #define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ 80 #define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ 81 #define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ 82 #define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ 83 #define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ 84 #define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ 85 #define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ 86 #define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ 87 #define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ 88 #define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ 89 #define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ 90 #define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ 91 #define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ 92 #define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ 93 #define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ 94 #define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ 95 #define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ 96 97 /* Secure memory map addresses */ 98 #define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ 99 #define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ 100 #define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ 101 #define DTCM1_BASE_S 0x30002000 /* Data TCM block 1 Secure base address */ 102 #define DTCM2_BASE_S 0x30004000 /* Data TCM block 2 Secure base address */ 103 #define DTCM3_BASE_S 0x30006000 /* Data TCM block 3 Secure base address */ 104 #define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ 105 #define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ 106 #define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ 107 /* Secure Subsystem peripheral region */ 108 #define DMA_350_BASE_S 0x50002000 /* DMA350 register block Secure base address */ 109 #define ETHOS_U55_APB_BASE_S 0x50004000 /* Ethos-U55 APB Secure base address */ 110 #define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ 111 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ 112 #define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ 113 #define CORSTONE310_SACFG_BASE_S 0x50080000 /* Corstone-310 Secure Access Configuration Register Secure base address */ 114 #define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ 115 #define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ 116 /* Secure MSTEXPPILL Peripheral region */ 117 #define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ 118 #define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ 119 #define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ 120 #define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ 121 #define AHB_USER_0_BASE_S 0x51104000 /* AHB USER 0 Secure base address */ 122 #define AHB_USER_1_BASE_S 0x51105000 /* AHB USER 1 Secure base address */ 123 #define AHB_USER_2_BASE_S 0x51106000 /* AHB USER 2 Secure base address */ 124 #define AHB_USER_3_BASE_S 0x51107000 /* AHB USER 3 Secure base address */ 125 #define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ 126 #define USB_BASE_S 0x51500000 /* USB Secure base address */ 127 #define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ 128 #define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ 129 #define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ 130 #define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ 131 #define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ 132 #define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ 133 #define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ 134 #define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ 135 #define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ 136 /* Secure Subsystem peripheral region */ 137 #define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ 138 #define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ 139 #define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ 140 #define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ 141 #define CORSTONE310_SYSINFO_BASE_S 0x58020000 /* Corstone-310 System info Block Secure base address */ 142 #define CORSTONE310_SYSCTRL_BASE_S 0x58021000 /* Corstone-310 System control Block Secure base address */ 143 #define CORSTONE310_SYSPPU_BASE_S 0x58022000 /* Corstone-310 System Power Policy Unit Secure base address */ 144 #define CORSTONE310_CPU0PPU_BASE_S 0x58023000 /* Corstone-310 CPU 0 Power Policy Unit Secure base address */ 145 #define CORSTONE310_MGMTPPU_BASE_S 0x58028000 /* Corstone-310 Management Power Policy Unit Secure base address */ 146 #define CORSTONE310_DBGPPU_BASE_S 0x58029000 /* Corstone-310 Debug Power Policy Unit Secure base address */ 147 #define CORSTONE310_NPU0PPU_BASE_S 0x5802A000 /* Corstone-310 NPU 0 Power Policy Unit Secure base address */ 148 #define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ 149 #define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ 150 #define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ 151 #define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ 152 #define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ 153 #define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ 154 /* Secure MSTEXPPIHL Peripheral region */ 155 #define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ 156 #define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ 157 #define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ 158 #define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ 159 #define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ 160 #define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ 161 #define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ 162 #define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ 163 #define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ 164 #define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ 165 #define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ 166 #define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ 167 #define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ 168 #define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ 169 #define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ 170 #define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ 171 #define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ 172 #define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ 173 #define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ 174 #define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ 175 #define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ 176 #define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ 177 #define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ 178 #define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ 179 #define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ 180 #define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ 181 182 /* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ 183 #define CORSTONE310_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller 184 * Access from Non-secure software is only allowed 185 * if AIRCR.BFHFNMINS is set to 1 */ 186 187 /* Memory size definitions */ 188 #define ITCM_SIZE (0x00008000) /* 32 kB */ 189 #define DTCM_BLK_SIZE (0x00002000) /* 8 kB */ 190 #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ 191 #define SRAM_SIZE (0x00200000) /* 2 MB */ 192 #define ISRAM0_SIZE (0x00200000) /* 2 MB */ 193 #define ISRAM1_SIZE (0x00200000) /* 2 MB */ 194 #define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ 195 #define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ 196 #define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ 197 198 /* Defines for Driver MPC's */ 199 /* SRAM -- 2 MB */ 200 #define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) 201 #define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) 202 #define MPC_SRAM_RANGE_OFFSET_NS (0x0) 203 #define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) 204 #define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) 205 #define MPC_SRAM_RANGE_OFFSET_S (0x0) 206 207 /* QSPI -- 8 MB */ 208 #define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) 209 #define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) 210 #define MPC_QSPI_RANGE_OFFSET_NS (0x0) 211 #define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) 212 #define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) 213 #define MPC_QSPI_RANGE_OFFSET_S (0x0) 214 215 /* ISRAM0 -- 2 MB*/ 216 #define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) 217 #define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) 218 #define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) 219 #define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) 220 #define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) 221 #define MPC_ISRAM0_RANGE_OFFSET_S (0x0) 222 223 /* ISRAM1 -- 2 MB */ 224 #define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) 225 #define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) 226 #define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) 227 #define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) 228 #define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) 229 #define MPC_ISRAM1_RANGE_OFFSET_S (0x0) 230 231 /* DDR4 -- 2GB (8 * 256 MB) */ 232 #define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) 233 #define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) 234 #define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) 235 #define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) 236 #define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) 237 #define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) 238 #define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) 239 #define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) 240 #define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) 241 #define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) 242 #define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) 243 #define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) 244 #define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) 245 #define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) 246 #define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) 247 #define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) 248 #define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) 249 #define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) 250 #define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) 251 #define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) 252 #define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) 253 #define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) 254 #define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) 255 #define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) 256 257 #endif /* __PLATFORM_BASE_ADDRESS_H__ */ 258
