1    /*
2     * Some or all of this work - Copyright (c) 2006 - 2021, Intel Corp.
3     * All rights reserved.
4     *
5     * Redistribution and use in source and binary forms, with or without modification,
6     * are permitted provided that the following conditions are met:
7     *
8     * Redistributions of source code must retain the above copyright notice,
9     * this list of conditions and the following disclaimer.
10     * Redistributions in binary form must reproduce the above copyright notice,
11     * this list of conditions and the following disclaimer in the documentation
12     * and/or other materials provided with the distribution.
13     * Neither the name of Intel Corporation nor the names of its contributors
14     * may be used to endorse or promote products derived from this software
15     * without specific prior written permission.
16     *
17     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20     * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21     * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23     * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24     * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25     * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27     */
28    /*
29     * Bug 222:
30     *
31     * SUMMARY: Alternating access to OpRegions of different Address Spaces issue
32     */
33    Method (M10A, 0, Serialized)
34    {
35        Method (CHCK, 3, NotSerialized)
36        {
37            If ((Arg0 != Arg1))
38            {
39                ERR (__METHOD__, ZFFF, __LINE__, 0x00, 0x00, Arg0, Arg1)
40            }
41        }
42
43        OperationRegion (OPR0, SystemMemory, 0x00, 0x01)
44        OperationRegion (OPR1, SystemIO, 0x00, 0x01)
45        Field (OPR0, ByteAcc, NoLock, Preserve)
46        {
47            F000,   8
48        }
49
50        Field (OPR1, ByteAcc, NoLock, Preserve)
51        {
52            F001,   8
53        }
54
55        F000 = 0x5A
56        CHCK (F000, 0x5A, 0x00)
57        F001 = 0xC3
58        CHCK (F001, 0xC3, 0x01)
59        CHCK (F000, 0x5A, 0x02)
60        CHCK (F001, 0xC3, 0x03)
61    }
62