1/*
2 * Some or all of this work - Copyright (c) 2006 - 2021, Intel Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * Bug 198:
31 *
32 * COMPONENT:
33 *
34 * SUMMARY:
35 */
36
37Method(mfa9) {
38
39	Event(e900)
40	Event(e9Z0)
41	Mutex(mx90, 0)
42	Mutex(mx91, 0)
43	Device(d900) { Name(i900, 0xabcd0017) }
44	Device(d9Z0) { Name(i900, 0xabcd0017) }
45	ThermalZone(tz90) {}
46	ThermalZone(tz91) {}
47	Processor(pr90, 0, 0xFFFFFFFF, 0) {}
48	Processor(pr91, 0, 0xFFFFFFFF, 0) {}
49	OperationRegion(r900, SystemMemory, 0x100, 0x100)
50	OperationRegion(r9Z0, SystemMemory, 0x100, 0x100)
51	PowerResource(pw90, 1, 0) {Method(mmmm){return (0)}}
52	PowerResource(pw91, 1, 0) {Method(mmmm){return (0)}}
53
54	Name(RMRC, 0)
55	Name(NRMT, "QQQQ")
56	Name(CTST, "CTST")
57	Name(RR44, Package(8) {})
58	Name(RR55, Package(8) {})
59	Name(s000, "The expected contents of 0-th elements of both Packages - RR44 and RR55")
60
61	// Error checking
62	Method(m000, 1) {
63		Store("======================================== sit 1", Debug)
64		Store(arg0, Debug)
65		Store(RMRC, Debug)
66		Store(DerefOf(Index(RR44, 0)), Debug)
67		Store(DerefOf(Index(RR55, 0)), Debug)
68
69		Store(DerefOf(Index(RR44, 0)), Local0)
70		Store(DerefOf(Index(RR55, 0)), Local1)
71
72		if (LNotEqual(Local0, s000)) {
73			// Store("Error 0", Debug)
74			err("", zFFF, __LINE__, 0, 0, Local0, s000)
75		}
76		if (LNotEqual(Local1, s000)) {
77			// Store("Error 1", Debug)
78			err("", zFFF, __LINE__, 0, 0, Local0, s000)
79		}
80
81		Store("========================================.", Debug)
82	}
83
84	Method(m001) {
85
86		Name(b000, Buffer(4) {})
87
88		if (SizeOf(NRMT)) {
89			Store("vvvvvv", Local0)
90			Concatenate(Local0, "PASS:", Local1)
91			Concatenate(":", CTST, Local0)
92
93			// This - eliminates the effect
94			// Store(s000, Local0)
95
96			Store("The expected contents of 0-th elements of both Packages - RR44 and RR55", Local0)
97
98			// The order of RR55 and RR44 is essential, only the first is then corrupted:
99
100			Store(Local0, Index(RR44, RMRC))
101			Store(Local0, Index(RR55, RMRC))
102
103			m000(0x1000)
104//			m000()
105
106			Increment(RMRC)
107		}
108
109		m000(0x1001)
110//		m000()
111	}
112
113Method(m002)
114{
115	Store("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ RR44", Index(RR44, 0))
116	Store("ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ RR55", Index(RR55, 0))
117
118	Store(10000000000, Local0)
119	// Store(1000000, Local0)
120	Store(0, Local1)
121
122	ToBCD(Local0, Local2)
123
124
125	// These don't cause the effect:
126	// Divide(1, Local1, Local2)
127	// Divide(1, Local1, Local7, Local2)
128	// Store(SizeOf(d9Z0), Local2)
129
130	if (LNotEqual(Local2, 0)) {
131		Store("Zizi 012345", Debug)
132	}
133
134	// If you uncomment this Store the effect will disappear
135
136	// Store(0, Local0)
137}
138
139	// If you uncomment this Store then another one of RR44 and RR55 will be corrupted
140	// (see comment to m001)
141
142	// Store("m002", NRMT)
143
144//	Store("--------------!!!!!!!!!!!--------- RR44", Debug)
145//	Store(Index(RR44, 0), Debug)
146//	Store("--------------!!!!!!!!!!!--------- RR55", Debug)
147//	Store(Index(RR55, 0), Debug)
148	Store("---------------------------------- SSSSSSSS 0", Debug)
149
150	CH03("", 0, 0x002, __LINE__, 0)
151	m002()
152
153//	Store("---------------------------------- SSSSSSSS 1", Debug)
154
155	m001()
156
157//	Store("---------------------------------- SSSSSSSS 2", Debug)
158
159	m000(0x1009)
160
161//	m000()
162
163	if (F64) {
164		CH03("", 0, 0x003, __LINE__, 0)
165	} else {
166		CH04("", 0, 0xff, 0, __LINE__, 0, 0) // AE_AML_NUMERIC_OVERFLOW
167	}
168}
169