1 /*
2 * Copyright (c) 2017 comsuisse AG
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8 #include <zephyr/kernel.h>
9 #include <zephyr/ztest.h>
10 #include <zephyr/drivers/i2s.h>
11 #include <zephyr/sys/iterable_sections.h>
12
13 #define I2S_DEV_NODE_RX DT_ALIAS(i2s_node0)
14 #ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
15 #define I2S_DEV_NODE_TX DT_ALIAS(i2s_node1)
16 #else
17 #define I2S_DEV_NODE_TX DT_ALIAS(i2s_node0)
18 #endif
19
20 #define NUM_BLOCKS 20
21 #define SAMPLE_NO 64
22
23 /* The data_l represent a sine wave */
24 static int16_t data_l[SAMPLE_NO] = {
25 3211, 6392, 9511, 12539, 15446, 18204, 20787, 23169,
26 25329, 27244, 28897, 30272, 31356, 32137, 32609, 32767,
27 32609, 32137, 31356, 30272, 28897, 27244, 25329, 23169,
28 20787, 18204, 15446, 12539, 9511, 6392, 3211, 0,
29 -3212, -6393, -9512, -12540, -15447, -18205, -20788, -23170,
30 -25330, -27245, -28898, -30273, -31357, -32138, -32610, -32767,
31 -32610, -32138, -31357, -30273, -28898, -27245, -25330, -23170,
32 -20788, -18205, -15447, -12540, -9512, -6393, -3212, -1,
33 };
34
35 /* The data_r represent a sine wave shifted by 90 deg to data_l sine wave */
36 static int16_t data_r[SAMPLE_NO] = {
37 32609, 32137, 31356, 30272, 28897, 27244, 25329, 23169,
38 20787, 18204, 15446, 12539, 9511, 6392, 3211, 0,
39 -3212, -6393, -9512, -12540, -15447, -18205, -20788, -23170,
40 -25330, -27245, -28898, -30273, -31357, -32138, -32610, -32767,
41 -32610, -32138, -31357, -30273, -28898, -27245, -25330, -23170,
42 -20788, -18205, -15447, -12540, -9512, -6393, -3212, -1,
43 3211, 6392, 9511, 12539, 15446, 18204, 20787, 23169,
44 25329, 27244, 28897, 30272, 31356, 32137, 32609, 32767,
45 };
46
47 #define BLOCK_SIZE (2 * sizeof(data_l))
48
49 #ifdef CONFIG_NOCACHE_MEMORY
50 #define MEM_SLAB_CACHE_ATTR __nocache
51 #else
52 #define MEM_SLAB_CACHE_ATTR
53 #endif /* CONFIG_NOCACHE_MEMORY */
54
55 /*
56 * NUM_BLOCKS is the number of blocks used by the test. Some of the drivers,
57 * e.g. i2s_mcux_flexcomm, permanently keep ownership of a few RX buffers. Add a few more
58 * RX blocks to satisfy this requirement
59 */
60
61 char MEM_SLAB_CACHE_ATTR __aligned(WB_UP(32))
62 _k_mem_slab_buf_rx_0_mem_slab[(NUM_BLOCKS + 2) * WB_UP(BLOCK_SIZE)];
63 STRUCT_SECTION_ITERABLE(k_mem_slab, rx_0_mem_slab) =
64 Z_MEM_SLAB_INITIALIZER(rx_0_mem_slab, _k_mem_slab_buf_rx_0_mem_slab,
65 WB_UP(BLOCK_SIZE), NUM_BLOCKS + 2);
66
67 char MEM_SLAB_CACHE_ATTR __aligned(WB_UP(32))
68 _k_mem_slab_buf_tx_0_mem_slab[(NUM_BLOCKS) * WB_UP(BLOCK_SIZE)];
69 STRUCT_SECTION_ITERABLE(k_mem_slab, tx_0_mem_slab) =
70 Z_MEM_SLAB_INITIALIZER(tx_0_mem_slab, _k_mem_slab_buf_tx_0_mem_slab,
71 WB_UP(BLOCK_SIZE), NUM_BLOCKS);
72
73 static const struct device *dev_i2s_rx;
74 static const struct device *dev_i2s_tx;
75 static const struct device *dev_i2s_rxtx;
76 static bool dir_both_supported;
77
fill_buf(int16_t * tx_block,int att)78 static void fill_buf(int16_t *tx_block, int att)
79 {
80 for (int i = 0; i < SAMPLE_NO; i++) {
81 tx_block[2 * i] = data_l[i] >> att;
82 tx_block[2 * i + 1] = data_r[i] >> att;
83 }
84 }
85
verify_buf(int16_t * rx_block,int att)86 static int verify_buf(int16_t *rx_block, int att)
87 {
88 int sample_no = SAMPLE_NO;
89
90 #if (CONFIG_I2S_TEST_ALLOWED_DATA_OFFSET > 0)
91 static ZTEST_DMEM int offset = -1;
92
93 if (offset < 0) {
94 do {
95 ++offset;
96 if (offset > CONFIG_I2S_TEST_ALLOWED_DATA_OFFSET) {
97 TC_PRINT("Allowed data offset exceeded\n");
98 return -TC_FAIL;
99 }
100 } while (rx_block[2 * offset] != data_l[0] >> att);
101
102 TC_PRINT("Using data offset: %d\n", offset);
103 }
104
105 rx_block += 2 * offset;
106 sample_no -= offset;
107 #endif
108
109 for (int i = 0; i < sample_no; i++) {
110 if (rx_block[2 * i] != data_l[i] >> att) {
111 TC_PRINT("Error: att %d: data_l mismatch at position "
112 "%d, expected %d, actual %d\n",
113 att, i, data_l[i] >> att, rx_block[2 * i]);
114 return -TC_FAIL;
115 }
116 if (rx_block[2 * i + 1] != data_r[i] >> att) {
117 TC_PRINT("Error: att %d: data_r mismatch at position "
118 "%d, expected %d, actual %d\n",
119 att, i, data_r[i] >> att, rx_block[2 * i + 1]);
120 return -TC_FAIL;
121 }
122 }
123
124 return TC_PASS;
125 }
126
127 #define TIMEOUT 2000
128 #define FRAME_CLK_FREQ 44000
129
configure_stream(const struct device * dev_i2s,enum i2s_dir dir)130 static int configure_stream(const struct device *dev_i2s, enum i2s_dir dir)
131 {
132 int ret;
133 struct i2s_config i2s_cfg;
134
135 i2s_cfg.word_size = 16U;
136 i2s_cfg.channels = 2U;
137 i2s_cfg.format = I2S_FMT_DATA_FORMAT_I2S;
138 i2s_cfg.frame_clk_freq = FRAME_CLK_FREQ;
139 i2s_cfg.block_size = BLOCK_SIZE;
140 i2s_cfg.timeout = TIMEOUT;
141
142 if (dir == I2S_DIR_TX) {
143 /* Configure the Transmit port as Master */
144 i2s_cfg.options = I2S_OPT_FRAME_CLK_MASTER
145 | I2S_OPT_BIT_CLK_MASTER;
146 } else if (dir == I2S_DIR_RX) {
147 /* Configure the Receive port as Slave */
148 i2s_cfg.options = I2S_OPT_FRAME_CLK_SLAVE
149 | I2S_OPT_BIT_CLK_SLAVE;
150 } else { /* dir == I2S_DIR_BOTH */
151 i2s_cfg.options = I2S_OPT_FRAME_CLK_MASTER
152 | I2S_OPT_BIT_CLK_MASTER;
153 }
154
155 if (!IS_ENABLED(CONFIG_I2S_TEST_USE_GPIO_LOOPBACK)) {
156 i2s_cfg.options |= I2S_OPT_LOOPBACK;
157 }
158
159 if (dir == I2S_DIR_TX || dir == I2S_DIR_BOTH) {
160 i2s_cfg.mem_slab = &tx_0_mem_slab;
161 ret = i2s_configure(dev_i2s, I2S_DIR_TX, &i2s_cfg);
162 if (ret < 0) {
163 TC_PRINT("Failed to configure I2S TX stream (%d)\n",
164 ret);
165 return -TC_FAIL;
166 }
167 }
168
169 if (dir == I2S_DIR_RX || dir == I2S_DIR_BOTH) {
170 i2s_cfg.mem_slab = &rx_0_mem_slab;
171 ret = i2s_configure(dev_i2s, I2S_DIR_RX, &i2s_cfg);
172 if (ret < 0) {
173 TC_PRINT("Failed to configure I2S RX stream (%d)\n",
174 ret);
175 return -TC_FAIL;
176 }
177 }
178
179 return TC_PASS;
180 }
181
182
183 /** @brief Short I2S transfer.
184 *
185 * - TX stream START trigger starts transmission.
186 * - RX stream START trigger starts reception.
187 * - sending / receiving a short sequence of data returns success.
188 * - TX stream DRAIN trigger empties the transmit queue.
189 * - RX stream STOP trigger stops reception.
190 */
ZTEST(drivers_i2s_speed,test_i2s_transfer_short)191 ZTEST(drivers_i2s_speed, test_i2s_transfer_short)
192 {
193 if (IS_ENABLED(CONFIG_I2S_TEST_USE_I2S_DIR_BOTH)) {
194 TC_PRINT("RX/TX transfer requires use of I2S_DIR_BOTH.\n");
195 ztest_test_skip();
196 return;
197 }
198
199 void *rx_block[3];
200 void *tx_block;
201 size_t rx_size;
202 int ret;
203
204 /* Prefill TX queue */
205 for (int i = 0; i < 3; i++) {
206 ret = k_mem_slab_alloc(&tx_0_mem_slab, &tx_block, K_FOREVER);
207 zassert_equal(ret, 0);
208 fill_buf((uint16_t *)tx_block, i);
209
210 ret = i2s_write(dev_i2s_tx, tx_block, BLOCK_SIZE);
211 zassert_equal(ret, 0);
212
213 TC_PRINT("%d->OK\n", i);
214 }
215
216 /* Start reception */
217 ret = i2s_trigger(dev_i2s_rx, I2S_DIR_RX, I2S_TRIGGER_START);
218 zassert_equal(ret, 0, "RX START trigger failed");
219
220 /* Start transmission */
221 ret = i2s_trigger(dev_i2s_tx, I2S_DIR_TX, I2S_TRIGGER_START);
222 zassert_equal(ret, 0, "TX START trigger failed");
223
224 /* All data written, drain TX queue and stop the transmission */
225 ret = i2s_trigger(dev_i2s_tx, I2S_DIR_TX, I2S_TRIGGER_DRAIN);
226 zassert_equal(ret, 0, "TX DRAIN trigger failed");
227
228 ret = i2s_read(dev_i2s_rx, &rx_block[0], &rx_size);
229 zassert_equal(ret, 0);
230 zassert_equal(rx_size, BLOCK_SIZE);
231
232 ret = i2s_read(dev_i2s_rx, &rx_block[1], &rx_size);
233 zassert_equal(ret, 0);
234 zassert_equal(rx_size, BLOCK_SIZE);
235
236 /* All but one data block read, stop reception */
237 ret = i2s_trigger(dev_i2s_rx, I2S_DIR_RX, I2S_TRIGGER_STOP);
238 zassert_equal(ret, 0, "RX STOP trigger failed");
239
240 ret = i2s_read(dev_i2s_rx, &rx_block[2], &rx_size);
241 zassert_equal(ret, 0);
242 zassert_equal(rx_size, BLOCK_SIZE);
243
244 /* Verify received data */
245 ret = verify_buf((uint16_t *)rx_block[0], 0);
246 zassert_equal(ret, 0);
247 k_mem_slab_free(&rx_0_mem_slab, rx_block[0]);
248 TC_PRINT("%d<-OK\n", 1);
249
250 ret = verify_buf((uint16_t *)rx_block[1], 1);
251 zassert_equal(ret, 0);
252 k_mem_slab_free(&rx_0_mem_slab, rx_block[1]);
253 TC_PRINT("%d<-OK\n", 2);
254
255 ret = verify_buf((uint16_t *)rx_block[2], 2);
256 zassert_equal(ret, 0);
257 k_mem_slab_free(&rx_0_mem_slab, rx_block[2]);
258 TC_PRINT("%d<-OK\n", 3);
259 }
260
261 /** @brief Long I2S transfer.
262 *
263 * - TX stream START trigger starts transmission.
264 * - RX stream START trigger starts reception.
265 * - sending / receiving a long sequence of data returns success.
266 * - TX stream DRAIN trigger empties the transmit queue.
267 * - RX stream STOP trigger stops reception.
268 */
ZTEST(drivers_i2s_speed,test_i2s_transfer_long)269 ZTEST(drivers_i2s_speed, test_i2s_transfer_long)
270 {
271 if (IS_ENABLED(CONFIG_I2S_TEST_USE_I2S_DIR_BOTH)) {
272 TC_PRINT("RX/TX transfer requires use of I2S_DIR_BOTH.\n");
273 ztest_test_skip();
274 return;
275 }
276
277 void *rx_block[NUM_BLOCKS];
278 void *tx_block[NUM_BLOCKS];
279 size_t rx_size;
280 int tx_idx;
281 int rx_idx = 0;
282 int num_verified;
283 int ret;
284
285 /* Prepare TX data blocks */
286 for (tx_idx = 0; tx_idx < NUM_BLOCKS; tx_idx++) {
287 ret = k_mem_slab_alloc(&tx_0_mem_slab, &tx_block[tx_idx],
288 K_FOREVER);
289 zassert_equal(ret, 0);
290 fill_buf((uint16_t *)tx_block[tx_idx], tx_idx % 3);
291 }
292
293 tx_idx = 0;
294
295 /* Prefill TX queue */
296 ret = i2s_write(dev_i2s_tx, tx_block[tx_idx++], BLOCK_SIZE);
297 zassert_equal(ret, 0);
298
299 ret = i2s_write(dev_i2s_tx, tx_block[tx_idx++], BLOCK_SIZE);
300 zassert_equal(ret, 0);
301
302 /* Start reception */
303 ret = i2s_trigger(dev_i2s_rx, I2S_DIR_RX, I2S_TRIGGER_START);
304 zassert_equal(ret, 0, "RX START trigger failed");
305
306 /* Start transmission */
307 ret = i2s_trigger(dev_i2s_tx, I2S_DIR_TX, I2S_TRIGGER_START);
308 zassert_equal(ret, 0, "TX START trigger failed");
309
310 for (; tx_idx < NUM_BLOCKS; ) {
311 ret = i2s_write(dev_i2s_tx, tx_block[tx_idx++], BLOCK_SIZE);
312 zassert_equal(ret, 0);
313
314 ret = i2s_read(dev_i2s_rx, &rx_block[rx_idx++], &rx_size);
315 zassert_equal(ret, 0);
316 zassert_equal(rx_size, BLOCK_SIZE);
317 }
318
319 /* All data written, flush TX queue and stop the transmission */
320 ret = i2s_trigger(dev_i2s_tx, I2S_DIR_TX, I2S_TRIGGER_DRAIN);
321 zassert_equal(ret, 0, "TX DRAIN trigger failed");
322
323 ret = i2s_read(dev_i2s_rx, &rx_block[rx_idx++], &rx_size);
324 zassert_equal(ret, 0);
325 zassert_equal(rx_size, BLOCK_SIZE);
326
327 /* All but one data block read, stop reception */
328 ret = i2s_trigger(dev_i2s_rx, I2S_DIR_RX, I2S_TRIGGER_STOP);
329 zassert_equal(ret, 0, "RX STOP trigger failed");
330
331 ret = i2s_read(dev_i2s_rx, &rx_block[rx_idx++], &rx_size);
332 zassert_equal(ret, 0);
333 zassert_equal(rx_size, BLOCK_SIZE);
334
335 TC_PRINT("%d TX blocks sent\n", tx_idx);
336 TC_PRINT("%d RX blocks received\n", rx_idx);
337
338 /* Verify received data */
339 num_verified = 0;
340 for (rx_idx = 0; rx_idx < NUM_BLOCKS; rx_idx++) {
341 ret = verify_buf((uint16_t *)rx_block[rx_idx], rx_idx % 3);
342 if (ret != 0) {
343 TC_PRINT("%d RX block invalid\n", rx_idx);
344 } else {
345 num_verified++;
346 }
347 k_mem_slab_free(&rx_0_mem_slab, rx_block[rx_idx]);
348 }
349 zassert_equal(num_verified, NUM_BLOCKS, "Invalid RX blocks received");
350 }
351
352
353 /** @brief Short I2S transfer using I2S_DIR_BOTH.
354 *
355 * - START trigger starts both the transmission and reception.
356 * - Sending / receiving a short sequence of data returns success.
357 * - DRAIN trigger empties the transmit queue and stops both streams.
358 */
ZTEST(drivers_i2s_speed_both_rxtx,test_i2s_dir_both_transfer_short)359 ZTEST(drivers_i2s_speed_both_rxtx, test_i2s_dir_both_transfer_short)
360 {
361 if (!dir_both_supported) {
362 TC_PRINT("I2S_DIR_BOTH value is not supported.\n");
363 ztest_test_skip();
364 return;
365 }
366
367 void *rx_block[3];
368 void *tx_block;
369 size_t rx_size;
370 int ret;
371
372 /* Prefill TX queue */
373 for (int i = 0; i < 3; i++) {
374 ret = k_mem_slab_alloc(&tx_0_mem_slab, &tx_block, K_FOREVER);
375 zassert_equal(ret, 0);
376 fill_buf((uint16_t *)tx_block, i);
377
378 ret = i2s_write(dev_i2s_rxtx, tx_block, BLOCK_SIZE);
379 zassert_equal(ret, 0);
380
381 TC_PRINT("%d->OK\n", i);
382 }
383
384 ret = i2s_trigger(dev_i2s_rxtx, I2S_DIR_BOTH, I2S_TRIGGER_START);
385 zassert_equal(ret, 0, "RX/TX START trigger failed\n");
386
387 /* All data written, drain TX queue and stop both streams. */
388 ret = i2s_trigger(dev_i2s_rxtx, I2S_DIR_BOTH, I2S_TRIGGER_DRAIN);
389 zassert_equal(ret, 0, "RX/TX DRAIN trigger failed");
390
391 ret = i2s_read(dev_i2s_rxtx, &rx_block[0], &rx_size);
392 zassert_equal(ret, 0);
393 zassert_equal(rx_size, BLOCK_SIZE);
394
395 ret = i2s_read(dev_i2s_rxtx, &rx_block[1], &rx_size);
396 zassert_equal(ret, 0);
397 zassert_equal(rx_size, BLOCK_SIZE);
398
399 ret = i2s_read(dev_i2s_rxtx, &rx_block[2], &rx_size);
400 zassert_equal(ret, 0);
401 zassert_equal(rx_size, BLOCK_SIZE);
402
403 /* Verify received data */
404 ret = verify_buf((uint16_t *)rx_block[0], 0);
405 zassert_equal(ret, 0);
406 k_mem_slab_free(&rx_0_mem_slab, rx_block[0]);
407 TC_PRINT("%d<-OK\n", 1);
408
409 ret = verify_buf((uint16_t *)rx_block[1], 1);
410 zassert_equal(ret, 0);
411 k_mem_slab_free(&rx_0_mem_slab, rx_block[1]);
412 TC_PRINT("%d<-OK\n", 2);
413
414 ret = verify_buf((uint16_t *)rx_block[2], 2);
415 zassert_equal(ret, 0);
416 k_mem_slab_free(&rx_0_mem_slab, rx_block[2]);
417 TC_PRINT("%d<-OK\n", 3);
418 }
419
420 /** @brief Long I2S transfer using I2S_DIR_BOTH.
421 *
422 * - START trigger starts both the transmission and reception.
423 * - Sending / receiving a long sequence of data returns success.
424 * - DRAIN trigger empties the transmit queue and stops both streams.
425 */
ZTEST(drivers_i2s_speed_both_rxtx,test_i2s_dir_both_transfer_long)426 ZTEST(drivers_i2s_speed_both_rxtx, test_i2s_dir_both_transfer_long)
427 {
428 if (!dir_both_supported) {
429 TC_PRINT("I2S_DIR_BOTH value is not supported.\n");
430 ztest_test_skip();
431 return;
432 }
433
434 void *rx_block[NUM_BLOCKS];
435 void *tx_block[NUM_BLOCKS];
436 size_t rx_size;
437 int tx_idx;
438 int rx_idx = 0;
439 int num_verified;
440 int ret;
441
442 /* Prepare TX data blocks */
443 for (tx_idx = 0; tx_idx < NUM_BLOCKS; tx_idx++) {
444 ret = k_mem_slab_alloc(&tx_0_mem_slab, &tx_block[tx_idx],
445 K_FOREVER);
446 zassert_equal(ret, 0);
447 fill_buf((uint16_t *)tx_block[tx_idx], tx_idx % 3);
448 }
449
450 tx_idx = 0;
451
452 /* Prefill TX queue */
453 ret = i2s_write(dev_i2s_rxtx, tx_block[tx_idx++], BLOCK_SIZE);
454 zassert_equal(ret, 0);
455
456 ret = i2s_write(dev_i2s_rxtx, tx_block[tx_idx++], BLOCK_SIZE);
457 zassert_equal(ret, 0);
458
459 ret = i2s_trigger(dev_i2s_rxtx, I2S_DIR_BOTH, I2S_TRIGGER_START);
460 zassert_equal(ret, 0, "RX/TX START trigger failed\n");
461
462 for (; tx_idx < NUM_BLOCKS; ) {
463 ret = i2s_write(dev_i2s_rxtx, tx_block[tx_idx++], BLOCK_SIZE);
464 zassert_equal(ret, 0);
465
466 ret = i2s_read(dev_i2s_rxtx, &rx_block[rx_idx++], &rx_size);
467 zassert_equal(ret, 0);
468 zassert_equal(rx_size, BLOCK_SIZE);
469 }
470
471 /* All data written, drain TX queue and stop both streams. */
472 ret = i2s_trigger(dev_i2s_rxtx, I2S_DIR_BOTH, I2S_TRIGGER_DRAIN);
473 zassert_equal(ret, 0, "RX/TX DRAIN trigger failed");
474
475 ret = i2s_read(dev_i2s_rxtx, &rx_block[rx_idx++], &rx_size);
476 zassert_equal(ret, 0);
477 zassert_equal(rx_size, BLOCK_SIZE);
478
479 ret = i2s_read(dev_i2s_rxtx, &rx_block[rx_idx++], &rx_size);
480 zassert_equal(ret, 0);
481 zassert_equal(rx_size, BLOCK_SIZE);
482
483 TC_PRINT("%d TX blocks sent\n", tx_idx);
484 TC_PRINT("%d RX blocks received\n", rx_idx);
485
486 /* Verify received data */
487 num_verified = 0;
488 for (rx_idx = 0; rx_idx < NUM_BLOCKS; rx_idx++) {
489 ret = verify_buf((uint16_t *)rx_block[rx_idx], rx_idx % 3);
490 if (ret != 0) {
491 TC_PRINT("%d RX block invalid\n", rx_idx);
492 } else {
493 num_verified++;
494 }
495 k_mem_slab_free(&rx_0_mem_slab, rx_block[rx_idx]);
496 }
497 zassert_equal(num_verified, NUM_BLOCKS, "Invalid RX blocks received");
498 }
499
test_i2s_speed_configure(void)500 static void *test_i2s_speed_configure(void)
501 {
502 /* Configure I2S TX transfer. */
503 int ret;
504
505 dev_i2s_tx = DEVICE_DT_GET_OR_NULL(I2S_DEV_NODE_TX);
506 zassert_not_null(dev_i2s_tx, "transfer device not found");
507 zassert(device_is_ready(dev_i2s_tx), "transfer device not ready");
508
509 ret = configure_stream(dev_i2s_tx, I2S_DIR_TX);
510 zassert_equal(ret, TC_PASS);
511
512 /* Configure I2S RX transfer. */
513 dev_i2s_rx = DEVICE_DT_GET_OR_NULL(I2S_DEV_NODE_RX);
514 zassert_not_null(dev_i2s_rx, "receive device not found");
515 zassert(device_is_ready(dev_i2s_rx), "receive device not ready");
516
517 ret = configure_stream(dev_i2s_rx, I2S_DIR_RX);
518 zassert_equal(ret, TC_PASS);
519
520 return 0;
521 }
522
test_i2s_speed_rxtx_configure(void)523 static void *test_i2s_speed_rxtx_configure(void)
524 {
525 int ret;
526
527 /* Configure I2S Dir Both transfer. */
528 dev_i2s_rxtx = DEVICE_DT_GET_OR_NULL(I2S_DEV_NODE_RX);
529 zassert_not_null(dev_i2s_rxtx, "receive device not found");
530 zassert(device_is_ready(dev_i2s_rxtx), "receive device not ready");
531
532 ret = configure_stream(dev_i2s_rxtx, I2S_DIR_BOTH);
533 zassert_equal(ret, TC_PASS);
534
535 /* Check if the tested driver supports the I2S_DIR_BOTH value.
536 * Use the DROP trigger for this, as in the current state of the driver
537 * (READY, both TX and RX queues empty) it is actually a no-op.
538 */
539 ret = i2s_trigger(dev_i2s_rxtx, I2S_DIR_BOTH, I2S_TRIGGER_DROP);
540 dir_both_supported = (ret == 0);
541
542 if (IS_ENABLED(CONFIG_I2S_TEST_USE_I2S_DIR_BOTH)) {
543 zassert_true(dir_both_supported,
544 "I2S_DIR_BOTH value is supposed to be supported.");
545 }
546
547 return 0;
548 }
549
550
551 ZTEST_SUITE(drivers_i2s_speed, NULL, test_i2s_speed_configure, NULL, NULL, NULL);
552 ZTEST_SUITE(drivers_i2s_speed_both_rxtx, NULL, test_i2s_speed_rxtx_configure, NULL, NULL, NULL);
553
