1 /*
2 * Copyright (c) 2016 Intel Corporation
3 * Copyright 2024 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include "test_gpio.h"
9
10 /* Grotesque hack for pinmux boards */
11 #if defined(CONFIG_BOARD_RV32M1_VEGA)
12 #include <fsl_port.h>
13 #elif defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4)
14 #include "device_imx.h"
15 #elif defined(CONFIG_BOARD_MIMXRT1050_EVK)
16 #include <fsl_iomuxc.h>
17 #elif defined(CONFIG_BOARD_NRF52_BSIM)
18 #include <NRF_GPIO.h>
19 #endif
20
board_setup(void)21 static void board_setup(void)
22 {
23 #if defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4)
24 /*
25 * Configure pin mux.
26 * The following code needs to configure the same GPIOs which were
27 * selected as test pins in device tree.
28 */
29
30 if (PIN_IN != 15) {
31 printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15);
32 k_panic();
33 }
34
35 if (PIN_OUT != 14) {
36 printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14);
37 k_panic();
38 }
39
40 /* Configure pin RGMII2_RD2 as GPIO5_IO14. */
41 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 =
42 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(5);
43 /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
44 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 =
45 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK |
46 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK |
47 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(2) |
48 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(6);
49
50 /* Configure pin RGMII2_RD3 as GPIO5_IO15. */
51 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 =
52 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(5);
53 /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
54 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 =
55 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK |
56 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK |
57 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(2) |
58 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(6);
59 #elif defined(CONFIG_GPIO_EMUL)
60 extern struct gpio_callback gpio_emul_callback;
61 const struct device *const dev = DEVICE_DT_GET(DEV);
62
63 zassert_true(device_is_ready(dev), "GPIO dev is not ready");
64 int rc = gpio_add_callback(dev, &gpio_emul_callback);
65 __ASSERT(rc == 0, "gpio_add_callback() failed: %d", rc);
66 #elif defined(CONFIG_BOARD_NRF52_BSIM)
67 static bool done;
68
69 if (!done) {
70 done = true;
71 /* This functions allows to programmatically short-circuit SOC GPIO pins */
72 nrf_gpio_backend_register_short(1, PIN_OUT, 1, PIN_IN);
73 }
74 #endif
75 }
76
gpio_basic_setup(void)77 static void *gpio_basic_setup(void)
78 {
79 board_setup();
80
81 return NULL;
82 }
83
84 /* Test GPIO port configuration */
85 ZTEST_SUITE(gpio_port, NULL, gpio_basic_setup, NULL, NULL, NULL);
86
87 /* Test GPIO callback management */
88 ZTEST_SUITE(gpio_port_cb_mgmt, NULL, gpio_basic_setup, NULL, NULL, NULL);
89
90 /* Test GPIO callbacks */
91 ZTEST_SUITE(gpio_port_cb_vari, NULL, gpio_basic_setup, NULL, NULL, NULL);
92
93 /* Test GPIO port configuration influence on callbacks. Want to run just
94 * after flash, hence the name starting in 'a'
95 */
96 ZTEST_SUITE(after_flash_gpio_config_trigger, NULL, gpio_basic_setup, NULL, NULL,
97 NULL);
98
