1 /*
2 * Copyright (c) 2017-2019 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stddef.h>
8 #include <string.h>
9
10 #include <zephyr/toolchain.h>
11 #include <zephyr/types.h>
12 #include <soc.h>
13 #include <zephyr/drivers/clock_control.h>
14
15 #include "hal/cpu.h"
16 #include "hal/cntr.h"
17 #include "hal/ccm.h"
18 #include "hal/radio.h"
19
20 #include "util/memq.h"
21
22 #include "lll.h"
23 #include "lll_internal.h"
24
25 #include "ll_test.h"
26
27 #include "hal/debug.h"
28
29 #define CNTR_MIN_DELTA 3
30
31 static const uint32_t test_sync_word = 0x71764129;
32 static uint8_t test_phy;
33 static uint8_t test_phy_flags;
34 static uint16_t test_num_rx;
35 static bool started;
36
37 /* NOTE: The PRBS9 sequence used as packet payload.
38 * The bytes in the sequence are in the right order, but the bits of each byte
39 * in the array are reverse from that found by running the PRBS9 algorithm. This
40 * is done to transmit MSbit first on air.
41 */
42
43 static const uint8_t prbs9[] = {
44 0xFF, 0xC1, 0xFB, 0xE8, 0x4C, 0x90, 0x72, 0x8B,
45 0xE7, 0xB3, 0x51, 0x89, 0x63, 0xAB, 0x23, 0x23,
46 0x02, 0x84, 0x18, 0x72, 0xAA, 0x61, 0x2F, 0x3B,
47 0x51, 0xA8, 0xE5, 0x37, 0x49, 0xFB, 0xC9, 0xCA,
48 0x0C, 0x18, 0x53, 0x2C, 0xFD, 0x45, 0xE3, 0x9A,
49 0xE6, 0xF1, 0x5D, 0xB0, 0xB6, 0x1B, 0xB4, 0xBE,
50 0x2A, 0x50, 0xEA, 0xE9, 0x0E, 0x9C, 0x4B, 0x5E,
51 0x57, 0x24, 0xCC, 0xA1, 0xB7, 0x59, 0xB8, 0x87,
52 0xFF, 0xE0, 0x7D, 0x74, 0x26, 0x48, 0xB9, 0xC5,
53 0xF3, 0xD9, 0xA8, 0xC4, 0xB1, 0xD5, 0x91, 0x11,
54 0x01, 0x42, 0x0C, 0x39, 0xD5, 0xB0, 0x97, 0x9D,
55 0x28, 0xD4, 0xF2, 0x9B, 0xA4, 0xFD, 0x64, 0x65,
56 0x06, 0x8C, 0x29, 0x96, 0xFE, 0xA2, 0x71, 0x4D,
57 0xF3, 0xF8, 0x2E, 0x58, 0xDB, 0x0D, 0x5A, 0x5F,
58 0x15, 0x28, 0xF5, 0x74, 0x07, 0xCE, 0x25, 0xAF,
59 0x2B, 0x12, 0xE6, 0xD0, 0xDB, 0x2C, 0xDC, 0xC3,
60 0x7F, 0xF0, 0x3E, 0x3A, 0x13, 0xA4, 0xDC, 0xE2,
61 0xF9, 0x6C, 0x54, 0xE2, 0xD8, 0xEA, 0xC8, 0x88,
62 0x00, 0x21, 0x86, 0x9C, 0x6A, 0xD8, 0xCB, 0x4E,
63 0x14, 0x6A, 0xF9, 0x4D, 0xD2, 0x7E, 0xB2, 0x32,
64 0x03, 0xC6, 0x14, 0x4B, 0x7F, 0xD1, 0xB8, 0xA6,
65 0x79, 0x7C, 0x17, 0xAC, 0xED, 0x06, 0xAD, 0xAF,
66 0x0A, 0x94, 0x7A, 0xBA, 0x03, 0xE7, 0x92, 0xD7,
67 0x15, 0x09, 0x73, 0xE8, 0x6D, 0x16, 0xEE, 0xE1,
68 0x3F, 0x78, 0x1F, 0x9D, 0x09, 0x52, 0x6E, 0xF1,
69 0x7C, 0x36, 0x2A, 0x71, 0x6C, 0x75, 0x64, 0x44,
70 0x80, 0x10, 0x43, 0x4E, 0x35, 0xEC, 0x65, 0x27,
71 0x0A, 0xB5, 0xFC, 0x26, 0x69, 0x3F, 0x59, 0x99,
72 0x01, 0x63, 0x8A, 0xA5, 0xBF, 0x68, 0x5C, 0xD3,
73 0x3C, 0xBE, 0x0B, 0xD6, 0x76, 0x83, 0xD6, 0x57,
74 0x05, 0x4A, 0x3D, 0xDD, 0x81, 0x73, 0xC9, 0xEB,
75 0x8A, 0x84, 0x39, 0xF4, 0x36, 0x0B, 0xF7};
76
77 /* TODO: fill correct prbs15 */
78 static const uint8_t prbs15[255] = { 0x00, };
79
80 static uint8_t tx_req;
81 static uint8_t volatile tx_ack;
82
isr_tx(void * param)83 static void isr_tx(void *param)
84 {
85 uint32_t l, i, s, t;
86
87 /* Clear radio status and events */
88 radio_status_reset();
89 radio_tmr_status_reset();
90
91 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
92 radio_gpio_pa_lna_disable();
93 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
94
95 /* Exit if radio disabled */
96 if (((tx_req - tx_ack) & 0x01) == 0U) {
97 tx_ack = tx_req;
98
99 return;
100 }
101
102 /* LE Test Packet Interval */
103 l = radio_tmr_end_get() - radio_tmr_ready_get();
104 i = DIV_ROUND_UP((l + 249), SCAN_INT_UNIT_US) * SCAN_INT_UNIT_US;
105 t = radio_tmr_end_get() - l + i;
106 t -= radio_tx_ready_delay_get(test_phy, test_phy_flags);
107
108 /* Set timer capture in the future. */
109 radio_tmr_sample();
110 s = radio_tmr_sample_get();
111 while (t < s) {
112 t += SCAN_INT_UNIT_US;
113 }
114
115 /* Setup next Tx */
116 radio_switch_complete_and_disable();
117 radio_tmr_start_us(1, t);
118 radio_tmr_aa_capture();
119 radio_tmr_end_capture();
120
121 /* TODO: check for probable stale timer capture being set */
122
123 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
124 radio_gpio_pa_setup();
125 radio_gpio_pa_lna_enable(t + radio_tx_ready_delay_get(test_phy,
126 test_phy_flags) -
127 HAL_RADIO_GPIO_PA_OFFSET);
128 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
129 }
130
isr_rx(void * param)131 static void isr_rx(void *param)
132 {
133 uint8_t crc_ok = 0U;
134 uint8_t trx_done;
135
136 /* Read radio status and events */
137 trx_done = radio_is_done();
138 if (trx_done) {
139 crc_ok = radio_crc_is_valid();
140 }
141
142 /* Clear radio status and events */
143 radio_status_reset();
144 radio_tmr_status_reset();
145
146 /* Exit if radio disabled */
147 if (!trx_done) {
148 return;
149 }
150
151 /* Setup next Rx */
152 radio_switch_complete_and_rx(test_phy);
153
154 /* Count Rx-ed packets */
155 if (crc_ok) {
156 test_num_rx++;
157 }
158 }
159
init(uint8_t chan,uint8_t phy,void (* isr)(void *))160 static uint8_t init(uint8_t chan, uint8_t phy, void (*isr)(void *))
161 {
162 int err;
163
164 if (started) {
165 return 1;
166 }
167
168 /* start coarse timer */
169 cntr_start();
170
171 /* Setup resources required by Radio */
172 err = lll_clk_on_wait();
173
174 /* Reset Radio h/w */
175 radio_reset();
176 radio_isr_set(isr, NULL);
177
178 /* Store value needed in Tx/Rx ISR */
179 if (phy < 0x04) {
180 test_phy = BIT(phy - 1);
181 test_phy_flags = 1U;
182 } else {
183 test_phy = BIT(2);
184 test_phy_flags = 0U;
185 }
186
187 /* Setup Radio in Tx/Rx */
188 /* NOTE: No whitening in test mode. */
189 radio_phy_set(test_phy, test_phy_flags);
190 radio_tmr_tifs_set(150);
191 radio_tx_power_max_set();
192 radio_freq_chan_set((chan << 1) + 2);
193 radio_aa_set((uint8_t *)&test_sync_word);
194 radio_crc_configure(0x65b, 0x555555);
195 radio_pkt_configure(8, 255, (test_phy << 1));
196
197 return 0;
198 }
199
ll_test_tx(uint8_t chan,uint8_t len,uint8_t type,uint8_t phy,uint8_t cte_len,uint8_t cte_type,uint8_t switch_pattern_len,const uint8_t * ant_id,int8_t tx_power)200 uint8_t ll_test_tx(uint8_t chan, uint8_t len, uint8_t type, uint8_t phy,
201 uint8_t cte_len, uint8_t cte_type, uint8_t switch_pattern_len,
202 const uint8_t *ant_id, int8_t tx_power)
203 {
204 uint32_t start_us;
205 uint8_t *payload;
206 uint8_t *pdu;
207 uint8_t err;
208
209 ARG_UNUSED(cte_len);
210 ARG_UNUSED(cte_type);
211 ARG_UNUSED(switch_pattern_len);
212 ARG_UNUSED(ant_id);
213 ARG_UNUSED(tx_power);
214
215 if ((type > 0x07) || !phy || (phy > 0x04)) {
216 return 1;
217 }
218
219 err = init(chan, phy, isr_tx);
220 if (err) {
221 return err;
222 }
223
224 tx_req++;
225
226 pdu = radio_pkt_scratch_get();
227 payload = &pdu[2];
228
229 switch (type) {
230 case 0x00:
231 memcpy(payload, prbs9, len);
232 break;
233
234 case 0x01:
235 memset(payload, 0x0f, len);
236 break;
237
238 case 0x02:
239 memset(payload, 0x55, len);
240 break;
241
242 case 0x03:
243 memcpy(payload, prbs15, len);
244 break;
245
246 case 0x04:
247 memset(payload, 0xff, len);
248 break;
249
250 case 0x05:
251 memset(payload, 0x00, len);
252 break;
253
254 case 0x06:
255 memset(payload, 0xf0, len);
256 break;
257
258 case 0x07:
259 memset(payload, 0xaa, len);
260 break;
261 }
262
263 pdu[0] = type;
264 pdu[1] = len;
265
266 radio_pkt_tx_set(pdu);
267 radio_switch_complete_and_disable();
268 start_us = radio_tmr_start(1, cntr_cnt_get() + CNTR_MIN_DELTA, 0);
269 radio_tmr_aa_capture();
270 radio_tmr_end_capture();
271
272 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
273 radio_gpio_pa_setup();
274 radio_gpio_pa_lna_enable(start_us +
275 radio_tx_ready_delay_get(test_phy,
276 test_phy_flags) -
277 HAL_RADIO_GPIO_PA_OFFSET);
278 #else /* !HAL_RADIO_GPIO_HAVE_PA_PIN */
279 ARG_UNUSED(start_us);
280 #endif /* !HAL_RADIO_GPIO_HAVE_PA_PIN */
281
282 started = true;
283
284 return 0;
285 }
286
ll_test_rx(uint8_t chan,uint8_t phy,uint8_t mod_idx,uint8_t expected_cte_len,uint8_t expected_cte_type,uint8_t slot_duration,uint8_t switch_pattern_len,const uint8_t * ant_ids)287 uint8_t ll_test_rx(uint8_t chan, uint8_t phy, uint8_t mod_idx, uint8_t expected_cte_len,
288 uint8_t expected_cte_type, uint8_t slot_duration, uint8_t switch_pattern_len,
289 const uint8_t *ant_ids)
290 {
291 uint8_t err;
292
293 if (!phy || (phy > 0x03)) {
294 return 1;
295 }
296
297 ARG_UNUSED(expected_cte_len);
298 ARG_UNUSED(expected_cte_type);
299 ARG_UNUSED(slot_duration);
300 ARG_UNUSED(switch_pattern_len);
301 ARG_UNUSED(ant_ids);
302
303 err = init(chan, phy, isr_rx);
304 if (err) {
305 return err;
306 }
307
308 radio_pkt_rx_set(radio_pkt_scratch_get());
309 radio_switch_complete_and_rx(test_phy);
310 radio_tmr_start(0, cntr_cnt_get() + CNTR_MIN_DELTA, 0);
311
312 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
313 radio_gpio_lna_on();
314 #endif /* !HAL_RADIO_GPIO_HAVE_LNA_PIN */
315
316 started = true;
317
318 return 0;
319 }
320
ll_test_end(uint16_t * num_rx)321 uint8_t ll_test_end(uint16_t *num_rx)
322 {
323 int err;
324 uint8_t ack;
325
326 if (!started) {
327 return 1;
328 }
329
330 /* Return packets Rx-ed/Completed */
331 *num_rx = test_num_rx;
332 test_num_rx = 0U;
333
334 /* Disable Radio, if in Rx test */
335 ack = tx_ack;
336 if (tx_req == ack) {
337 radio_disable();
338 } else {
339 /* Wait for Tx to complete */
340 tx_req = ack + 2;
341 while (tx_req != tx_ack) {
342 cpu_sleep();
343 }
344 }
345
346 /* Stop packet timer */
347 radio_tmr_stop();
348
349 /* Release resources acquired for Radio */
350 err = lll_clk_off();
351 LL_ASSERT(!err || err == -EBUSY);
352
353 /* Stop coarse timer */
354 cntr_stop();
355
356 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
357 radio_gpio_lna_off();
358 #endif /* !HAL_RADIO_GPIO_HAVE_LNA_PIN */
359
360 started = false;
361
362 return 0;
363 }
364
