1 /*
2 * Copyright (c) 2016-2021 Nordic Semiconductor ASA
3 * Copyright (c) 2016 Vinayak Kariappa Chettimada
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/kernel.h>
9
cpu_sleep(void)10 static inline void cpu_sleep(void)
11 {
12 k_cpu_atomic_idle(irq_lock());
13 }
14
cpu_dmb(void)15 static inline void cpu_dmb(void)
16 {
17 #if defined(CONFIG_CPU_CORTEX_M)
18 /* NOTE: Refer to ARM Cortex-M Programming Guide to Memory Barrier
19 * Instructions, Section 4.1 Normal access in memories
20 *
21 * Implementation: In the Cortex-M processors data transfers are
22 * carried out in the programmed order.
23 *
24 * Hence, there is no need to use a memory barrier instruction between
25 * each access. Only a compiler memory clobber is sufficient.
26 */
27 __asm__ volatile ("" : : : "memory");
28 #elif defined(CONFIG_ARCH_POSIX)
29 /* FIXME: Add necessary host machine required Data Memory Barrier
30 * instruction alongwith the below defined compiler memory
31 * clobber.
32 */
33 __asm__ volatile ("" : : : "memory");
34 #else
35 #error "Unsupported CPU."
36 #endif
37 }
38
