1 /*
2  * Copyright (c) 2018 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32WB processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <zephyr/logging/log.h>
15 
16 #include <stm32_ll_system.h>
17 
18 #include <cmsis_core.h>
19 
20 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
21 LOG_MODULE_REGISTER(soc);
22 
23 extern void stm32_pm_init(void);
24 /**
25  * @brief Perform basic hardware initialization at boot.
26  *
27  * This needs to be run from the very beginning.
28  */
soc_early_init_hook(void)29 void soc_early_init_hook(void)
30 {
31 	/* Enable the ART Accelerator I-cache, D-cache and prefetch */
32 	LL_FLASH_EnableInstCache();
33 	LL_FLASH_EnableDataCache();
34 	LL_FLASH_EnablePrefetch();
35 
36 	/* Update CMSIS SystemCoreClock variable (HCLK) */
37 	/* At reset, system core clock is set to 4 MHz from MSI */
38 	SystemCoreClock = 4000000;
39 
40 	/* Set C2 Power Mode to shutdown */
41 	/* It will be updated by C2 when required */
42 	LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
43 #if CONFIG_PM
44 	stm32_pm_init();
45 #endif
46 
47 }
48