1 /*
2  * Copyright (c) 2023 STMicroelectronics
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief System/hardware module for STM32WBA processor
10  */
11 
12 #include <zephyr/device.h>
13 #include <zephyr/init.h>
14 #include <stm32_ll_bus.h>
15 #include <stm32_ll_pwr.h>
16 #include <stm32_ll_rcc.h>
17 #include <stm32_ll_icache.h>
18 #include <zephyr/arch/cpu.h>
19 #include <zephyr/irq.h>
20 #include <zephyr/logging/log.h>
21 #include "soc.h"
22 #include <cmsis_core.h>
23 
24 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
25 LOG_MODULE_REGISTER(soc);
26 
27 /**
28  * @brief Perform basic hardware initialization at boot.
29  *
30  * This needs to be run from the very beginning.
31  */
stm32wba_init(void)32 void stm32wba_init(void)
33 {
34 	/* Enable instruction cache in 1-way (direct mapped cache) */
35 	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
36 	LL_ICACHE_Enable();
37 #ifdef CONFIG_STM32_FLASH_PREFETCH
38 	__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
39 #endif
40 
41 	/* Update CMSIS SystemCoreClock variable (HCLK) */
42 	/* At reset, system core clock is set to 16 MHz from HSI */
43 	SystemCoreClock = 16000000;
44 
45 	/* Enable PWR */
46 	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
47 
48 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
49 	LL_PWR_SetRegulatorSupply(LL_PWR_SMPS_SUPPLY);
50 #elif defined(CONFIG_POWER_SUPPLY_LDO)
51 	LL_PWR_SetRegulatorSupply(LL_PWR_LDO_SUPPLY);
52 #endif
53 }
54 
soc_early_init_hook(void)55 void soc_early_init_hook(void)
56 {
57 	stm32wba_init();
58 #if CONFIG_PM
59 	stm32_power_init();
60 #endif
61 }
62