1 /* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief System/hardware module for STM32H5 processor 10 */ 11 12 #include <zephyr/device.h> 13 #include <zephyr/init.h> 14 #include <stm32_ll_bus.h> 15 #include <stm32_ll_pwr.h> 16 #include <stm32_ll_icache.h> 17 #include <zephyr/logging/log.h> 18 19 #include <cmsis_core.h> 20 21 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL 22 LOG_MODULE_REGISTER(soc); 23 24 extern void stm32_power_init(void); 25 /** 26 * @brief Perform basic hardware initialization at boot. 27 * 28 * This needs to be run from the very beginning. 29 */ soc_early_init_hook(void)30void soc_early_init_hook(void) 31 { 32 /* Enable instruction cache in 1-way (direct mapped cache) */ 33 LL_ICACHE_SetMode(LL_ICACHE_1WAY); 34 LL_ICACHE_Enable(); 35 36 /* Update CMSIS SystemCoreClock variable (HCLK) */ 37 /* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */ 38 SystemCoreClock = 32000000; 39 40 #if defined(PWR_UCPDR_UCPD_DBDIS) 41 if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) || 42 !IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) { 43 /* Disable USB Type-C dead battery pull-down behavior */ 44 LL_PWR_DisableUCPDDeadBattery(); 45 } 46 47 #endif /* PWR_UCPDR_UCPD_DBDIS */ 48 49 #if CONFIG_PM 50 stm32_power_init(); 51 #endif 52 } 53
